Bugzilla – Attachment 131491 Details for
Bug 101176
[IGT] gem_workarounds@basic-read Test assertion failure
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kern.log
kern.log (text/plain), 9.52 MB, created by
Humberto Israel Perez Rodriguez
on 2017-05-24 20:11:00 UTC
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hide
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Description:
kern.log
Filename:
MIME Type:
Creator:
Humberto Israel Perez Rodriguez
Created:
2017-05-24 20:11:00 UTC
Size:
9.52 MB
patch
obsolete
>May 24 03:26:52 BXT-2 kernel: [ 311.499452] Console: switching to colour frame buffer device 128x48 >May 24 03:26:52 BXT-2 kernel: [ 311.715393] Console: switching to colour dummy device 80x25 >May 24 03:26:52 BXT-2 kernel: [ 311.832875] Console: switching to colour frame buffer device 128x48 >May 24 03:26:53 BXT-2 kernel: [ 312.028613] Console: switching to colour dummy device 80x25 >May 24 03:26:53 BXT-2 kernel: [ 312.132801] Console: switching to colour frame buffer device 128x48 >May 24 03:26:53 BXT-2 kernel: [ 312.327400] Console: switching to colour dummy device 80x25 >May 24 03:26:54 BXT-2 kernel: [ 313.432827] Console: switching to colour frame buffer device 128x48 >May 24 03:26:54 BXT-2 kernel: [ 313.625203] Console: switching to colour dummy device 80x25 >May 24 03:26:55 BXT-2 kernel: [ 314.716192] Console: switching to colour frame buffer device 128x48 >May 24 03:26:55 BXT-2 kernel: [ 314.923162] Console: switching to colour dummy device 80x25 >May 24 03:26:59 BXT-2 kernel: [ 318.761562] [drm:missed_breadcrumb [i915]] rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes, current seqno=567d, last=5680 >May 24 03:27:04 BXT-2 kernel: [ 323.762399] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_exec_fence [14273], reason: Hang on rcs0, action: reset >May 24 03:27:04 BXT-2 kernel: [ 323.763298] [drm:i915_reset_and_wakeup [i915]] resetting chip >May 24 03:27:04 BXT-2 kernel: [ 323.763418] drm/i915: Resetting chip after gpu hang >May 24 03:27:04 BXT-2 kernel: [ 323.764809] [drm:i915_gem_reset [i915]] context gem_exec_fence[14273]/0 marked guilty (score 10) banned? no >May 24 03:27:04 BXT-2 kernel: [ 323.764864] [drm:i915_gem_reset [i915]] resetting rcs0 to restart from tail of request 0x567e >May 24 03:27:04 BXT-2 kernel: [ 323.765137] [drm] RC6 on >May 24 03:27:04 BXT-2 kernel: [ 323.765616] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:27:04 BXT-2 kernel: [ 323.765675] [drm:gen8_init_common_ring [i915]] Restarting rcs0:0 from 0x5680 >May 24 03:27:04 BXT-2 kernel: [ 323.765753] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:27:04 BXT-2 kernel: [ 323.765890] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:27:04 BXT-2 kernel: [ 323.766100] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:27:04 BXT-2 kernel: [ 323.766238] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:27:04 BXT-2 kernel: [ 323.833143] Console: switching to colour frame buffer device 128x48 >May 24 03:27:05 BXT-2 kernel: [ 324.027261] Console: switching to colour dummy device 80x25 >May 24 03:27:10 BXT-2 kernel: [ 329.866358] Console: switching to colour frame buffer device 128x48 >May 24 03:27:11 BXT-2 kernel: [ 330.240307] Console: switching to colour dummy device 80x25 >May 24 03:27:16 BXT-2 kernel: [ 335.966416] Console: switching to colour frame buffer device 128x48 >May 24 03:27:17 BXT-2 kernel: [ 336.147274] Console: switching to colour dummy device 80x25 >May 24 03:27:17 BXT-2 kernel: [ 336.216425] Console: switching to colour frame buffer device 128x48 >May 24 03:27:17 BXT-2 kernel: [ 336.402830] Console: switching to colour dummy device 80x25 >May 24 03:27:22 BXT-2 kernel: [ 341.883268] Console: switching to colour frame buffer device 128x48 >May 24 03:27:23 BXT-2 kernel: [ 342.072645] Console: switching to colour dummy device 80x25 >May 24 03:27:28 BXT-2 kernel: [ 347.533258] Console: switching to colour frame buffer device 128x48 >May 24 03:27:28 BXT-2 kernel: [ 347.720557] Console: switching to colour dummy device 80x25 >May 24 03:27:34 BXT-2 kernel: [ 353.183250] Console: switching to colour frame buffer device 128x48 >May 24 03:27:34 BXT-2 kernel: [ 353.402435] Console: switching to colour dummy device 80x25 >May 24 03:27:39 BXT-2 kernel: [ 358.883309] Console: switching to colour frame buffer device 128x48 >May 24 03:27:40 BXT-2 kernel: [ 359.072791] Console: switching to colour dummy device 80x25 >May 24 03:27:45 BXT-2 kernel: [ 364.550170] Console: switching to colour frame buffer device 128x48 >May 24 03:27:45 BXT-2 kernel: [ 364.752665] Console: switching to colour dummy device 80x25 >May 24 03:27:51 BXT-2 kernel: [ 370.216769] Console: switching to colour frame buffer device 128x48 >May 24 03:27:51 BXT-2 kernel: [ 370.413370] Console: switching to colour dummy device 80x25 >May 24 03:27:56 BXT-2 kernel: [ 375.866857] Console: switching to colour frame buffer device 128x48 >May 24 03:27:57 BXT-2 kernel: [ 376.062779] Console: switching to colour dummy device 80x25 >May 24 03:28:02 BXT-2 kernel: [ 381.533644] Console: switching to colour frame buffer device 128x48 >May 24 03:28:02 BXT-2 kernel: [ 381.758079] Console: switching to colour dummy device 80x25 >May 24 03:28:08 BXT-2 kernel: [ 387.217042] Console: switching to colour frame buffer device 128x48 >May 24 03:28:08 BXT-2 kernel: [ 387.401665] Console: switching to colour dummy device 80x25 >May 24 03:28:13 BXT-2 kernel: [ 392.878695] Console: switching to colour frame buffer device 128x48 >May 24 03:28:14 BXT-2 kernel: [ 393.067575] Console: switching to colour dummy device 80x25 >May 24 03:28:19 BXT-2 kernel: [ 398.545490] Console: switching to colour frame buffer device 128x48 >May 24 03:28:19 BXT-2 kernel: [ 398.738025] Console: switching to colour dummy device 80x25 >May 24 03:28:25 BXT-2 kernel: [ 404.195470] Console: switching to colour frame buffer device 128x48 >May 24 03:28:25 BXT-2 kernel: [ 404.387063] Console: switching to colour dummy device 80x25 >May 24 03:28:25 BXT-2 kernel: [ 404.406480] gem_exec_gttfil (16173): drop_caches: 4 >May 24 03:28:39 BXT-2 kernel: [ 418.450673] Console: switching to colour frame buffer device 128x48 >May 24 03:28:39 BXT-2 kernel: [ 418.622713] Console: switching to colour dummy device 80x25 >May 24 03:28:49 BXT-2 kernel: [ 428.200861] Console: switching to colour frame buffer device 128x48 >May 24 03:28:49 BXT-2 kernel: [ 428.625029] Console: switching to colour dummy device 80x25 >May 24 03:28:59 BXT-2 kernel: [ 438.134221] Console: switching to colour frame buffer device 128x48 >May 24 03:28:59 BXT-2 kernel: [ 438.347010] Console: switching to colour dummy device 80x25 >May 24 03:29:02 BXT-2 kernel: [ 441.150960] Console: switching to colour frame buffer device 128x48 >May 24 03:29:02 BXT-2 kernel: [ 441.351652] Console: switching to colour dummy device 80x25 >May 24 03:29:02 BXT-2 kernel: [ 441.412459] Console: switching to colour frame buffer device 128x48 >May 24 03:29:02 BXT-2 kernel: [ 441.600055] Console: switching to colour dummy device 80x25 >May 24 03:29:02 BXT-2 kernel: [ 441.650973] Console: switching to colour frame buffer device 128x48 >May 24 03:29:02 BXT-2 kernel: [ 441.835098] Console: switching to colour dummy device 80x25 >May 24 03:29:02 BXT-2 kernel: [ 441.950954] Console: switching to colour frame buffer device 128x48 >May 24 03:29:03 BXT-2 kernel: [ 442.134823] Console: switching to colour dummy device 80x25 >May 24 03:29:03 BXT-2 kernel: [ 442.262433] Console: switching to colour frame buffer device 128x48 >May 24 03:29:03 BXT-2 kernel: [ 442.442475] Console: switching to colour dummy device 80x25 >May 24 03:29:03 BXT-2 kernel: [ 442.551039] Console: switching to colour frame buffer device 128x48 >May 24 03:29:03 BXT-2 kernel: [ 442.733076] Console: switching to colour dummy device 80x25 >May 24 03:29:03 BXT-2 kernel: [ 442.800972] Console: switching to colour frame buffer device 128x48 >May 24 03:29:03 BXT-2 kernel: [ 442.982364] Console: switching to colour dummy device 80x25 >May 24 03:29:04 BXT-2 kernel: [ 443.067604] Console: switching to colour frame buffer device 128x48 >May 24 03:29:04 BXT-2 kernel: [ 443.259200] Console: switching to colour dummy device 80x25 >May 24 03:29:04 BXT-2 kernel: [ 443.367608] Console: switching to colour frame buffer device 128x48 >May 24 03:29:04 BXT-2 kernel: [ 443.546098] Console: switching to colour dummy device 80x25 >May 24 03:29:04 BXT-2 kernel: [ 443.662418] Console: switching to colour frame buffer device 128x48 >May 24 03:29:04 BXT-2 kernel: [ 443.857786] Console: switching to colour dummy device 80x25 >May 24 03:29:05 BXT-2 kernel: [ 443.979254] Console: switching to colour frame buffer device 128x48 >May 24 03:29:05 BXT-2 kernel: [ 444.152465] Console: switching to colour dummy device 80x25 >May 24 03:29:05 BXT-2 kernel: [ 444.534321] Console: switching to colour frame buffer device 128x48 >May 24 03:29:05 BXT-2 kernel: [ 444.719160] Console: switching to colour dummy device 80x25 >May 24 03:29:07 BXT-2 kernel: [ 446.374083] PM: Syncing filesystems ... done. >May 24 03:29:07 BXT-2 kernel: [ 446.382659] PM: Preparing system for sleep (mem) >May 24 03:29:23 BXT-2 kernel: [ 446.421836] Freezing user space processes ... (elapsed 0.005 seconds) done. >May 24 03:29:23 BXT-2 kernel: [ 446.427389] OOM killer disabled. >May 24 03:29:23 BXT-2 kernel: [ 446.427393] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 03:29:23 BXT-2 kernel: [ 446.429258] PM: Suspending system (mem) >May 24 03:29:23 BXT-2 kernel: [ 446.429572] Suspending console(s) (use no_console_suspend to debug) >May 24 03:29:23 BXT-2 kernel: [ 446.562670] sd 0:0:0:0: [sda] Synchronizing SCSI cache >May 24 03:29:23 BXT-2 kernel: [ 446.564541] system 00:00: System wakeup disabled by ACPI >May 24 03:29:23 BXT-2 kernel: [ 446.565457] ACPI : EC: event blocked >May 24 03:29:23 BXT-2 kernel: [ 446.571335] sd 0:0:0:0: [sda] Stopping disk >May 24 03:29:23 BXT-2 kernel: [ 446.581127] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:29:23 BXT-2 kernel: [ 446.610710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:29:23 BXT-2 kernel: [ 446.615849] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:29:23 BXT-2 kernel: [ 446.616891] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:29:23 BXT-2 kernel: [ 446.636897] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:29:23 BXT-2 kernel: [ 446.638841] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:29:23 BXT-2 kernel: [ 446.640651] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:29:23 BXT-2 kernel: [ 446.647536] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:29:23 BXT-2 kernel: [ 446.648737] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:29:23 BXT-2 kernel: [ 446.649800] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 446.650876] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 446.651149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:29:23 BXT-2 kernel: [ 446.651303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:29:23 BXT-2 kernel: [ 446.651459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:29:23 BXT-2 kernel: [ 446.651609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:29:23 BXT-2 kernel: [ 446.651761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:29:23 BXT-2 kernel: [ 446.651913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:29:23 BXT-2 kernel: [ 446.652078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:29:23 BXT-2 kernel: [ 446.652227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:29:23 BXT-2 kernel: [ 446.652378] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:23 BXT-2 kernel: [ 446.652640] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:23 BXT-2 kernel: [ 446.652792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:29:23 BXT-2 kernel: [ 446.653176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:23 BXT-2 kernel: [ 446.653326] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:23 BXT-2 kernel: [ 446.653860] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:29:23 BXT-2 kernel: [ 446.654581] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:29:23 BXT-2 kernel: [ 447.276261] hpet1: lost 7161 rtc interrupts >May 24 03:29:23 BXT-2 kernel: [ 448.164882] hpet1: lost 7161 rtc interrupts >May 24 03:29:23 BXT-2 kernel: [ 448.220380] PM: suspend of devices complete after 1663.047 msecs >May 24 03:29:23 BXT-2 kernel: [ 448.231723] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:29:23 BXT-2 kernel: [ 448.231791] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:29:23 BXT-2 kernel: [ 448.231829] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.232042] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.232082] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:29:23 BXT-2 kernel: [ 448.232124] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:29:23 BXT-2 kernel: [ 448.232162] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:29:23 BXT-2 kernel: [ 448.232707] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:29:23 BXT-2 kernel: [ 448.232749] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:29:23 BXT-2 kernel: [ 448.233101] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.233137] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:29:23 BXT-2 kernel: [ 448.233181] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:29:23 BXT-2 kernel: [ 448.233223] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:29:23 BXT-2 kernel: [ 448.233267] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:29:23 BXT-2 kernel: [ 448.233310] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:29:23 BXT-2 kernel: [ 448.245239] PM: late suspend of devices complete after 24.847 msecs >May 24 03:29:23 BXT-2 kernel: [ 448.249242] ACPI : EC: interrupt blocked >May 24 03:29:23 BXT-2 kernel: [ 448.249512] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI >May 24 03:29:23 BXT-2 kernel: [ 448.249601] r8169 0000:03:00.0: System wakeup enabled by ACPI >May 24 03:29:23 BXT-2 kernel: [ 448.273006] PM: noirq suspend of devices complete after 27.757 msecs >May 24 03:29:23 BXT-2 kernel: [ 448.273182] ACPI: Preparing to enter system sleep state S3 >May 24 03:29:23 BXT-2 kernel: [ 448.276572] ACPI : EC: EC stopped >May 24 03:29:23 BXT-2 kernel: [ 448.276579] PM: Saving platform NVS memory >May 24 03:29:23 BXT-2 kernel: [ 448.276636] Disabling non-boot CPUs ... >May 24 03:29:23 BXT-2 kernel: [ 448.297645] Broke affinity for irq 369 >May 24 03:29:23 BXT-2 kernel: [ 448.297656] Broke affinity for irq 371 >May 24 03:29:23 BXT-2 kernel: [ 448.297667] Broke affinity for irq 373 >May 24 03:29:23 BXT-2 kernel: [ 448.299296] smpboot: CPU 1 is now offline >May 24 03:29:23 BXT-2 kernel: [ 448.320383] Broke affinity for irq 369 >May 24 03:29:23 BXT-2 kernel: [ 448.320394] Broke affinity for irq 371 >May 24 03:29:23 BXT-2 kernel: [ 448.320405] Broke affinity for irq 372 >May 24 03:29:23 BXT-2 kernel: [ 448.320414] Broke affinity for irq 373 >May 24 03:29:23 BXT-2 kernel: [ 448.321551] smpboot: CPU 2 is now offline >May 24 03:29:23 BXT-2 kernel: [ 448.335852] Broke affinity for irq 1 >May 24 03:29:23 BXT-2 kernel: [ 448.335866] Broke affinity for irq 8 >May 24 03:29:23 BXT-2 kernel: [ 448.335876] Broke affinity for irq 9 >May 24 03:29:23 BXT-2 kernel: [ 448.335887] Broke affinity for irq 12 >May 24 03:29:23 BXT-2 kernel: [ 448.335897] Broke affinity for irq 14 >May 24 03:29:23 BXT-2 kernel: [ 448.336058] Broke affinity for irq 367 >May 24 03:29:23 BXT-2 kernel: [ 448.336067] Broke affinity for irq 368 >May 24 03:29:23 BXT-2 kernel: [ 448.336076] Broke affinity for irq 369 >May 24 03:29:23 BXT-2 kernel: [ 448.336085] Broke affinity for irq 370 >May 24 03:29:23 BXT-2 kernel: [ 448.336094] Broke affinity for irq 371 >May 24 03:29:23 BXT-2 kernel: [ 448.336103] Broke affinity for irq 372 >May 24 03:29:23 BXT-2 kernel: [ 448.336112] Broke affinity for irq 373 >May 24 03:29:23 BXT-2 kernel: [ 448.337281] smpboot: CPU 3 is now offline >May 24 03:29:23 BXT-2 kernel: [ 448.348572] ACPI: Low-level resume complete >May 24 03:29:23 BXT-2 kernel: [ 448.349153] ACPI : EC: EC started >May 24 03:29:23 BXT-2 kernel: [ 448.349164] PM: Restoring platform NVS memory >May 24 03:29:23 BXT-2 kernel: [ 448.350881] Suspended for 13.650 seconds >May 24 03:29:23 BXT-2 kernel: [ 448.355471] Enabling non-boot CPUs ... >May 24 03:29:23 BXT-2 kernel: [ 448.357310] x86: Booting SMP configuration: >May 24 03:29:23 BXT-2 kernel: [ 448.357389] smpboot: Booting Node 0 Processor 1 APIC 0x2 >May 24 03:29:23 BXT-2 kernel: [ 448.370390] cache: parent cpu1 should not be sleeping >May 24 03:29:23 BXT-2 kernel: [ 448.373002] CPU1 is up >May 24 03:29:23 BXT-2 kernel: [ 448.373223] smpboot: Booting Node 0 Processor 2 APIC 0x4 >May 24 03:29:23 BXT-2 kernel: [ 448.381747] cache: parent cpu2 should not be sleeping >May 24 03:29:23 BXT-2 kernel: [ 448.385079] CPU2 is up >May 24 03:29:23 BXT-2 kernel: [ 448.385287] smpboot: Booting Node 0 Processor 3 APIC 0x6 >May 24 03:29:23 BXT-2 kernel: [ 448.393714] cache: parent cpu3 should not be sleeping >May 24 03:29:23 BXT-2 kernel: [ 448.397596] CPU3 is up >May 24 03:29:23 BXT-2 kernel: [ 448.402180] ACPI: Waking up from system sleep state S3 >May 24 03:29:23 BXT-2 kernel: [ 448.411920] ACPI : EC: interrupt unblocked >May 24 03:29:23 BXT-2 kernel: [ 448.413840] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI >May 24 03:29:23 BXT-2 kernel: [ 448.435749] PM: noirq resume of devices complete after 25.614 msecs >May 24 03:29:23 BXT-2 kernel: [ 448.436529] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00 >May 24 03:29:23 BXT-2 kernel: [ 448.436590] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:29:23 BXT-2 kernel: [ 448.436648] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:29:23 BXT-2 kernel: [ 448.436772] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 03:29:23 BXT-2 kernel: [ 448.437156] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:29:23 BXT-2 kernel: [ 448.437252] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:29:23 BXT-2 kernel: [ 448.437349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.437426] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:29:23 BXT-2 kernel: [ 448.439774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.441899] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:29:23 BXT-2 kernel: [ 448.441964] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:29:23 BXT-2 kernel: [ 448.442033] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:29:23 BXT-2 kernel: [ 448.442115] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.442188] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:29:23 BXT-2 kernel: [ 448.443934] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:29:23 BXT-2 kernel: [ 448.450470] PM: early resume of devices complete after 14.232 msecs >May 24 03:29:23 BXT-2 kernel: [ 448.451117] ACPI : EC: event unblocked >May 24 03:29:23 BXT-2 kernel: [ 448.453163] r8169 0000:03:00.0: System wakeup disabled by ACPI >May 24 03:29:23 BXT-2 kernel: [ 448.453353] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 03:29:23 BXT-2 kernel: [ 448.461184] sd 0:0:0:0: [sda] Starting disk >May 24 03:29:23 BXT-2 kernel: [ 448.467222] r8169 0000:03:00.0 enp3s0: link down >May 24 03:29:23 BXT-2 kernel: [ 448.561456] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:29:23 BXT-2 kernel: [ 448.561580] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:29:23 BXT-2 kernel: [ 448.561622] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:29:23 BXT-2 kernel: [ 448.561712] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:29:23 BXT-2 kernel: [ 448.561837] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38 >May 24 03:29:23 BXT-2 kernel: [ 448.562374] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:29:23 BXT-2 kernel: [ 448.562491] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:29:23 BXT-2 kernel: [ 448.562598] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:29:23 BXT-2 kernel: [ 448.562705] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:29:23 BXT-2 kernel: [ 448.562812] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:29:23 BXT-2 kernel: [ 448.563713] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.563816] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:29:23 BXT-2 kernel: [ 448.563964] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.564009] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:29:23 BXT-2 kernel: [ 448.564062] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.564104] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:29:23 BXT-2 kernel: [ 448.564157] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.564199] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:29:23 BXT-2 kernel: [ 448.564250] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:29:23 BXT-2 kernel: [ 448.564295] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:29:23 BXT-2 kernel: [ 448.564340] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:29:23 BXT-2 kernel: [ 448.564389] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:29:23 BXT-2 kernel: [ 448.564432] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:29:23 BXT-2 kernel: [ 448.564497] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:29:23 BXT-2 kernel: [ 448.564540] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:29:23 BXT-2 kernel: [ 448.564588] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:29:23 BXT-2 kernel: [ 448.564632] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:29:23 BXT-2 kernel: [ 448.564676] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:29:23 BXT-2 kernel: [ 448.564720] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:29:23 BXT-2 kernel: [ 448.564827] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:29:23 BXT-2 kernel: [ 448.564889] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:29:23 BXT-2 kernel: [ 448.564942] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:29:23 BXT-2 kernel: [ 448.564987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565028] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565069] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:23 BXT-2 kernel: [ 448.565078] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565121] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:23 BXT-2 kernel: [ 448.565125] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565167] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565211] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565253] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:23 BXT-2 kernel: [ 448.565336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565382] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565424] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:23 BXT-2 kernel: [ 448.565492] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.565534] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.565578] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.565621] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.565666] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:29:23 BXT-2 kernel: [ 448.565707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565748] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565789] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:23 BXT-2 kernel: [ 448.565794] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565835] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:23 BXT-2 kernel: [ 448.565840] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565882] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.565923] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:29:23 BXT-2 kernel: [ 448.565967] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:23 BXT-2 kernel: [ 448.566049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566092] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.566133] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:23 BXT-2 kernel: [ 448.566178] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.566222] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.566265] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.566309] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.566353] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:29:23 BXT-2 kernel: [ 448.566394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566452] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566493] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:23 BXT-2 kernel: [ 448.566497] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.566538] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:23 BXT-2 kernel: [ 448.566543] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.566585] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.566627] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566668] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:23 BXT-2 kernel: [ 448.566751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.566793] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.566834] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:23 BXT-2 kernel: [ 448.566878] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.566923] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.566967] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.567175] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:29:23 BXT-2 kernel: [ 448.567291] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:29:23 BXT-2 kernel: [ 448.567331] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.567517] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.567558] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:29:23 BXT-2 kernel: [ 448.567602] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:29:23 BXT-2 kernel: [ 448.567645] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:29:23 BXT-2 kernel: [ 448.568190] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:29:23 BXT-2 kernel: [ 448.568285] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:29:23 BXT-2 kernel: [ 448.568327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:29:23 BXT-2 kernel: [ 448.568375] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:29:23 BXT-2 kernel: [ 448.568419] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:29:23 BXT-2 kernel: [ 448.568478] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:29:23 BXT-2 kernel: [ 448.568524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.568566] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:29:23 BXT-2 kernel: [ 448.568608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.568650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:29:23 BXT-2 kernel: [ 448.568691] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.568732] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:23 BXT-2 kernel: [ 448.568739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:23 BXT-2 kernel: [ 448.568780] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:23 BXT-2 kernel: [ 448.568785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:23 BXT-2 kernel: [ 448.568828] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:29:23 BXT-2 kernel: [ 448.568870] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:29:23 BXT-2 kernel: [ 448.568912] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:29:23 BXT-2 kernel: [ 448.568953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:23 BXT-2 kernel: [ 448.568995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.569038] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:29:23 BXT-2 kernel: [ 448.569079] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:23 BXT-2 kernel: [ 448.569122] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.569165] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.569207] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.569248] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.569294] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:29:23 BXT-2 kernel: [ 448.569336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:29:23 BXT-2 kernel: [ 448.569380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:29:23 BXT-2 kernel: [ 448.569423] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:29:23 BXT-2 kernel: [ 448.569483] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:29:23 BXT-2 kernel: [ 448.569525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.569567] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:29:23 BXT-2 kernel: [ 448.569608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.569650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:29:23 BXT-2 kernel: [ 448.569692] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.569733] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:23 BXT-2 kernel: [ 448.569738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:23 BXT-2 kernel: [ 448.569781] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:23 BXT-2 kernel: [ 448.569786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:23 BXT-2 kernel: [ 448.569828] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:29:23 BXT-2 kernel: [ 448.569870] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:29:23 BXT-2 kernel: [ 448.569912] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:29:23 BXT-2 kernel: [ 448.569953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:23 BXT-2 kernel: [ 448.569995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:23 BXT-2 kernel: [ 448.570038] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:29:23 BXT-2 kernel: [ 448.570079] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:23 BXT-2 kernel: [ 448.570121] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.570162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.570204] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.570245] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:29:23 BXT-2 kernel: [ 448.570291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.570345] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:29:23 BXT-2 kernel: [ 448.570389] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:29:23 BXT-2 kernel: [ 448.570449] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:29:23 BXT-2 kernel: [ 448.570493] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:29:23 BXT-2 kernel: [ 448.570537] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:29:23 BXT-2 kernel: [ 448.570731] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:29:23 BXT-2 kernel: [ 448.570767] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:29:23 BXT-2 kernel: [ 448.571056] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:29:23 BXT-2 kernel: [ 448.571108] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.571147] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:29:23 BXT-2 kernel: [ 448.571277] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:29:23 BXT-2 kernel: [ 448.573534] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.573847] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:23 BXT-2 kernel: [ 448.573892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:29:23 BXT-2 kernel: [ 448.573936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:29:23 BXT-2 kernel: [ 448.573979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:29:23 BXT-2 kernel: [ 448.574022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:29:23 BXT-2 kernel: [ 448.574064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:29:23 BXT-2 kernel: [ 448.574106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:29:23 BXT-2 kernel: [ 448.574150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:29:23 BXT-2 kernel: [ 448.574193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:29:23 BXT-2 kernel: [ 448.574237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:29:23 BXT-2 kernel: [ 448.574283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:23 BXT-2 kernel: [ 448.574329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:23 BXT-2 kernel: [ 448.574401] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:29:23 BXT-2 kernel: [ 448.574464] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:29:23 BXT-2 kernel: [ 448.577244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:23 BXT-2 kernel: [ 448.577288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:23 BXT-2 kernel: [ 448.577333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:29:23 BXT-2 kernel: [ 448.613522] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -5 >May 24 03:29:23 BXT-2 kernel: [ 448.613617] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training >May 24 03:29:23 BXT-2 kernel: [ 448.613680] [drm:intel_dp_start_link_train [i915]] Link Training failed at link rate = 162000, lane count = 4 >May 24 03:29:23 BXT-2 kernel: [ 448.613929] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:23 BXT-2 kernel: [ 448.615631] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:29:23 BXT-2 kernel: [ 448.615856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:29:23 BXT-2 kernel: [ 448.615919] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:29:23 BXT-2 kernel: [ 448.616015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:29:23 BXT-2 kernel: [ 448.616381] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:29:23 BXT-2 kernel: [ 448.616444] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:29:23 BXT-2 kernel: [ 448.617986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:23 BXT-2 kernel: [ 448.618047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:23 BXT-2 kernel: [ 448.618111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:29:23 BXT-2 kernel: [ 448.618962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:23 BXT-2 kernel: [ 448.619022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:23 BXT-2 kernel: [ 448.619878] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:29:23 BXT-2 kernel: [ 448.619939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:29:23 BXT-2 kernel: [ 448.620998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:29:23 BXT-2 kernel: [ 448.623107] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:29:23 BXT-2 kernel: [ 448.624196] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:29:23 BXT-2 kernel: [ 448.641107] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:23 BXT-2 kernel: [ 448.641188] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:29:23 BXT-2 kernel: [ 448.641410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:23 BXT-2 kernel: [ 448.641674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:23 BXT-2 kernel: [ 448.641753] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:29:23 BXT-2 kernel: [ 448.641969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:23 BXT-2 kernel: [ 448.642110] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:29:23 BXT-2 kernel: [ 448.643773] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:29:23 BXT-2 kernel: [ 448.644075] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:23 BXT-2 kernel: [ 448.644235] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from connected to disconnected >May 24 03:29:23 BXT-2 kernel: [ 448.644331] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:23 BXT-2 kernel: [ 448.644629] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:29:23 BXT-2 kernel: [ 448.646215] PM: resume of devices complete after 195.735 msecs >May 24 03:29:23 BXT-2 kernel: [ 448.646850] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:29:23 BXT-2 kernel: [ 448.648977] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:29:23 BXT-2 kernel: [ 448.649051] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:29:23 BXT-2 kernel: [ 448.649159] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:29:23 BXT-2 kernel: [ 448.649231] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:29:23 BXT-2 kernel: [ 448.649379] PM: Finishing wakeup. >May 24 03:29:23 BXT-2 kernel: [ 448.649387] OOM killer enabled. >May 24 03:29:23 BXT-2 kernel: [ 448.649392] Restarting tasks ... >May 24 03:29:23 BXT-2 kernel: [ 448.649825] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:29:23 BXT-2 kernel: [ 448.650310] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:29:23 BXT-2 kernel: [ 448.657095] done. >May 24 03:29:23 BXT-2 kernel: [ 448.658575] video LNXVIDEO:00: Restoring backlight state >May 24 03:29:23 BXT-2 kernel: [ 448.661661] [drm] RC6 on >May 24 03:29:23 BXT-2 kernel: [ 448.671910] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:29:23 BXT-2 NetworkManager[807]: <info> [1495614563.3075] device (enp3s0): link disconnected >May 24 03:29:23 BXT-2 kernel: [ 448.771128] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:29:23 BXT-2 kernel: [ 448.925462] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:29:23 BXT-2 kernel: [ 448.966630] ata1.00: configured for UDMA/133 >May 24 03:29:24 BXT-2 kernel: [ 450.007870] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:29:24 BXT-2 kernel: [ 450.007918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:29:24 BXT-2 kernel: [ 450.007963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 540000 pixel clock 148500KHz >May 24 03:29:24 BXT-2 kernel: [ 450.008009] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:29:24 BXT-2 kernel: [ 450.008051] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:29:24 BXT-2 kernel: [ 450.008096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.008139] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:29:24 BXT-2 kernel: [ 450.008182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.008225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:29:24 BXT-2 kernel: [ 450.008268] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.008310] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:24 BXT-2 kernel: [ 450.008319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.008361] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:24 BXT-2 kernel: [ 450.008367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.008411] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.009577] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:29:24 BXT-2 kernel: [ 450.009621] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:29:24 BXT-2 kernel: [ 450.009664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:24 BXT-2 kernel: [ 450.009706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.009752] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:29:24 BXT-2 kernel: [ 450.009796] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:24 BXT-2 kernel: [ 450.009842] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:83, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:29:24 BXT-2 kernel: [ 450.009885] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:29:24 BXT-2 kernel: [ 450.009928] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:29:24 BXT-2 kernel: [ 450.009972] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:29:24 BXT-2 kernel: [ 450.010015] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:29:24 BXT-2 kernel: [ 450.010066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:29:24 BXT-2 kernel: [ 450.010124] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.010168] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.010363] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.010458] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:29:24 BXT-2 kernel: [ 450.011708] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.017786] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:29:24 BXT-2 kernel: [ 450.017899] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.017955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:29:24 BXT-2 kernel: [ 450.017999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:29:24 BXT-2 kernel: [ 450.018041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:29:24 BXT-2 kernel: [ 450.018084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:29:24 BXT-2 kernel: [ 450.018126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:29:24 BXT-2 kernel: [ 450.018169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:29:24 BXT-2 kernel: [ 450.018212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:29:24 BXT-2 kernel: [ 450.018255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:29:24 BXT-2 kernel: [ 450.018298] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:29:24 BXT-2 kernel: [ 450.018343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.018388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:24 BXT-2 kernel: [ 450.019298] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:29:24 BXT-2 kernel: [ 450.019347] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.021200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:24 BXT-2 kernel: [ 450.021246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:24 BXT-2 kernel: [ 450.021291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:29:24 BXT-2 kernel: [ 450.057112] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -5 >May 24 03:29:24 BXT-2 kernel: [ 450.057173] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training >May 24 03:29:24 BXT-2 kernel: [ 450.057254] [drm:intel_dp_start_link_train [i915]] Link Training failed at link rate = 270000, lane count = 2 >May 24 03:29:24 BXT-2 kernel: [ 450.057319] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.058702] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.058884] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.058981] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:29:24 BXT-2 kernel: [ 450.059154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.075671] [drm:drm_fb_helper_hotplug_event] >May 24 03:29:24 BXT-2 kernel: [ 450.075679] [drm:drm_setup_crtcs] >May 24 03:29:24 BXT-2 kernel: [ 450.075688] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.075753] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.075767] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:29:24 BXT-2 kernel: [ 450.077081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:29:24 BXT-2 kernel: [ 450.077141] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:24 BXT-2 kernel: [ 450.077925] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:29:24 BXT-2 kernel: [ 450.079068] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:29:24 BXT-2 kernel: [ 450.079116] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:29:24 BXT-2 kernel: [ 450.079158] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:29:24 BXT-2 kernel: [ 450.079201] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:29:24 BXT-2 kernel: [ 450.079838] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:29:24 BXT-2 kernel: [ 450.079885] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:29:24 BXT-2 kernel: [ 450.084981] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:29:24 BXT-2 kernel: [ 450.085049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:29:24 BXT-2 kernel: [ 450.085057] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085062] [drm:drm_mode_debug_printmodeline] Modeline 72:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085067] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085072] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085078] [drm:drm_mode_debug_printmodeline] Modeline 70:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085083] [drm:drm_mode_debug_printmodeline] Modeline 78:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085088] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:29:24 BXT-2 kernel: [ 450.085093] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085098] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.085103] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:29:24 BXT-2 kernel: [ 450.085108] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:29:24 BXT-2 kernel: [ 450.085113] [drm:drm_mode_debug_printmodeline] Modeline 76:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:29:24 BXT-2 kernel: [ 450.085142] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:29:24 BXT-2 kernel: [ 450.085146] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:29:24 BXT-2 kernel: [ 450.085205] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:29:24 BXT-2 kernel: [ 450.085216] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:29:24 BXT-2 kernel: [ 450.085221] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:29:24 BXT-2 kernel: [ 450.085224] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:29:24 BXT-2 kernel: [ 450.085228] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:29:24 BXT-2 kernel: [ 450.085255] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:29:24 BXT-2 kernel: [ 450.086626] [drm:drm_fb_helper_hotplug_event] >May 24 03:29:24 BXT-2 kernel: [ 450.086661] [drm:drm_setup_crtcs] >May 24 03:29:24 BXT-2 kernel: [ 450.086767] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.086893] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.086970] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:29:24 BXT-2 kernel: [ 450.086977] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:29:24 BXT-2 kernel: [ 450.087026] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:24 BXT-2 kernel: [ 450.092565] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:29:24 BXT-2 kernel: [ 450.093527] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:29:24 BXT-2 kernel: [ 450.093573] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:29:24 BXT-2 kernel: [ 450.093616] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:29:24 BXT-2 kernel: [ 450.093658] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:29:24 BXT-2 kernel: [ 450.094309] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:29:24 BXT-2 kernel: [ 450.094355] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:29:24 BXT-2 kernel: [ 450.100076] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:29:24 BXT-2 kernel: [ 450.100148] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:29:24 BXT-2 kernel: [ 450.100155] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100161] [drm:drm_mode_debug_printmodeline] Modeline 72:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100166] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100171] [drm:drm_mode_debug_printmodeline] Modeline 71:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100176] [drm:drm_mode_debug_printmodeline] Modeline 70:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100181] [drm:drm_mode_debug_printmodeline] Modeline 78:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100186] [drm:drm_mode_debug_printmodeline] Modeline 79:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:29:24 BXT-2 kernel: [ 450.100192] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100197] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.100202] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:29:24 BXT-2 kernel: [ 450.100207] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:29:24 BXT-2 kernel: [ 450.100212] [drm:drm_mode_debug_printmodeline] Modeline 76:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:29:24 BXT-2 kernel: [ 450.100248] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:29:24 BXT-2 kernel: [ 450.100252] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:29:24 BXT-2 kernel: [ 450.100314] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:29:24 BXT-2 kernel: [ 450.100335] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:29:24 BXT-2 kernel: [ 450.100339] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:29:24 BXT-2 kernel: [ 450.100343] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:29:24 BXT-2 kernel: [ 450.100347] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:29:24 BXT-2 kernel: [ 450.100380] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:29:24 BXT-2 kernel: [ 450.101984] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:29:24 BXT-2 kernel: [ 450.102031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:29:24 BXT-2 kernel: [ 450.102076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:29:24 BXT-2 kernel: [ 450.102121] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:29:24 BXT-2 kernel: [ 450.102163] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:29:24 BXT-2 kernel: [ 450.102209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.102253] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:29:24 BXT-2 kernel: [ 450.102295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.102338] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:29:24 BXT-2 kernel: [ 450.102380] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.102422] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:24 BXT-2 kernel: [ 450.102481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.102524] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:24 BXT-2 kernel: [ 450.102531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.102574] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:29:24 BXT-2 kernel: [ 450.102617] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:29:24 BXT-2 kernel: [ 450.102660] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:29:24 BXT-2 kernel: [ 450.102703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:24 BXT-2 kernel: [ 450.102746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:24 BXT-2 kernel: [ 450.102791] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:29:24 BXT-2 kernel: [ 450.102833] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:24 BXT-2 kernel: [ 450.102878] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:83, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:29:24 BXT-2 kernel: [ 450.102922] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:29:24 BXT-2 kernel: [ 450.102965] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:29:24 BXT-2 kernel: [ 450.103008] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:29:24 BXT-2 kernel: [ 450.103051] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:29:24 BXT-2 kernel: [ 450.103096] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:29:24 BXT-2 kernel: [ 450.103151] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:29:24 BXT-2 kernel: [ 450.103194] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.103359] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.110727] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:29:24 BXT-2 kernel: [ 450.110840] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.110914] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:29:24 BXT-2 kernel: [ 450.124710] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:29:24 BXT-2 kernel: [ 450.124823] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:29:24 BXT-2 kernel: [ 450.124946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:29:24 BXT-2 kernel: [ 450.124994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:29:24 BXT-2 kernel: [ 450.125036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:29:24 BXT-2 kernel: [ 450.125079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:29:24 BXT-2 kernel: [ 450.125122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:29:24 BXT-2 kernel: [ 450.125164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:29:24 BXT-2 kernel: [ 450.125207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:29:24 BXT-2 kernel: [ 450.125250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:29:24 BXT-2 kernel: [ 450.125292] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:24 BXT-2 kernel: [ 450.125339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:29:24 BXT-2 kernel: [ 450.125384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:24 BXT-2 kernel: [ 450.125429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:24 BXT-2 kernel: [ 450.125590] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:29:24 BXT-2 kernel: [ 450.125634] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:29:24 BXT-2 kernel: [ 450.127750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:24 BXT-2 kernel: [ 450.127795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:24 BXT-2 kernel: [ 450.127839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:29:24 BXT-2 kernel: [ 450.128612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:24 BXT-2 kernel: [ 450.128655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:24 BXT-2 kernel: [ 450.129387] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:29:24 BXT-2 kernel: [ 450.129430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:29:24 BXT-2 kernel: [ 450.130530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:29:24 BXT-2 kernel: [ 450.132626] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:29:24 BXT-2 kernel: [ 450.133643] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:29:24 BXT-2 kernel: [ 450.150577] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:24 BXT-2 kernel: [ 450.150644] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:29:24 BXT-2 kernel: [ 450.150817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:24 BXT-2 kernel: [ 450.150935] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:29:24 BXT-2 kernel: [ 450.183930] Console: switching to colour frame buffer device 128x48 >May 24 03:29:25 BXT-2 kernel: [ 450.365873] Console: switching to colour dummy device 80x25 >May 24 03:29:26 BXT-2 kernel: [ 451.833128] r8169 0000:03:00.0 enp3s0: link up >May 24 03:29:26 BXT-2 NetworkManager[807]: <info> [1495614566.4840] device (enp3s0): link connected >May 24 03:29:26 BXT-2 kernel: [ 451.995660] PM: Syncing filesystems ... >May 24 03:29:33 BXT-2 kernel: [ 452.003317] PM: done. >May 24 03:29:33 BXT-2 kernel: [ 452.003326] Freezing user space processes ... (elapsed 0.002 seconds) done. >May 24 03:29:33 BXT-2 kernel: [ 452.005640] OOM killer disabled. >May 24 03:29:33 BXT-2 kernel: [ 452.006405] PM: Marking nosave pages: [mem 0x00000000-0x00000fff] >May 24 03:29:33 BXT-2 kernel: [ 452.006519] PM: Marking nosave pages: [mem 0x0003f000-0x0003ffff] >May 24 03:29:33 BXT-2 kernel: [ 452.006522] PM: Marking nosave pages: [mem 0x0009e000-0x000fffff] >May 24 03:29:33 BXT-2 kernel: [ 452.006527] PM: Marking nosave pages: [mem 0x10000000-0x12150fff] >May 24 03:29:33 BXT-2 kernel: [ 452.006680] PM: Marking nosave pages: [mem 0x77717000-0x79c43fff] >May 24 03:29:33 BXT-2 kernel: [ 452.006838] PM: Marking nosave pages: [mem 0x79fc6000-0x79ff0fff] >May 24 03:29:33 BXT-2 kernel: [ 452.006841] PM: Marking nosave pages: [mem 0x7a9df000-0x7a9e0fff] >May 24 03:29:33 BXT-2 kernel: [ 452.006844] PM: Marking nosave pages: [mem 0x7b000000-0xffffffff] >May 24 03:29:33 BXT-2 kernel: [ 452.008915] PM: Basic memory bitmaps created >May 24 03:29:33 BXT-2 kernel: [ 452.009322] PM: Preallocating image memory... done (allocated 257920 pages) >May 24 03:29:33 BXT-2 kernel: [ 452.653776] PM: Allocated 1031680 kbytes in 0.64 seconds (1612.00 MB/s) >May 24 03:29:33 BXT-2 kernel: [ 452.653779] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 03:29:33 BXT-2 kernel: [ 452.778925] Suspending console(s) (use no_console_suspend to debug) >May 24 03:29:33 BXT-2 kernel: [ 452.783364] system 00:00: System wakeup disabled by ACPI >May 24 03:29:33 BXT-2 kernel: [ 452.784258] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:29:33 BXT-2 kernel: [ 452.784838] ACPI : EC: event blocked >May 24 03:29:33 BXT-2 kernel: [ 452.802844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:29:33 BXT-2 kernel: [ 452.802996] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:29:33 BXT-2 kernel: [ 452.819602] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:29:33 BXT-2 kernel: [ 452.819741] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:29:33 BXT-2 kernel: [ 452.819872] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:29:33 BXT-2 kernel: [ 452.820214] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:33 BXT-2 kernel: [ 452.820280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:29:33 BXT-2 kernel: [ 452.820343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:29:33 BXT-2 kernel: [ 452.820406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:29:33 BXT-2 kernel: [ 452.820499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:29:33 BXT-2 kernel: [ 452.820562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:29:33 BXT-2 kernel: [ 452.820630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:29:33 BXT-2 kernel: [ 452.820694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:29:33 BXT-2 kernel: [ 452.820757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:29:33 BXT-2 kernel: [ 452.820820] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:33 BXT-2 kernel: [ 452.820888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:29:33 BXT-2 kernel: [ 452.820952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:33 BXT-2 kernel: [ 452.821017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:33 BXT-2 kernel: [ 452.821118] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:29:33 BXT-2 kernel: [ 452.933602] PM: freeze of devices complete after 154.530 msecs >May 24 03:29:33 BXT-2 kernel: [ 452.933606] PM: hibernation debug: Waiting for 5 seconds. >May 24 03:29:33 BXT-2 kernel: [ 458.446654] ACPI : EC: event unblocked >May 24 03:29:33 BXT-2 kernel: [ 458.448002] usb usb1: root hub lost power or was reset >May 24 03:29:33 BXT-2 kernel: [ 458.448017] usb usb2: root hub lost power or was reset >May 24 03:29:33 BXT-2 kernel: [ 458.448808] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 03:29:33 BXT-2 kernel: [ 458.461123] r8169 0000:03:00.0 enp3s0: link down >May 24 03:29:33 BXT-2 kernel: [ 458.461240] sd 0:0:0:0: [sda] Starting disk >May 24 03:29:33 BXT-2 kernel: [ 458.578116] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:29:33 BXT-2 kernel: [ 458.578204] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:29:33 BXT-2 kernel: [ 458.578248] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:29:33 BXT-2 kernel: [ 458.578315] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:29:33 BXT-2 kernel: [ 458.578469] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:29:33 BXT-2 kernel: [ 458.578627] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:29:33 BXT-2 kernel: [ 458.578694] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:29:33 BXT-2 kernel: [ 458.578815] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:29:33 BXT-2 kernel: [ 458.578938] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:29:33 BXT-2 kernel: [ 458.579061] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:29:33 BXT-2 kernel: [ 458.579159] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:33 BXT-2 kernel: [ 458.579217] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:29:33 BXT-2 kernel: [ 458.579313] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.579358] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:29:33 BXT-2 kernel: [ 458.579411] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.579473] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:29:33 BXT-2 kernel: [ 458.579526] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.579568] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:29:33 BXT-2 kernel: [ 458.579616] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:29:33 BXT-2 kernel: [ 458.579661] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:29:33 BXT-2 kernel: [ 458.579705] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:29:33 BXT-2 kernel: [ 458.579755] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:29:33 BXT-2 kernel: [ 458.579799] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:29:33 BXT-2 kernel: [ 458.579843] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:29:33 BXT-2 kernel: [ 458.579887] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:29:33 BXT-2 kernel: [ 458.579933] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:29:33 BXT-2 kernel: [ 458.579977] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:29:33 BXT-2 kernel: [ 458.580021] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:29:33 BXT-2 kernel: [ 458.580065] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:29:33 BXT-2 kernel: [ 458.580115] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:29:33 BXT-2 kernel: [ 458.580165] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:29:33 BXT-2 kernel: [ 458.580217] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:29:33 BXT-2 kernel: [ 458.580261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.580302] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.580343] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:33 BXT-2 kernel: [ 458.580355] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.580396] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:33 BXT-2 kernel: [ 458.580423] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.580467] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.580509] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:29:33 BXT-2 kernel: [ 458.580551] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.580593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:33 BXT-2 kernel: [ 458.580634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.580679] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.580720] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:33 BXT-2 kernel: [ 458.580765] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.580809] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.580852] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.580896] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.580940] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:29:33 BXT-2 kernel: [ 458.580982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581023] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581064] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:33 BXT-2 kernel: [ 458.581069] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581110] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:33 BXT-2 kernel: [ 458.581115] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581157] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581198] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581240] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:33 BXT-2 kernel: [ 458.581322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581365] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581406] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:33 BXT-2 kernel: [ 458.581470] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.581514] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.581557] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.581601] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.581645] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:29:33 BXT-2 kernel: [ 458.581686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581728] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581769] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:33 BXT-2 kernel: [ 458.581774] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581814] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:33 BXT-2 kernel: [ 458.581819] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581861] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.581903] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581944] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.581986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:33 BXT-2 kernel: [ 458.582027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.582070] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:29:33 BXT-2 kernel: [ 458.582111] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:33 BXT-2 kernel: [ 458.582154] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.582198] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.582242] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.582409] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:29:33 BXT-2 kernel: [ 458.582468] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:29:33 BXT-2 kernel: [ 458.582508] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:29:33 BXT-2 kernel: [ 458.582561] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:29:33 BXT-2 kernel: [ 458.582602] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:29:33 BXT-2 kernel: [ 458.582645] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:29:33 BXT-2 kernel: [ 458.582686] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:29:33 BXT-2 kernel: [ 458.583231] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:29:33 BXT-2 kernel: [ 458.583312] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:29:33 BXT-2 kernel: [ 458.583355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:29:33 BXT-2 kernel: [ 458.583399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:29:33 BXT-2 kernel: [ 458.583464] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:29:33 BXT-2 kernel: [ 458.583505] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:29:33 BXT-2 kernel: [ 458.583551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.583593] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:29:33 BXT-2 kernel: [ 458.583634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.583677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:29:33 BXT-2 kernel: [ 458.583718] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.583759] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:29:33 BXT-2 kernel: [ 458.583764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:33 BXT-2 kernel: [ 458.583805] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:29:33 BXT-2 kernel: [ 458.583810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:29:33 BXT-2 kernel: [ 458.583852] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:29:33 BXT-2 kernel: [ 458.583894] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:29:33 BXT-2 kernel: [ 458.583935] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:29:33 BXT-2 kernel: [ 458.583977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:29:33 BXT-2 kernel: [ 458.584018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:29:33 BXT-2 kernel: [ 458.584061] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:29:33 BXT-2 kernel: [ 458.584102] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:29:33 BXT-2 kernel: [ 458.584143] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.584185] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.584226] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.584267] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:29:33 BXT-2 kernel: [ 458.584313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:29:33 BXT-2 kernel: [ 458.584366] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:29:33 BXT-2 kernel: [ 458.584410] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:29:33 BXT-2 kernel: [ 458.584569] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:29:33 BXT-2 kernel: [ 458.584605] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:29:33 BXT-2 kernel: [ 458.584894] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:29:33 BXT-2 kernel: [ 458.584946] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:29:33 BXT-2 kernel: [ 458.584985] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:29:33 BXT-2 kernel: [ 458.585039] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:29:33 BXT-2 kernel: [ 458.585283] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:29:33 BXT-2 kernel: [ 458.585606] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:29:33 BXT-2 kernel: [ 458.585651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:29:33 BXT-2 kernel: [ 458.585694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:29:33 BXT-2 kernel: [ 458.585736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:29:33 BXT-2 kernel: [ 458.585778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:29:33 BXT-2 kernel: [ 458.585821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:29:33 BXT-2 kernel: [ 458.585863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:29:33 BXT-2 kernel: [ 458.585904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:29:33 BXT-2 kernel: [ 458.585946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:29:33 BXT-2 kernel: [ 458.585991] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:33 BXT-2 kernel: [ 458.586038] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:29:33 BXT-2 kernel: [ 458.586083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:29:33 BXT-2 kernel: [ 458.586127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:33 BXT-2 kernel: [ 458.586201] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:29:33 BXT-2 kernel: [ 458.586245] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:29:33 BXT-2 kernel: [ 458.587685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:33 BXT-2 kernel: [ 458.587726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:33 BXT-2 kernel: [ 458.587771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:29:33 BXT-2 kernel: [ 458.588549] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:29:33 BXT-2 kernel: [ 458.588590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:29:33 BXT-2 kernel: [ 458.589315] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:29:33 BXT-2 kernel: [ 458.589356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:29:33 BXT-2 kernel: [ 458.590398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:29:33 BXT-2 kernel: [ 458.592504] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:29:33 BXT-2 kernel: [ 458.593554] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:29:33 BXT-2 kernel: [ 458.610468] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:33 BXT-2 kernel: [ 458.610521] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:29:33 BXT-2 kernel: [ 458.610690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:29:33 BXT-2 kernel: [ 458.610798] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:29:33 BXT-2 kernel: [ 458.610849] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:29:33 BXT-2 kernel: [ 458.611086] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:29:33 BXT-2 kernel: [ 458.611180] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:29:33 BXT-2 kernel: [ 458.611199] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:29:33 BXT-2 kernel: [ 458.611267] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:29:33 BXT-2 kernel: [ 458.611389] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:29:33 BXT-2 kernel: [ 458.614681] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:29:33 BXT-2 kernel: [ 458.615669] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:29:33 BXT-2 kernel: [ 458.615738] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:29:33 BXT-2 kernel: [ 458.615803] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:29:33 BXT-2 kernel: [ 458.615868] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:29:33 BXT-2 kernel: [ 458.616428] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:29:33 BXT-2 kernel: [ 458.616543] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:29:33 BXT-2 kernel: [ 458.621716] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:29:33 BXT-2 kernel: [ 458.771894] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:29:33 BXT-2 kernel: [ 458.830983] usb 1-8: reset full-speed USB device number 2 using xhci_hcd >May 24 03:29:33 BXT-2 kernel: [ 458.933510] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:29:33 BXT-2 kernel: [ 458.995528] ata1.00: configured for UDMA/133 >May 24 03:29:33 BXT-2 kernel: [ 459.003156] PM: restore of devices complete after 558.410 msecs >May 24 03:29:33 BXT-2 kernel: [ 459.007369] PM: Image restored successfully. >May 24 03:29:33 BXT-2 kernel: [ 459.008130] PM: Basic memory bitmaps freed >May 24 03:29:33 BXT-2 kernel: [ 459.008137] OOM killer enabled. >May 24 03:29:33 BXT-2 kernel: [ 459.008142] Restarting tasks ... done. >May 24 03:29:33 BXT-2 NetworkManager[807]: <info> [1495614573.6635] device (enp3s0): link disconnected >May 24 03:29:33 BXT-2 kernel: [ 459.035204] video LNXVIDEO:00: Restoring backlight state >May 24 03:29:33 BXT-2 kernel: [ 459.038307] [drm] RC6 on >May 24 03:29:35 BXT-2 kernel: [ 460.393910] Console: switching to colour frame buffer device 128x48 >May 24 03:29:35 BXT-2 kernel: [ 460.594635] Console: switching to colour dummy device 80x25 >May 24 03:29:35 BXT-2 kernel: [ 460.660593] Console: switching to colour frame buffer device 128x48 >May 24 03:29:35 BXT-2 kernel: [ 460.857177] Console: switching to colour dummy device 80x25 >May 24 03:29:35 BXT-2 kernel: [ 460.927279] Console: switching to colour frame buffer device 128x48 >May 24 03:29:35 BXT-2 kernel: [ 461.116980] Console: switching to colour dummy device 80x25 >May 24 03:29:35 BXT-2 kernel: [ 461.193911] Console: switching to colour frame buffer device 128x48 >May 24 03:29:36 BXT-2 kernel: [ 461.380810] Console: switching to colour dummy device 80x25 >May 24 03:29:36 BXT-2 kernel: [ 461.443894] Console: switching to colour frame buffer device 128x48 >May 24 03:29:36 BXT-2 kernel: [ 461.632361] Console: switching to colour dummy device 80x25 >May 24 03:29:36 BXT-2 kernel: [ 461.693890] Console: switching to colour frame buffer device 128x48 >May 24 03:29:36 BXT-2 kernel: [ 461.880748] Console: switching to colour dummy device 80x25 >May 24 03:29:36 BXT-2 kernel: [ 461.960589] Console: switching to colour frame buffer device 128x48 >May 24 03:29:36 BXT-2 kernel: [ 462.149590] Console: switching to colour dummy device 80x25 >May 24 03:29:36 BXT-2 kernel: [ 462.192435] r8169 0000:03:00.0 enp3s0: link up >May 24 03:29:36 BXT-2 NetworkManager[807]: <info> [1495614576.8420] device (enp3s0): link connected >May 24 03:29:36 BXT-2 kernel: [ 462.210646] Console: switching to colour frame buffer device 128x48 >May 24 03:29:37 BXT-2 kernel: [ 462.399433] Console: switching to colour dummy device 80x25 >May 24 03:29:37 BXT-2 kernel: [ 462.477242] Console: switching to colour frame buffer device 128x48 >May 24 03:29:37 BXT-2 kernel: [ 462.664449] Console: switching to colour dummy device 80x25 >May 24 03:29:37 BXT-2 kernel: [ 462.727226] Console: switching to colour frame buffer device 128x48 >May 24 03:29:37 BXT-2 kernel: [ 462.919973] Console: switching to colour dummy device 80x25 >May 24 03:29:37 BXT-2 kernel: [ 462.993882] Console: switching to colour frame buffer device 128x48 >May 24 03:29:37 BXT-2 kernel: [ 463.182998] Console: switching to colour dummy device 80x25 >May 24 03:29:37 BXT-2 kernel: [ 463.243911] Console: switching to colour frame buffer device 128x48 >May 24 03:29:38 BXT-2 kernel: [ 463.438895] Console: switching to colour dummy device 80x25 >May 24 03:29:38 BXT-2 kernel: [ 463.510601] Console: switching to colour frame buffer device 128x48 >May 24 03:29:38 BXT-2 kernel: [ 463.701122] Console: switching to colour dummy device 80x25 >May 24 03:29:38 BXT-2 kernel: [ 463.760620] Console: switching to colour frame buffer device 128x48 >May 24 03:29:38 BXT-2 kernel: [ 463.957651] Console: switching to colour dummy device 80x25 >May 24 03:29:38 BXT-2 kernel: [ 464.027252] Console: switching to colour frame buffer device 128x48 >May 24 03:29:38 BXT-2 kernel: [ 464.224965] Console: switching to colour dummy device 80x25 >May 24 03:29:38 BXT-2 kernel: [ 464.293890] Console: switching to colour frame buffer device 128x48 >May 24 03:29:39 BXT-2 kernel: [ 464.481630] Console: switching to colour dummy device 80x25 >May 24 03:29:39 BXT-2 kernel: [ 464.543910] Console: switching to colour frame buffer device 128x48 >May 24 03:29:39 BXT-2 kernel: [ 464.732657] Console: switching to colour dummy device 80x25 >May 24 03:29:39 BXT-2 kernel: [ 464.793919] Console: switching to colour frame buffer device 128x48 >May 24 03:29:39 BXT-2 kernel: [ 464.980915] Console: switching to colour dummy device 80x25 >May 24 03:29:39 BXT-2 kernel: [ 465.043911] Console: switching to colour frame buffer device 128x48 >May 24 03:29:39 BXT-2 kernel: [ 465.234912] Console: switching to colour dummy device 80x25 >May 24 03:29:40 BXT-2 kernel: [ 465.410637] Console: switching to colour frame buffer device 128x48 >May 24 03:29:40 BXT-2 kernel: [ 465.600756] Console: switching to colour dummy device 80x25 >May 24 03:29:40 BXT-2 kernel: [ 465.777265] Console: switching to colour frame buffer device 128x48 >May 24 03:29:40 BXT-2 kernel: [ 465.965286] Console: switching to colour dummy device 80x25 >May 24 03:29:40 BXT-2 kernel: [ 466.143939] Console: switching to colour frame buffer device 128x48 >May 24 03:29:40 BXT-2 kernel: [ 466.333918] Console: switching to colour dummy device 80x25 >May 24 03:29:41 BXT-2 kernel: [ 466.510615] Console: switching to colour frame buffer device 128x48 >May 24 03:29:41 BXT-2 kernel: [ 466.699687] Console: switching to colour dummy device 80x25 >May 24 03:29:41 BXT-2 kernel: [ 466.877267] Console: switching to colour frame buffer device 128x48 >May 24 03:29:41 BXT-2 kernel: [ 467.070502] Console: switching to colour dummy device 80x25 >May 24 03:29:41 BXT-2 kernel: [ 467.260700] Console: switching to colour frame buffer device 128x48 >May 24 03:29:42 BXT-2 kernel: [ 467.458841] Console: switching to colour dummy device 80x25 >May 24 03:29:42 BXT-2 kernel: [ 467.643995] Console: switching to colour frame buffer device 128x48 >May 24 03:29:42 BXT-2 kernel: [ 467.835330] Console: switching to colour dummy device 80x25 >May 24 03:29:42 BXT-2 kernel: [ 468.010695] Console: switching to colour frame buffer device 128x48 >May 24 03:29:42 BXT-2 kernel: [ 468.202851] Console: switching to colour dummy device 80x25 >May 24 03:29:43 BXT-2 kernel: [ 468.377376] Console: switching to colour frame buffer device 128x48 >May 24 03:29:43 BXT-2 kernel: [ 468.568278] Console: switching to colour dummy device 80x25 >May 24 03:29:43 BXT-2 kernel: [ 468.643989] Console: switching to colour frame buffer device 128x48 >May 24 03:29:43 BXT-2 kernel: [ 468.830711] Console: switching to colour dummy device 80x25 >May 24 03:29:43 BXT-2 kernel: [ 468.877340] Console: switching to colour frame buffer device 128x48 >May 24 03:29:43 BXT-2 kernel: [ 469.063071] Console: switching to colour dummy device 80x25 >May 24 03:29:43 BXT-2 kernel: [ 469.110678] Console: switching to colour frame buffer device 128x48 >May 24 03:29:43 BXT-2 kernel: [ 469.292506] Console: switching to colour dummy device 80x25 >May 24 03:29:43 BXT-2 kernel: [ 469.343964] Console: switching to colour frame buffer device 128x48 >May 24 03:29:44 BXT-2 kernel: [ 469.525193] Console: switching to colour dummy device 80x25 >May 24 03:29:44 BXT-2 kernel: [ 469.577334] Console: switching to colour frame buffer device 128x48 >May 24 03:29:44 BXT-2 kernel: [ 469.759184] Console: switching to colour dummy device 80x25 >May 24 03:29:44 BXT-2 kernel: [ 469.810721] Console: switching to colour frame buffer device 128x48 >May 24 03:29:44 BXT-2 kernel: [ 469.985265] Console: switching to colour dummy device 80x25 >May 24 03:29:44 BXT-2 kernel: [ 470.060683] Console: switching to colour frame buffer device 128x48 >May 24 03:29:44 BXT-2 kernel: [ 470.237628] Console: switching to colour dummy device 80x25 >May 24 03:29:44 BXT-2 kernel: [ 470.310692] Console: switching to colour frame buffer device 128x48 >May 24 03:29:45 BXT-2 kernel: [ 470.504740] Console: switching to colour dummy device 80x25 >May 24 03:29:45 BXT-2 kernel: [ 471.110708] Console: switching to colour frame buffer device 128x48 >May 24 03:29:45 BXT-2 kernel: [ 471.347496] Console: switching to colour dummy device 80x25 >May 24 03:29:46 BXT-2 kernel: [ 471.394005] Console: switching to colour frame buffer device 128x48 >May 24 03:29:46 BXT-2 kernel: [ 471.581847] Console: switching to colour dummy device 80x25 >May 24 03:29:46 BXT-2 kernel: [ 471.694014] Console: switching to colour frame buffer device 128x48 >May 24 03:29:46 BXT-2 kernel: [ 471.868796] Console: switching to colour dummy device 80x25 >May 24 03:29:47 BXT-2 kernel: [ 472.777307] Console: switching to colour frame buffer device 128x48 >May 24 03:29:47 BXT-2 kernel: [ 472.968861] Console: switching to colour dummy device 80x25 >May 24 03:29:47 BXT-2 kernel: [ 473.110694] Console: switching to colour frame buffer device 128x48 >May 24 03:29:47 BXT-2 kernel: [ 473.296029] Console: switching to colour dummy device 80x25 >May 24 03:29:48 BXT-2 kernel: [ 473.810695] Console: switching to colour frame buffer device 128x48 >May 24 03:29:48 BXT-2 kernel: [ 473.999470] Console: switching to colour dummy device 80x25 >May 24 03:29:49 BXT-2 kernel: [ 474.893993] Console: switching to colour frame buffer device 128x48 >May 24 03:29:49 BXT-2 kernel: [ 475.079918] Console: switching to colour dummy device 80x25 >May 24 03:29:49 BXT-2 kernel: [ 475.177424] Console: switching to colour frame buffer device 128x48 >May 24 03:29:50 BXT-2 kernel: [ 475.352548] Console: switching to colour dummy device 80x25 >May 24 03:29:50 BXT-2 kernel: [ 475.444009] Console: switching to colour frame buffer device 128x48 >May 24 03:29:50 BXT-2 kernel: [ 475.622084] Console: switching to colour dummy device 80x25 >May 24 03:29:50 BXT-2 kernel: [ 475.710719] Console: switching to colour frame buffer device 128x48 >May 24 03:29:50 BXT-2 kernel: [ 475.887745] Console: switching to colour dummy device 80x25 >May 24 03:29:50 BXT-2 kernel: [ 475.994030] Console: switching to colour frame buffer device 128x48 >May 24 03:29:50 BXT-2 kernel: [ 476.208181] Console: switching to colour dummy device 80x25 >May 24 03:29:50 BXT-2 kernel: [ 476.222675] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:50 BXT-2 kernel: [ 476.278724] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:50 BXT-2 kernel: [ 476.279074] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:50 BXT-2 kernel: [ 476.327362] Console: switching to colour frame buffer device 128x48 >May 24 03:29:51 BXT-2 kernel: [ 476.546998] Console: switching to colour dummy device 80x25 >May 24 03:29:51 BXT-2 kernel: [ 476.569019] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:51 BXT-2 kernel: [ 476.990439] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:51 BXT-2 kernel: [ 476.990968] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:51 BXT-2 kernel: [ 477.060721] Console: switching to colour frame buffer device 128x48 >May 24 03:29:51 BXT-2 kernel: [ 477.277696] Console: switching to colour dummy device 80x25 >May 24 03:29:51 BXT-2 kernel: [ 477.291326] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:52 BXT-2 kernel: [ 478.068491] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:52 BXT-2 kernel: [ 478.068954] Setting dangerous option prefault_disable - tainting kernel >May 24 03:29:52 BXT-2 kernel: [ 478.127371] Console: switching to colour frame buffer device 128x48 >May 24 03:29:52 BXT-2 kernel: [ 478.319478] Console: switching to colour dummy device 80x25 >May 24 03:29:53 BXT-2 kernel: [ 478.394029] Console: switching to colour frame buffer device 128x48 >May 24 03:29:53 BXT-2 kernel: [ 478.585173] Console: switching to colour dummy device 80x25 >May 24 03:29:53 BXT-2 kernel: [ 479.277364] Console: switching to colour frame buffer device 128x48 >May 24 03:29:54 BXT-2 kernel: [ 479.470057] Console: switching to colour dummy device 80x25 >May 24 03:29:54 BXT-2 kernel: [ 479.927382] Console: switching to colour frame buffer device 128x48 >May 24 03:29:54 BXT-2 kernel: [ 480.158351] Console: switching to colour dummy device 80x25 >May 24 03:29:55 BXT-2 kernel: [ 480.577494] Console: switching to colour frame buffer device 128x48 >May 24 03:29:55 BXT-2 kernel: [ 480.804527] Console: switching to colour dummy device 80x25 >May 24 03:29:55 BXT-2 kernel: [ 481.277510] Console: switching to colour frame buffer device 128x48 >May 24 03:29:56 BXT-2 kernel: [ 481.471780] Console: switching to colour dummy device 80x25 >May 24 03:29:58 BXT-2 kernel: [ 484.077514] Console: switching to colour frame buffer device 128x48 >May 24 03:29:58 BXT-2 kernel: [ 484.273200] Console: switching to colour dummy device 80x25 >May 24 03:30:02 BXT-2 kernel: [ 487.860854] Console: switching to colour frame buffer device 128x48 >May 24 03:30:02 BXT-2 kernel: [ 488.056265] Console: switching to colour dummy device 80x25 >May 24 03:30:04 BXT-2 kernel: [ 490.060817] Console: switching to colour frame buffer device 128x48 >May 24 03:30:04 BXT-2 kernel: [ 490.236005] Console: switching to colour dummy device 80x25 >May 24 03:30:06 BXT-2 kernel: [ 492.177603] Console: switching to colour frame buffer device 128x48 >May 24 03:30:07 BXT-2 kernel: [ 492.368597] Console: switching to colour dummy device 80x25 >May 24 03:30:07 BXT-2 kernel: [ 492.402693] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1 >May 24 03:30:07 BXT-2 kernel: [ 492.510895] Console: switching to colour frame buffer device 128x48 >May 24 03:30:07 BXT-2 kernel: [ 492.705058] Console: switching to colour dummy device 80x25 >May 24 03:30:07 BXT-2 kernel: [ 492.722002] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1 >May 24 03:30:08 BXT-2 kernel: [ 493.944220] Console: switching to colour frame buffer device 128x48 >May 24 03:30:08 BXT-2 kernel: [ 494.127143] Console: switching to colour dummy device 80x25 >May 24 03:30:08 BXT-2 kernel: [ 494.150445] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1 >May 24 03:30:12 BXT-2 kernel: [ 497.774285] [drm:missed_breadcrumb [i915]] rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x5c/0x80 [i915], irq posted? yes, current seqno=d87c9, last=d8846 >May 24 03:30:18 BXT-2 kernel: [ 503.735701] [drm] GPU HANG: ecode 9:0:0xe757fffe, in gem_ringfill [19162], reason: Hang on rcs0, action: reset >May 24 03:30:18 BXT-2 kernel: [ 503.736011] [drm:i915_reset_and_wakeup [i915]] resetting chip >May 24 03:30:18 BXT-2 kernel: [ 503.736998] drm/i915: Resetting chip after gpu hang >May 24 03:30:18 BXT-2 kernel: [ 503.747174] [drm:i915_gem_reset [i915]] context gem_ringfill[19162]/0 marked guilty (score 10) banned? no >May 24 03:30:18 BXT-2 kernel: [ 503.747220] [drm:i915_gem_reset [i915]] resetting rcs0 to restart from tail of request 0xd87ca >May 24 03:30:18 BXT-2 kernel: [ 503.747825] [drm] RC6 on >May 24 03:30:18 BXT-2 kernel: [ 503.748743] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:30:18 BXT-2 kernel: [ 503.748791] [drm:gen8_init_common_ring [i915]] Restarting rcs0:0 from 0xd8846 >May 24 03:30:18 BXT-2 kernel: [ 503.748888] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:30:18 BXT-2 kernel: [ 503.749023] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:30:18 BXT-2 kernel: [ 503.749156] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:30:18 BXT-2 kernel: [ 503.749265] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:30:19 BXT-2 kernel: [ 504.994229] Console: switching to colour frame buffer device 128x48 >May 24 03:30:19 BXT-2 kernel: [ 505.190720] Console: switching to colour dummy device 80x25 >May 24 03:30:19 BXT-2 kernel: [ 505.206872] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1 >May 24 03:30:19 BXT-2 kernel: [ 505.327590] Console: switching to colour frame buffer device 128x48 >May 24 03:30:20 BXT-2 kernel: [ 505.521615] Console: switching to colour dummy device 80x25 >May 24 03:30:20 BXT-2 kernel: [ 505.537577] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1 >May 24 03:30:20 BXT-2 kernel: [ 505.660972] Console: switching to colour frame buffer device 128x48 >May 24 03:30:20 BXT-2 kernel: [ 505.828322] Console: switching to colour dummy device 80x25 >May 24 03:30:20 BXT-2 kernel: [ 505.927591] Console: switching to colour frame buffer device 128x48 >May 24 03:30:20 BXT-2 kernel: [ 506.122345] Console: switching to colour dummy device 80x25 >May 24 03:30:20 BXT-2 kernel: [ 506.241155] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:30:20 BXT-2 kernel: [ 506.241236] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:30:20 BXT-2 kernel: [ 506.241280] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:30:20 BXT-2 kernel: [ 506.241324] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:30:20 BXT-2 kernel: [ 506.241368] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:30:20 BXT-2 kernel: [ 506.241411] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:30:20 BXT-2 kernel: [ 506.241823] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:30:20 BXT-2 kernel: [ 506.241869] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:30:20 BXT-2 kernel: [ 506.241912] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:30:20 BXT-2 kernel: [ 506.282830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:20 BXT-2 kernel: [ 506.283173] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:20 BXT-2 kernel: [ 506.296039] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:20 BXT-2 kernel: [ 506.296223] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:20 BXT-2 kernel: [ 506.296348] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:20 BXT-2 kernel: [ 506.296774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:20 BXT-2 kernel: [ 506.296820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:20 BXT-2 kernel: [ 506.296864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:20 BXT-2 kernel: [ 506.296907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:20 BXT-2 kernel: [ 506.296950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:20 BXT-2 kernel: [ 506.296994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:20 BXT-2 kernel: [ 506.297041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:20 BXT-2 kernel: [ 506.297084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:20 BXT-2 kernel: [ 506.297127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:20 BXT-2 kernel: [ 506.297170] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:20 BXT-2 kernel: [ 506.297218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:20 BXT-2 kernel: [ 506.297264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:20 BXT-2 kernel: [ 506.297309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:20 BXT-2 kernel: [ 506.297442] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:20 BXT-2 kernel: [ 506.297661] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:20 BXT-2 kernel: [ 506.297845] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:20 BXT-2 kernel: [ 506.297914] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:20 BXT-2 kernel: [ 506.297968] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:20 BXT-2 kernel: [ 506.298013] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:20 BXT-2 kernel: [ 506.298053] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:20 BXT-2 kernel: [ 506.298637] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:20 BXT-2 kernel: [ 506.309815] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:20 BXT-2 kernel: [ 506.309856] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:20 BXT-2 kernel: [ 506.310347] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:20 BXT-2 kernel: [ 506.310397] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:20 BXT-2 kernel: [ 506.310473] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:20 BXT-2 kernel: [ 506.310757] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:30:20 BXT-2 kernel: [ 506.313218] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.365893] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0 >May 24 03:30:21 BXT-2 kernel: [ 506.444400] [drm:i915_driver_load [i915]] No PCH found. >May 24 03:30:21 BXT-2 kernel: [ 506.444545] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09 >May 24 03:30:21 BXT-2 kernel: [ 506.446758] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a85 rev=0x0b >May 24 03:30:21 BXT-2 kernel: [ 506.446812] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no >May 24 03:30:21 BXT-2 kernel: [ 506.446862] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes >May 24 03:30:21 BXT-2 kernel: [ 506.446911] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no >May 24 03:30:21 BXT-2 kernel: [ 506.446960] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447009] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447058] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447107] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447156] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447205] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447254] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447303] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447352] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447401] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447867] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes >May 24 03:30:21 BXT-2 kernel: [ 506.447917] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no >May 24 03:30:21 BXT-2 kernel: [ 506.447967] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes >May 24 03:30:21 BXT-2 kernel: [ 506.448017] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes >May 24 03:30:21 BXT-2 kernel: [ 506.448066] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no >May 24 03:30:21 BXT-2 kernel: [ 506.448116] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no >May 24 03:30:21 BXT-2 kernel: [ 506.448165] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes >May 24 03:30:21 BXT-2 kernel: [ 506.448215] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no >May 24 03:30:21 BXT-2 kernel: [ 506.448264] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no >May 24 03:30:21 BXT-2 kernel: [ 506.448314] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no >May 24 03:30:21 BXT-2 kernel: [ 506.448364] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no >May 24 03:30:21 BXT-2 kernel: [ 506.448414] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes >May 24 03:30:21 BXT-2 kernel: [ 506.448808] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no >May 24 03:30:21 BXT-2 kernel: [ 506.448858] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes >May 24 03:30:21 BXT-2 kernel: [ 506.448908] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes >May 24 03:30:21 BXT-2 kernel: [ 506.448958] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no >May 24 03:30:21 BXT-2 kernel: [ 506.449007] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no >May 24 03:30:21 BXT-2 kernel: [ 506.449057] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no >May 24 03:30:21 BXT-2 kernel: [ 506.449106] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no >May 24 03:30:21 BXT-2 kernel: [ 506.449156] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no >May 24 03:30:21 BXT-2 kernel: [ 506.449206] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no >May 24 03:30:21 BXT-2 kernel: [ 506.454354] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001 >May 24 03:30:21 BXT-2 kernel: [ 506.454410] [drm:intel_device_info_runtime_init [i915]] slice total: 1 >May 24 03:30:21 BXT-2 kernel: [ 506.454786] [drm:intel_device_info_runtime_init [i915]] subslice total: 2 >May 24 03:30:21 BXT-2 kernel: [ 506.454836] [drm:intel_device_info_runtime_init [i915]] subslice mask 0006 >May 24 03:30:21 BXT-2 kernel: [ 506.454885] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 2 >May 24 03:30:21 BXT-2 kernel: [ 506.454934] [drm:intel_device_info_runtime_init [i915]] EU total: 12 >May 24 03:30:21 BXT-2 kernel: [ 506.454983] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6 >May 24 03:30:21 BXT-2 kernel: [ 506.455032] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n >May 24 03:30:21 BXT-2 kernel: [ 506.455082] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y >May 24 03:30:21 BXT-2 kernel: [ 506.455131] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y >May 24 03:30:21 BXT-2 kernel: [ 506.455181] [drm:i915_driver_load [i915]] ppgtt mode: 3 >May 24 03:30:21 BXT-2 kernel: [ 506.455229] [drm:i915_driver_load [i915]] use GPU semaphores? no >May 24 03:30:21 BXT-2 kernel: [ 506.455352] [drm] Memory usable by graphics device = 4096M >May 24 03:30:21 BXT-2 kernel: [ 506.455417] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M >May 24 03:30:21 BXT-2 kernel: [ 506.458733] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M >May 24 03:30:21 BXT-2 kernel: [ 506.458737] [drm] VT-d active for gfx access >May 24 03:30:21 BXT-2 kernel: [ 506.458757] [drm] Replacing VGA console driver >May 24 03:30:21 BXT-2 kernel: [ 506.458935] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K >May 24 03:30:21 BXT-2 kernel: [ 506.459006] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0 >May 24 03:30:21 BXT-2 kernel: [ 506.459330] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:30:21 BXT-2 kernel: [ 506.459864] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:30:21 BXT-2 kernel: [ 506.459924] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:30:21 BXT-2 kernel: [ 506.460025] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:30:21 BXT-2 kernel: [ 506.460398] [drm:intel_gvt_init [i915]] Unsupported device. GVT-g is disabled >May 24 03:30:21 BXT-2 kernel: [ 506.460710] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). >May 24 03:30:21 BXT-2 kernel: [ 506.460713] [drm] Driver supports precise vblank timestamp query. >May 24 03:30:21 BXT-2 kernel: [ 506.460790] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.460847] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON ", BDB version 207 >May 24 03:30:21 BXT-2 kernel: [ 506.460905] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 >May 24 03:30:21 BXT-2 kernel: [ 506.460961] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 >May 24 03:30:21 BXT-2 kernel: [ 506.461019] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19) >May 24 03:30:21 BXT-2 kernel: [ 506.461076] [drm:intel_bios_init [i915]] Panel type: 0 (VBT) >May 24 03:30:21 BXT-2 kernel: [ 506.461131] [drm:intel_bios_init [i915]] DRRS supported mode is static >May 24 03:30:21 BXT-2 kernel: [ 506.461196] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables: >May 24 03:30:21 BXT-2 kernel: [ 506.461205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 148350 1920 1960 2000 2040 1200 1204 1208 1212 0x8 0xa >May 24 03:30:21 BXT-2 kernel: [ 506.461262] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 1 >May 24 03:30:21 BXT-2 kernel: [ 506.461319] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping. >May 24 03:30:21 BXT-2 kernel: [ 506.461375] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38 >May 24 03:30:21 BXT-2 kernel: [ 506.461438] [drm:intel_bios_init [i915]] DRRS State Enabled:1 >May 24 03:30:21 BXT-2 kernel: [ 506.461860] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 >May 24 03:30:21 BXT-2 kernel: [ 506.461918] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.461975] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:0 DVI:0 EDP:0 CRT:0 >May 24 03:30:21 BXT-2 kernel: [ 506.462031] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.463172] [drm:intel_dsm_detect [i915]] no _DSM method for intel device >May 24 03:30:21 BXT-2 kernel: [ 506.463248] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:30:21 BXT-2 kernel: [ 506.463787] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:30:21 BXT-2 kernel: [ 506.463885] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.463957] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.464008] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.464060] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:30:21 BXT-2 kernel: [ 506.464123] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.464176] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:30:21 BXT-2 kernel: [ 506.464270] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it >May 24 03:30:21 BXT-2 kernel: [ 506.464322] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.464442] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it >May 24 03:30:21 BXT-2 kernel: [ 506.464881] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin >May 24 03:30:21 BXT-2 kernel: [ 506.472225] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:30:21 BXT-2 kernel: [ 506.474259] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled >May 24 03:30:21 BXT-2 kernel: [ 506.474341] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.474416] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474501] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474553] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474605] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474656] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474709] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474760] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474810] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec) >May 24 03:30:21 BXT-2 kernel: [ 506.474872] [drm:intel_modeset_init [i915]] 3 display pipes available. >May 24 03:30:21 BXT-2 kernel: [ 506.476268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.476373] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.476429] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.477128] [drm:intel_ddi_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it >May 24 03:30:21 BXT-2 kernel: [ 506.477187] [drm:intel_ddi_init [i915]] VBT says port B has lspcon >May 24 03:30:21 BXT-2 kernel: [ 506.477295] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B >May 24 03:30:21 BXT-2 kernel: [ 506.477367] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT) >May 24 03:30:21 BXT-2 kernel: [ 506.479715] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 0.0 >May 24 03:30:21 BXT-2 kernel: [ 506.480217] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.481375] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.482559] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.483814] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.485287] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.486400] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.487902] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.488796] [drm:drm_dp_i2c_do_msg] too many retries, giving up >May 24 03:30:21 BXT-2 kernel: [ 506.489314] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.490176] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7) >May 24 03:30:21 BXT-2 kernel: [ 506.490498] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.491614] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.492741] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.493853] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.494919] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.496081] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:30:21 BXT-2 kernel: [ 506.496712] [drm:drm_dp_i2c_do_msg] too many retries, giving up >May 24 03:30:21 BXT-2 kernel: [ 506.496722] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -121) >May 24 03:30:21 BXT-2 kernel: [ 506.496798] [drm:lspcon_init [i915]] No LSPCON detected, found unknown >May 24 03:30:21 BXT-2 kernel: [ 506.496854] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon >May 24 03:30:21 BXT-2 kernel: [ 506.496939] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port B >May 24 03:30:21 BXT-2 kernel: [ 506.497074] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C >May 24 03:30:21 BXT-2 kernel: [ 506.497144] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT) >May 24 03:30:21 BXT-2 kernel: [ 506.497262] [drm:intel_dsi_init [i915]] >May 24 03:30:21 BXT-2 kernel: [ 506.497446] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.497639] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:30:21 BXT-2 kernel: [ 506.497708] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.497765] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:30:21 BXT-2 kernel: [ 506.497830] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.497886] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:30:21 BXT-2 kernel: [ 506.497947] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:30:21 BXT-2 kernel: [ 506.498005] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:30:21 BXT-2 kernel: [ 506.498064] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:30:21 BXT-2 kernel: [ 506.498124] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:30:21 BXT-2 kernel: [ 506.498180] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:30:21 BXT-2 kernel: [ 506.498236] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:30:21 BXT-2 kernel: [ 506.498291] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:30:21 BXT-2 kernel: [ 506.498350] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:30:21 BXT-2 kernel: [ 506.498406] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:30:21 BXT-2 kernel: [ 506.498494] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:30:21 BXT-2 kernel: [ 506.498553] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:30:21 BXT-2 kernel: [ 506.498664] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:30:21 BXT-2 kernel: [ 506.498728] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:30:21 BXT-2 kernel: [ 506.498798] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:30:21 BXT-2 kernel: [ 506.498855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.498911] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.498966] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:21 BXT-2 kernel: [ 506.498975] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.499031] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:21 BXT-2 kernel: [ 506.499037] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.499094] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.499150] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:30:21 BXT-2 kernel: [ 506.499206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.499263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:21 BXT-2 kernel: [ 506.499319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.499378] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.499434] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:21 BXT-2 kernel: [ 506.499530] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.499590] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.499650] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.499712] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.499777] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:30:21 BXT-2 kernel: [ 506.499836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.499894] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.499953] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:21 BXT-2 kernel: [ 506.499963] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.500019] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:21 BXT-2 kernel: [ 506.500025] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.500083] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.500142] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:30:21 BXT-2 kernel: [ 506.500202] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.500259] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:21 BXT-2 kernel: [ 506.500315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.500373] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.500430] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:21 BXT-2 kernel: [ 506.500536] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.500593] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.500650] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.500707] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.500769] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:30:21 BXT-2 kernel: [ 506.500825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.500881] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.500937] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:21 BXT-2 kernel: [ 506.500944] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.501000] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:21 BXT-2 kernel: [ 506.501006] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.501063] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.501120] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:30:21 BXT-2 kernel: [ 506.501176] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.501233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:21 BXT-2 kernel: [ 506.501289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.501346] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.501403] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:21 BXT-2 kernel: [ 506.501487] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.501548] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.501610] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.501826] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.501923] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:30:21 BXT-2 kernel: [ 506.501979] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.502088] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.502143] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.502200] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:21 BXT-2 kernel: [ 506.502253] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:21 BXT-2 kernel: [ 506.502846] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.503445] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000] >May 24 03:30:21 BXT-2 kernel: [ 506.644641] [drm:i915_gem_context_init [i915]] logical context support initialized >May 24 03:30:21 BXT-2 kernel: [ 506.645227] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfffff000 >May 24 03:30:21 BXT-2 kernel: [ 506.648062] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:30:21 BXT-2 kernel: [ 506.648146] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:30:21 BXT-2 kernel: [ 506.648283] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:30:21 BXT-2 kernel: [ 506.648420] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:30:21 BXT-2 kernel: [ 506.648747] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:30:21 BXT-2 kernel: [ 506.649804] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping >May 24 03:30:21 BXT-2 kernel: [ 506.649863] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping >May 24 03:30:21 BXT-2 kernel: [ 506.649918] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping >May 24 03:30:21 BXT-2 kernel: [ 506.649972] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config >May 24 03:30:21 BXT-2 kernel: [ 506.650386] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:30:21 BXT-2 kernel: [ 506.656831] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1 >May 24 03:30:21 BXT-2 kernel: [ 506.657987] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2 >May 24 03:30:21 BXT-2 kernel: [ 506.659024] [drm] Initialized i915 1.6.0 20170515 for 0000:00:02.0 on minor 0 >May 24 03:30:21 BXT-2 kernel: [ 506.660972] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:30:21 BXT-2 kernel: [ 506.675319] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) >May 24 03:30:21 BXT-2 kernel: [ 506.681766] [drm:asle_work [i915]] bclp = 0x80000005 >May 24 03:30:21 BXT-2 kernel: [ 506.681966] [drm:asle_work [i915]] updating opregion backlight 5/255 >May 24 03:30:21 BXT-2 kernel: [ 506.683701] [drm:asle_work [i915]] bclp = 0x800000ff >May 24 03:30:21 BXT-2 kernel: [ 506.683768] [drm:asle_work [i915]] updating opregion backlight 255/255 >May 24 03:30:21 BXT-2 kernel: [ 506.684265] acpi device:10: registered as cooling_device5 >May 24 03:30:21 BXT-2 kernel: [ 506.685241] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input62 >May 24 03:30:21 BXT-2 kernel: [ 506.686239] [drm] DRM_I915_DEBUG enabled >May 24 03:30:21 BXT-2 kernel: [ 506.686244] [drm] DRM_I915_DEBUG_GEM enabled >May 24 03:30:21 BXT-2 kernel: [ 506.686267] [drm:drm_setup_crtcs] >May 24 03:30:21 BXT-2 kernel: [ 506.686281] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:21 BXT-2 kernel: [ 506.686361] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:21 BXT-2 kernel: [ 506.686514] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.686595] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.686920] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:21 BXT-2 kernel: [ 506.686986] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.687040] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.687213] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.689791] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.689852] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.689939] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.689994] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.690053] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:21 BXT-2 kernel: [ 506.690106] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:21 BXT-2 kernel: [ 506.690731] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.690746] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] status updated from unknown to disconnected >May 24 03:30:21 BXT-2 kernel: [ 506.691372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:21 BXT-2 kernel: [ 506.691384] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:21 BXT-2 kernel: [ 506.691465] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:21 BXT-2 kernel: [ 506.691564] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.691619] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.691930] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:21 BXT-2 kernel: [ 506.691995] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.692050] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.692118] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.695225] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:21 BXT-2 kernel: [ 506.697468] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:21 BXT-2 kernel: [ 506.697553] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:21 BXT-2 kernel: [ 506.697609] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:21 BXT-2 kernel: [ 506.697664] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:21 BXT-2 kernel: [ 506.698226] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:21 BXT-2 kernel: [ 506.698286] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:21 BXT-2 kernel: [ 506.704118] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.704178] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.704247] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.704302] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.704359] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:21 BXT-2 kernel: [ 506.704412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:21 BXT-2 kernel: [ 506.705019] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.705031] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] status updated from unknown to connected >May 24 03:30:21 BXT-2 kernel: [ 506.705137] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:21 BXT-2 kernel: [ 506.705149] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:21 BXT-2 kernel: [ 506.705155] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705161] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705166] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705171] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705176] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705182] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705187] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:21 BXT-2 kernel: [ 506.705192] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705197] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.705202] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:21 BXT-2 kernel: [ 506.705207] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:21 BXT-2 kernel: [ 506.705212] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:21 BXT-2 kernel: [ 506.705237] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:30:21 BXT-2 kernel: [ 506.705241] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:30:21 BXT-2 kernel: [ 506.705307] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:30:21 BXT-2 kernel: [ 506.705318] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:30:21 BXT-2 kernel: [ 506.705323] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:30:21 BXT-2 kernel: [ 506.705327] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:30:21 BXT-2 kernel: [ 506.705330] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config >May 24 03:30:21 BXT-2 kernel: [ 506.705347] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:30:21 BXT-2 kernel: [ 506.705423] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one >May 24 03:30:21 BXT-2 kernel: [ 506.709221] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00040000 >May 24 03:30:21 BXT-2 kernel: [ 506.709956] fbcon: inteldrmfb (fb0) is primary device >May 24 03:30:21 BXT-2 kernel: [ 506.710777] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:21 BXT-2 kernel: [ 506.710835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:21 BXT-2 kernel: [ 506.710893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:21 BXT-2 kernel: [ 506.710950] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:21 BXT-2 kernel: [ 506.711005] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:21 BXT-2 kernel: [ 506.711062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.711118] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:21 BXT-2 kernel: [ 506.711174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.711230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:21 BXT-2 kernel: [ 506.711285] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.711340] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:21 BXT-2 kernel: [ 506.711348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.711402] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:21 BXT-2 kernel: [ 506.711426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.711483] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:21 BXT-2 kernel: [ 506.711538] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:21 BXT-2 kernel: [ 506.711593] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.711648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:21 BXT-2 kernel: [ 506.711703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:21 BXT-2 kernel: [ 506.711760] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.711815] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:21 BXT-2 kernel: [ 506.711872] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.711928] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.711983] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.712038] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:21 BXT-2 kernel: [ 506.712097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.712162] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:21 BXT-2 kernel: [ 506.712218] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:21 BXT-2 kernel: [ 506.712274] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.712965] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:21 BXT-2 kernel: [ 506.713028] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:21 BXT-2 kernel: [ 506.713341] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:21 BXT-2 kernel: [ 506.713412] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.713488] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:21 BXT-2 kernel: [ 506.713661] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:21 BXT-2 kernel: [ 506.723175] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.723565] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:21 BXT-2 kernel: [ 506.723623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:21 BXT-2 kernel: [ 506.723679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:21 BXT-2 kernel: [ 506.723735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:21 BXT-2 kernel: [ 506.723790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:21 BXT-2 kernel: [ 506.723846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:21 BXT-2 kernel: [ 506.723901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:21 BXT-2 kernel: [ 506.723957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:21 BXT-2 kernel: [ 506.724012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:21 BXT-2 kernel: [ 506.724068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:21 BXT-2 kernel: [ 506.724128] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:21 BXT-2 kernel: [ 506.724186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:21 BXT-2 kernel: [ 506.724478] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:21 BXT-2 kernel: [ 506.724574] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:21 BXT-2 kernel: [ 506.730272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:21 BXT-2 kernel: [ 506.730328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:21 BXT-2 kernel: [ 506.730385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:21 BXT-2 kernel: [ 506.731264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:21 BXT-2 kernel: [ 506.731320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:21 BXT-2 kernel: [ 506.732108] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:21 BXT-2 kernel: [ 506.732166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:21 BXT-2 kernel: [ 506.733274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:21 BXT-2 kernel: [ 506.734535] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:21 BXT-2 kernel: [ 506.735973] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:21 BXT-2 kernel: [ 506.753225] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:21 BXT-2 kernel: [ 506.753293] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:21 BXT-2 kernel: [ 506.753547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:21 BXT-2 kernel: [ 506.753944] Console: switching to colour frame buffer device 240x67 >May 24 03:30:21 BXT-2 kernel: [ 506.777714] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device >May 24 03:30:21 BXT-2 kernel: [ 506.797397] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) >May 24 03:30:21 BXT-2 kernel: [ 506.822137] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC283: line_outs=2 (0x1b/0x21/0x0/0x0/0x0) type:hp >May 24 03:30:21 BXT-2 kernel: [ 506.822146] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) >May 24 03:30:21 BXT-2 kernel: [ 506.822149] snd_hda_codec_realtek hdaudioC0D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0) >May 24 03:30:21 BXT-2 kernel: [ 506.822151] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.822153] snd_hda_codec_realtek hdaudioC0D0: dig-out=0x1e/0x0 >May 24 03:30:21 BXT-2 kernel: [ 506.822155] snd_hda_codec_realtek hdaudioC0D0: inputs: >May 24 03:30:21 BXT-2 kernel: [ 506.822158] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 >May 24 03:30:21 BXT-2 kernel: [ 506.822160] snd_hda_codec_realtek hdaudioC0D0: Internal Mic=0x12 >May 24 03:30:21 BXT-2 kernel: [ 506.886730] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:30:21 BXT-2 kernel: [ 506.886796] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:30:21 BXT-2 kernel: [ 506.886839] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:30:21 BXT-2 kernel: [ 506.886883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:30:21 BXT-2 kernel: [ 506.886926] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:30:21 BXT-2 kernel: [ 506.886969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:30:21 BXT-2 kernel: [ 506.887011] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:30:21 BXT-2 kernel: [ 506.887054] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:30:21 BXT-2 kernel: [ 506.887097] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:30:21 BXT-2 kernel: [ 506.894955] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input63 >May 24 03:30:21 BXT-2 kernel: [ 506.897727] input: HDA Intel PCH Headphone Front as /devices/pci0000:00/0000:00:0e.0/sound/card0/input64 >May 24 03:30:21 BXT-2 kernel: [ 506.898331] input: HDA Intel PCH Front Headphone Surround as /devices/pci0000:00/0000:00:0e.0/sound/card0/input65 >May 24 03:30:21 BXT-2 kernel: [ 506.898939] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input66 >May 24 03:30:21 BXT-2 kernel: [ 506.899557] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input67 >May 24 03:30:21 BXT-2 kernel: [ 506.900128] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input68 >May 24 03:30:21 BXT-2 kernel: [ 506.900722] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input69 >May 24 03:30:21 BXT-2 kernel: [ 506.901283] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input70 >May 24 03:30:21 BXT-2 kernel: [ 507.049673] Console: switching to colour dummy device 80x25 >May 24 03:30:21 BXT-2 kernel: [ 507.053176] [drm] RC6 on >May 24 03:30:21 BXT-2 kernel: [ 507.072023] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:21 BXT-2 kernel: [ 507.072167] [drm:drm_internal_framebuffer_create] buffer object handle for unused plane 1 >May 24 03:30:21 BXT-2 kernel: [ 507.088399] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:21 BXT-2 kernel: [ 507.153254] Console: switching to colour frame buffer device 240x67 >May 24 03:30:22 BXT-2 kernel: [ 507.364024] Console: switching to colour dummy device 80x25 >May 24 03:30:22 BXT-2 kernel: [ 507.386924] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:22 BXT-2 kernel: [ 507.387071] [drm:drm_internal_framebuffer_create] non-zero pitch for unused plane 1 >May 24 03:30:22 BXT-2 kernel: [ 507.400872] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:22 BXT-2 kernel: [ 507.453054] Console: switching to colour frame buffer device 240x67 >May 24 03:30:22 BXT-2 kernel: [ 507.649571] Console: switching to colour dummy device 80x25 >May 24 03:30:22 BXT-2 kernel: [ 507.667954] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:22 BXT-2 kernel: [ 507.668100] [drm:drm_internal_framebuffer_create] non-zero offset for unused plane 1 >May 24 03:30:22 BXT-2 kernel: [ 507.682260] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:22 BXT-2 kernel: [ 507.719711] Console: switching to colour frame buffer device 240x67 >May 24 03:30:22 BXT-2 kernel: [ 507.918550] Console: switching to colour dummy device 80x25 >May 24 03:30:22 BXT-2 kernel: [ 507.941987] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:22 BXT-2 kernel: [ 507.942126] [drm:drm_internal_framebuffer_create] non-zero modifier for unused plane 1 >May 24 03:30:22 BXT-2 kernel: [ 507.955873] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:22 BXT-2 kernel: [ 508.003040] Console: switching to colour frame buffer device 240x67 >May 24 03:30:22 BXT-2 kernel: [ 508.201288] Console: switching to colour dummy device 80x25 >May 24 03:30:22 BXT-2 kernel: [ 508.224864] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:22 BXT-2 kernel: [ 508.225033] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:22 BXT-2 kernel: [ 508.238752] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:22 BXT-2 kernel: [ 508.286390] Console: switching to colour frame buffer device 240x67 >May 24 03:30:23 BXT-2 kernel: [ 508.481280] Console: switching to colour dummy device 80x25 >May 24 03:30:23 BXT-2 kernel: [ 508.505001] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:23 BXT-2 kernel: [ 508.505210] [drm:drm_internal_framebuffer_create] no buffer object handle for plane 0 >May 24 03:30:23 BXT-2 kernel: [ 508.519180] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:23 BXT-2 kernel: [ 508.569697] Console: switching to colour frame buffer device 240x67 >May 24 03:30:23 BXT-2 kernel: [ 508.778500] Console: switching to colour dummy device 80x25 >May 24 03:30:23 BXT-2 kernel: [ 508.802869] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:23 BXT-2 kernel: [ 508.803088] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:23 BXT-2 kernel: [ 508.817216] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:23 BXT-2 kernel: [ 508.869707] Console: switching to colour frame buffer device 240x67 >May 24 03:30:23 BXT-2 kernel: [ 509.071611] Console: switching to colour dummy device 80x25 >May 24 03:30:23 BXT-2 kernel: [ 509.094019] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:23 BXT-2 kernel: [ 509.094218] [drm:drm_internal_framebuffer_create] bad pitch 0 for plane 0 >May 24 03:30:23 BXT-2 kernel: [ 509.107308] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:23 BXT-2 kernel: [ 509.153017] Console: switching to colour frame buffer device 240x67 >May 24 03:30:23 BXT-2 kernel: [ 509.349946] Console: switching to colour dummy device 80x25 >May 24 03:30:24 BXT-2 kernel: [ 509.370924] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:24 BXT-2 kernel: [ 509.371138] [drm:drm_internal_framebuffer_create] bad pitch 32 for plane 0 >May 24 03:30:24 BXT-2 kernel: [ 509.385061] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:24 BXT-2 kernel: [ 509.436437] Console: switching to colour frame buffer device 240x67 >May 24 03:30:24 BXT-2 kernel: [ 509.633193] Console: switching to colour dummy device 80x25 >May 24 03:30:24 BXT-2 kernel: [ 509.652849] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:24 BXT-2 kernel: [ 509.653057] [drm:drm_internal_framebuffer_create] bad pitch 63 for plane 0 >May 24 03:30:24 BXT-2 kernel: [ 509.667370] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:24 BXT-2 kernel: [ 509.719742] Console: switching to colour frame buffer device 240x67 >May 24 03:30:24 BXT-2 kernel: [ 509.923440] Console: switching to colour dummy device 80x25 >May 24 03:30:24 BXT-2 kernel: [ 509.941971] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:24 BXT-2 kernel: [ 509.942186] [drm:drm_internal_framebuffer_create] bad pitch 128 for plane 0 >May 24 03:30:24 BXT-2 kernel: [ 509.956312] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:24 BXT-2 kernel: [ 510.003051] Console: switching to colour frame buffer device 240x67 >May 24 03:30:24 BXT-2 kernel: [ 510.204314] Console: switching to colour dummy device 80x25 >May 24 03:30:24 BXT-2 kernel: [ 510.228912] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:24 BXT-2 kernel: [ 510.229115] [drm:drm_internal_framebuffer_create] bad pitch 256 for plane 0 >May 24 03:30:24 BXT-2 kernel: [ 510.243202] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:24 BXT-2 kernel: [ 510.286388] Console: switching to colour frame buffer device 240x67 >May 24 03:30:25 BXT-2 kernel: [ 510.490704] Console: switching to colour dummy device 80x25 >May 24 03:30:25 BXT-2 kernel: [ 510.517023] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:25 BXT-2 kernel: [ 510.517238] [drm:drm_internal_framebuffer_create] bad pitch 1024 for plane 0 >May 24 03:30:25 BXT-2 kernel: [ 510.531838] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:25 BXT-2 kernel: [ 510.586454] Console: switching to colour frame buffer device 240x67 >May 24 03:30:25 BXT-2 kernel: [ 510.781725] Console: switching to colour dummy device 80x25 >May 24 03:30:25 BXT-2 kernel: [ 510.801952] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:25 BXT-2 kernel: [ 510.802165] [drm:drm_internal_framebuffer_create] bad pitch 999 for plane 0 >May 24 03:30:25 BXT-2 kernel: [ 510.815621] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:25 BXT-2 kernel: [ 510.869784] Console: switching to colour frame buffer device 240x67 >May 24 03:30:25 BXT-2 kernel: [ 511.071156] Console: switching to colour dummy device 80x25 >May 24 03:30:25 BXT-2 kernel: [ 511.093880] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:25 BXT-2 kernel: [ 511.094148] [drm:intel_framebuffer_init [i915]] linear pitch (65536) must be at most 32768 >May 24 03:30:25 BXT-2 kernel: [ 511.094159] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:25 BXT-2 kernel: [ 511.107811] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:25 BXT-2 kernel: [ 511.153062] Console: switching to colour frame buffer device 240x67 >May 24 03:30:26 BXT-2 kernel: [ 511.357278] Console: switching to colour dummy device 80x25 >May 24 03:30:26 BXT-2 kernel: [ 511.375002] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 511.375317] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 511.375341] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 511.375363] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 511.388917] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 511.436453] Console: switching to colour frame buffer device 240x67 >May 24 03:30:26 BXT-2 kernel: [ 511.648813] Console: switching to colour dummy device 80x25 >May 24 03:30:26 BXT-2 kernel: [ 511.665872] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:26 BXT-2 kernel: [ 511.666179] [drm:drm_internal_framebuffer_create] bad pitch 4096 for plane 0 >May 24 03:30:26 BXT-2 kernel: [ 511.666185] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0 >May 24 03:30:26 BXT-2 kernel: [ 511.666190] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0 >May 24 03:30:26 BXT-2 kernel: [ 511.680304] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:26 BXT-2 kernel: [ 511.736473] Console: switching to colour frame buffer device 240x67 >May 24 03:30:26 BXT-2 kernel: [ 511.930843] Console: switching to colour dummy device 80x25 >May 24 03:30:26 BXT-2 kernel: [ 511.949983] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 511.950336] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes) >May 24 03:30:26 BXT-2 kernel: [ 511.950349] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:26 BXT-2 kernel: [ 511.950400] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes) >May 24 03:30:26 BXT-2 kernel: [ 511.950562] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:26 BXT-2 kernel: [ 511.950624] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4194304 bytes) >May 24 03:30:26 BXT-2 kernel: [ 511.950636] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:26 BXT-2 kernel: [ 511.963686] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:26 BXT-2 kernel: [ 512.003071] Console: switching to colour frame buffer device 240x67 >May 24 03:30:26 BXT-2 kernel: [ 512.200205] Console: switching to colour dummy device 80x25 >May 24 03:30:26 BXT-2 kernel: [ 512.218034] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:26 BXT-2 kernel: [ 512.218395] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4198400 bytes, have 4190208 bytes) >May 24 03:30:26 BXT-2 kernel: [ 512.218783] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:26 BXT-2 kernel: [ 512.231877] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:26 BXT-2 kernel: [ 512.269739] Console: switching to colour frame buffer device 240x67 >May 24 03:30:27 BXT-2 kernel: [ 512.466714] Console: switching to colour dummy device 80x25 >May 24 03:30:27 BXT-2 kernel: [ 512.488888] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:27 BXT-2 kernel: [ 512.489197] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:27 BXT-2 kernel: [ 512.502795] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:27 BXT-2 kernel: [ 512.553060] Console: switching to colour frame buffer device 240x67 >May 24 03:30:27 BXT-2 kernel: [ 512.757583] Console: switching to colour dummy device 80x25 >May 24 03:30:27 BXT-2 kernel: [ 512.775950] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:27 BXT-2 kernel: [ 512.776328] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4194304 bytes, have 4190208 bytes) >May 24 03:30:27 BXT-2 kernel: [ 512.776340] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:27 BXT-2 kernel: [ 512.789753] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:27 BXT-2 kernel: [ 512.836384] Console: switching to colour frame buffer device 240x67 >May 24 03:30:27 BXT-2 kernel: [ 513.035723] Console: switching to colour dummy device 80x25 >May 24 03:30:27 BXT-2 kernel: [ 513.062980] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:27 BXT-2 kernel: [ 513.063363] [drm:drm_internal_framebuffer_create] bad fb modifier 72057594037927937 for plane 0 >May 24 03:30:27 BXT-2 kernel: [ 513.077092] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:27 BXT-2 kernel: [ 513.119828] Console: switching to colour frame buffer device 240x67 >May 24 03:30:27 BXT-2 kernel: [ 513.321628] Console: switching to colour dummy device 80x25 >May 24 03:30:27 BXT-2 kernel: [ 513.345902] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:27 BXT-2 kernel: [ 513.346314] [drm:intel_framebuffer_init [i915]] Unsupported fb modifier 0xffffffffffffffff! >May 24 03:30:27 BXT-2 kernel: [ 513.346325] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:28 BXT-2 kernel: [ 513.360647] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:28 BXT-2 kernel: [ 513.403110] Console: switching to colour frame buffer device 240x67 >May 24 03:30:28 BXT-2 kernel: [ 513.616826] Console: switching to colour dummy device 80x25 >May 24 03:30:28 BXT-2 kernel: [ 513.631432] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:28 BXT-2 kernel: [ 513.631886] [drm:intel_framebuffer_init [i915]] tiling_mode doesn't match fb modifier >May 24 03:30:28 BXT-2 kernel: [ 513.631899] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:28 BXT-2 kernel: [ 513.644909] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:28 BXT-2 kernel: [ 513.686447] Console: switching to colour frame buffer device 240x67 >May 24 03:30:28 BXT-2 kernel: [ 513.895465] Console: switching to colour dummy device 80x25 >May 24 03:30:28 BXT-2 kernel: [ 513.912996] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:28 BXT-2 kernel: [ 513.913373] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:28 BXT-2 kernel: [ 513.926585] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:28 BXT-2 kernel: [ 513.986466] Console: switching to colour frame buffer device 240x67 >May 24 03:30:28 BXT-2 kernel: [ 514.194770] Console: switching to colour dummy device 80x25 >May 24 03:30:28 BXT-2 kernel: [ 514.209903] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:28 BXT-2 kernel: [ 514.210287] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:28 BXT-2 kernel: [ 514.223505] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:28 BXT-2 kernel: [ 514.269784] Console: switching to colour frame buffer device 240x67 >May 24 03:30:29 BXT-2 kernel: [ 514.466488] Console: switching to colour dummy device 80x25 >May 24 03:30:29 BXT-2 kernel: [ 514.487872] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:29 BXT-2 kernel: [ 514.488358] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:29 BXT-2 kernel: [ 514.502111] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:29 BXT-2 kernel: [ 514.553076] Console: switching to colour frame buffer device 240x67 >May 24 03:30:29 BXT-2 kernel: [ 514.752223] Console: switching to colour dummy device 80x25 >May 24 03:30:29 BXT-2 kernel: [ 514.765903] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:29 BXT-2 kernel: [ 514.766392] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:29 BXT-2 kernel: [ 514.779525] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:29 BXT-2 kernel: [ 514.836392] Console: switching to colour frame buffer device 240x67 >May 24 03:30:29 BXT-2 kernel: [ 515.045651] Console: switching to colour dummy device 80x25 >May 24 03:30:29 BXT-2 kernel: [ 515.063973] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:29 BXT-2 kernel: [ 515.064557] [drm:intel_framebuffer_init [i915]] fb too big for bo (need 4194304 bytes, have 4190208 bytes) >May 24 03:30:29 BXT-2 kernel: [ 515.064570] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:29 BXT-2 kernel: [ 515.077727] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:29 BXT-2 kernel: [ 515.119813] Console: switching to colour frame buffer device 240x67 >May 24 03:30:29 BXT-2 kernel: [ 515.320113] Console: switching to colour dummy device 80x25 >May 24 03:30:29 BXT-2 kernel: [ 515.344943] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:30 BXT-2 kernel: [ 515.358197] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:30 BXT-2 kernel: [ 515.358341] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:30 BXT-2 kernel: [ 515.403056] Console: switching to colour frame buffer device 240x67 >May 24 03:30:30 BXT-2 kernel: [ 515.602920] Console: switching to colour dummy device 80x25 >May 24 03:30:30 BXT-2 kernel: [ 515.619249] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:30 BXT-2 kernel: [ 515.632916] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:30 BXT-2 kernel: [ 515.633273] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:30 BXT-2 kernel: [ 515.686423] Console: switching to colour frame buffer device 240x67 >May 24 03:30:30 BXT-2 kernel: [ 515.903533] Console: switching to colour dummy device 80x25 >May 24 03:30:30 BXT-2 kernel: [ 515.925909] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:30 BXT-2 kernel: [ 515.939879] [drm:intel_framebuffer_init [i915]] pitch (2048) must match tiling stride (4096) >May 24 03:30:30 BXT-2 kernel: [ 515.939893] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:30 BXT-2 kernel: [ 515.940249] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:30 BXT-2 kernel: [ 515.986463] Console: switching to colour frame buffer device 240x67 >May 24 03:30:30 BXT-2 kernel: [ 516.202656] Console: switching to colour dummy device 80x25 >May 24 03:30:30 BXT-2 kernel: [ 516.223845] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:30 BXT-2 kernel: [ 516.237685] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb >May 24 03:30:30 BXT-2 kernel: [ 516.237701] [drm:drm_internal_framebuffer_create] could not create framebuffer >May 24 03:30:30 BXT-2 kernel: [ 516.237832] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:30 BXT-2 kernel: [ 516.286470] Console: switching to colour frame buffer device 240x67 >May 24 03:30:31 BXT-2 kernel: [ 516.498577] Console: switching to colour dummy device 80x25 >May 24 03:30:31 BXT-2 kernel: [ 516.512187] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:31 BXT-2 kernel: [ 516.526301] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:31 BXT-2 kernel: [ 516.569753] Console: switching to colour frame buffer device 240x67 >May 24 03:30:31 BXT-2 kernel: [ 516.781201] Console: switching to colour dummy device 80x25 >May 24 03:30:31 BXT-2 kernel: [ 516.804836] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:31 BXT-2 kernel: [ 516.818558] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:31 BXT-2 kernel: [ 516.869750] Console: switching to colour frame buffer device 240x67 >May 24 03:30:31 BXT-2 kernel: [ 517.090532] Console: switching to colour dummy device 80x25 >May 24 03:30:31 BXT-2 kernel: [ 517.112970] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:31 BXT-2 kernel: [ 517.126753] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:31 BXT-2 kernel: [ 517.152948] [drm:drm_fb_helper_hotplug_event] >May 24 03:30:31 BXT-2 kernel: [ 517.152955] [drm:drm_setup_crtcs] >May 24 03:30:31 BXT-2 kernel: [ 517.152965] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:31 BXT-2 kernel: [ 517.153021] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:31 BXT-2 kernel: [ 517.153076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:31 BXT-2 kernel: [ 517.153083] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:31 BXT-2 kernel: [ 517.153132] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:31 BXT-2 kernel: [ 517.155102] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:31 BXT-2 kernel: [ 517.156081] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:31 BXT-2 kernel: [ 517.156126] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:31 BXT-2 kernel: [ 517.156169] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:31 BXT-2 kernel: [ 517.156211] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:31 BXT-2 kernel: [ 517.156868] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:31 BXT-2 kernel: [ 517.156912] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:31 BXT-2 kernel: [ 517.161641] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:31 BXT-2 kernel: [ 517.161710] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:31 BXT-2 kernel: [ 517.161718] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161723] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161728] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161733] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161738] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161744] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161749] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:31 BXT-2 kernel: [ 517.161754] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161759] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:31 BXT-2 kernel: [ 517.161764] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:31 BXT-2 kernel: [ 517.161769] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:31 BXT-2 kernel: [ 517.161774] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:31 BXT-2 kernel: [ 517.161804] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:30:31 BXT-2 kernel: [ 517.161808] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:30:31 BXT-2 kernel: [ 517.161870] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:30:31 BXT-2 kernel: [ 517.161880] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:30:31 BXT-2 kernel: [ 517.161884] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:30:31 BXT-2 kernel: [ 517.161888] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:30:31 BXT-2 kernel: [ 517.161892] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:30:31 BXT-2 kernel: [ 517.161912] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:30:31 BXT-2 kernel: [ 517.186478] Console: switching to colour frame buffer device 240x67 >May 24 03:30:32 BXT-2 kernel: [ 517.403627] Console: switching to colour dummy device 80x25 >May 24 03:30:32 BXT-2 kernel: [ 517.424910] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:32 BXT-2 kernel: [ 517.439146] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:32 BXT-2 kernel: [ 517.486462] Console: switching to colour frame buffer device 240x67 >May 24 03:30:32 BXT-2 kernel: [ 517.692836] Console: switching to colour dummy device 80x25 >May 24 03:30:32 BXT-2 kernel: [ 517.721071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:32 BXT-2 kernel: [ 517.721129] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:32 BXT-2 kernel: [ 517.721195] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:32 BXT-2 kernel: [ 517.721588] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:32 BXT-2 kernel: [ 517.721649] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:32 BXT-2 kernel: [ 517.723379] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:32 BXT-2 kernel: [ 517.724381] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:32 BXT-2 kernel: [ 517.724426] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:32 BXT-2 kernel: [ 517.724662] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:32 BXT-2 kernel: [ 517.724706] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:32 BXT-2 kernel: [ 517.725215] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:32 BXT-2 kernel: [ 517.725258] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:32 BXT-2 kernel: [ 517.730153] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:32 BXT-2 kernel: [ 517.730217] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:32 BXT-2 kernel: [ 517.730225] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730230] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730235] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730240] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730245] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730250] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730255] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:32 BXT-2 kernel: [ 517.730260] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730265] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.730270] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:32 BXT-2 kernel: [ 517.730275] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:32 BXT-2 kernel: [ 517.730280] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:32 BXT-2 kernel: [ 517.730788] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:32 BXT-2 kernel: [ 517.730834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:32 BXT-2 kernel: [ 517.730879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:32 BXT-2 kernel: [ 517.730923] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:32 BXT-2 kernel: [ 517.730966] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:32 BXT-2 kernel: [ 517.731011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:32 BXT-2 kernel: [ 517.731055] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:32 BXT-2 kernel: [ 517.731098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:32 BXT-2 kernel: [ 517.731142] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:32 BXT-2 kernel: [ 517.731185] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:32 BXT-2 kernel: [ 517.731227] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:32 BXT-2 kernel: [ 517.731235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.731278] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:32 BXT-2 kernel: [ 517.731284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.731328] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:32 BXT-2 kernel: [ 517.731371] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:32 BXT-2 kernel: [ 517.731415] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:32 BXT-2 kernel: [ 517.731608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:32 BXT-2 kernel: [ 517.731651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:32 BXT-2 kernel: [ 517.731696] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:32 BXT-2 kernel: [ 517.731738] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:32 BXT-2 kernel: [ 517.731784] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:32 BXT-2 kernel: [ 517.731827] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:32 BXT-2 kernel: [ 517.731870] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:32 BXT-2 kernel: [ 517.731914] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:32 BXT-2 kernel: [ 517.731959] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:32 BXT-2 kernel: [ 517.732010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:32 BXT-2 kernel: [ 517.732064] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:32 BXT-2 kernel: [ 517.732107] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:32 BXT-2 kernel: [ 517.732531] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:32 BXT-2 kernel: [ 517.736917] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:32 BXT-2 kernel: [ 517.737101] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:32 BXT-2 kernel: [ 517.737165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:32 BXT-2 kernel: [ 517.737209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:32 BXT-2 kernel: [ 517.737252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:32 BXT-2 kernel: [ 517.737294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:32 BXT-2 kernel: [ 517.737337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:32 BXT-2 kernel: [ 517.737380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:32 BXT-2 kernel: [ 517.737422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:32 BXT-2 kernel: [ 517.737515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:32 BXT-2 kernel: [ 517.737560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:32 BXT-2 kernel: [ 517.737607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:32 BXT-2 kernel: [ 517.737652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:32 BXT-2 kernel: [ 517.737727] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:32 BXT-2 kernel: [ 517.737770] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:32 BXT-2 kernel: [ 517.740933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:32 BXT-2 kernel: [ 517.740980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:32 BXT-2 kernel: [ 517.741026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:32 BXT-2 kernel: [ 517.741861] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:32 BXT-2 kernel: [ 517.741906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:32 BXT-2 kernel: [ 517.742965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:32 BXT-2 kernel: [ 517.745063] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:32 BXT-2 kernel: [ 517.746049] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:32 BXT-2 kernel: [ 517.746346] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:32 BXT-2 kernel: [ 517.746399] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:32 BXT-2 kernel: [ 517.746613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:32 BXT-2 kernel: [ 517.775458] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:32 BXT-2 kernel: [ 517.993190] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:32 BXT-2 kernel: [ 517.993259] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:32 BXT-2 kernel: [ 518.012814] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:32 BXT-2 kernel: [ 518.013269] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:32 BXT-2 kernel: [ 518.025497] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:33 BXT-2 kernel: [ 518.697304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:33 BXT-2 kernel: [ 518.697950] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:33 BXT-2 kernel: [ 518.715335] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:33 BXT-2 kernel: [ 518.715705] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 518.715833] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 518.716164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 518.716207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:33 BXT-2 kernel: [ 518.716250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 518.716293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 518.716337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 518.716380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:33 BXT-2 kernel: [ 518.716427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 518.716857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 518.716900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 518.716943] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 518.716992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:33 BXT-2 kernel: [ 518.717037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:33 BXT-2 kernel: [ 518.717082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 518.717193] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:33 BXT-2 kernel: [ 518.717274] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 518.717416] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 518.717905] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:33 BXT-2 kernel: [ 518.717974] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:33 BXT-2 kernel: [ 518.718018] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:33 BXT-2 kernel: [ 518.718056] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:33 BXT-2 kernel: [ 518.719221] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:33 BXT-2 kernel: [ 518.762298] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:33 BXT-2 kernel: [ 518.762356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:33 BXT-2 kernel: [ 518.762399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:33 BXT-2 kernel: [ 518.762476] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:33 BXT-2 kernel: [ 518.762517] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:33 BXT-2 kernel: [ 518.762561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:33 BXT-2 kernel: [ 518.762603] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:33 BXT-2 kernel: [ 518.762645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:33 BXT-2 kernel: [ 518.762686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:33 BXT-2 kernel: [ 518.762727] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:33 BXT-2 kernel: [ 518.762768] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:33 BXT-2 kernel: [ 518.762776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:33 BXT-2 kernel: [ 518.762816] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:33 BXT-2 kernel: [ 518.762821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:33 BXT-2 kernel: [ 518.762862] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:33 BXT-2 kernel: [ 518.762904] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:33 BXT-2 kernel: [ 518.762946] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:33 BXT-2 kernel: [ 518.762987] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:33 BXT-2 kernel: [ 518.763028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:33 BXT-2 kernel: [ 518.763071] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:33 BXT-2 kernel: [ 518.763112] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:33 BXT-2 kernel: [ 518.763154] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 518.763195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 518.763236] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 518.763277] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 518.763321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:33 BXT-2 kernel: [ 518.763371] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 518.763413] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:33 BXT-2 kernel: [ 518.763625] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:33 BXT-2 kernel: [ 518.763674] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:33 BXT-2 kernel: [ 518.763973] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:33 BXT-2 kernel: [ 518.764027] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 518.764066] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 518.764242] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:33 BXT-2 kernel: [ 518.765870] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 518.766212] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 518.766255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:33 BXT-2 kernel: [ 518.766297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 518.766339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 518.766381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 518.766422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:33 BXT-2 kernel: [ 518.766490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 518.766532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 518.766574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 518.766615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:33 BXT-2 kernel: [ 518.766662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:33 BXT-2 kernel: [ 518.766705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 518.766808] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:33 BXT-2 kernel: [ 518.766860] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 518.769923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:33 BXT-2 kernel: [ 518.769965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:33 BXT-2 kernel: [ 518.770009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:33 BXT-2 kernel: [ 518.770783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:33 BXT-2 kernel: [ 518.770824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:33 BXT-2 kernel: [ 518.771554] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:33 BXT-2 kernel: [ 518.771596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:33 BXT-2 kernel: [ 518.772647] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:33 BXT-2 kernel: [ 518.774758] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:33 BXT-2 kernel: [ 518.776018] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:33 BXT-2 kernel: [ 518.792900] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 518.792951] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:33 BXT-2 kernel: [ 518.793127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 518.793524] Console: switching to colour frame buffer device 240x67 >May 24 03:30:33 BXT-2 kernel: [ 518.997878] Console: switching to colour dummy device 80x25 >May 24 03:30:33 BXT-2 kernel: [ 519.018525] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:33 BXT-2 kernel: [ 519.018584] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:33 BXT-2 kernel: [ 519.018601] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:33 BXT-2 kernel: [ 519.018928] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 519.018974] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 519.019642] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:33 BXT-2 kernel: [ 519.020526] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:33 BXT-2 kernel: [ 519.020572] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:33 BXT-2 kernel: [ 519.020615] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:33 BXT-2 kernel: [ 519.020657] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:33 BXT-2 kernel: [ 519.021140] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:33 BXT-2 kernel: [ 519.021182] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:33 BXT-2 kernel: [ 519.025931] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:33 BXT-2 kernel: [ 519.025996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:33 BXT-2 kernel: [ 519.026003] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026009] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026014] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026019] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026024] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026029] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026034] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:33 BXT-2 kernel: [ 519.026039] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026044] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.026049] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:33 BXT-2 kernel: [ 519.026054] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:33 BXT-2 kernel: [ 519.026059] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:33 BXT-2 kernel: [ 519.038923] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:33 BXT-2 kernel: [ 519.114907] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:33 BXT-2 kernel: [ 519.115080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:33 BXT-2 kernel: [ 519.115252] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:33 BXT-2 kernel: [ 519.126824] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:33 BXT-2 kernel: [ 519.126935] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 519.127054] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 519.127391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 519.127702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:33 BXT-2 kernel: [ 519.127746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 519.127789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 519.127831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 519.127874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:33 BXT-2 kernel: [ 519.127923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 519.127966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 519.128008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 519.128051] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 519.128099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:33 BXT-2 kernel: [ 519.128144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:33 BXT-2 kernel: [ 519.128188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 519.128303] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:33 BXT-2 kernel: [ 519.128385] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 519.129078] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 519.129147] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:33 BXT-2 kernel: [ 519.129205] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:33 BXT-2 kernel: [ 519.129248] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:33 BXT-2 kernel: [ 519.129286] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:33 BXT-2 kernel: [ 519.130473] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:33 BXT-2 kernel: [ 519.131767] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:33 BXT-2 kernel: [ 519.131822] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 519.131942] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:33 BXT-2 kernel: [ 519.131985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:33 BXT-2 kernel: [ 519.132030] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:33 BXT-2 kernel: [ 519.132074] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:33 BXT-2 kernel: [ 519.132116] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:33 BXT-2 kernel: [ 519.132159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:33 BXT-2 kernel: [ 519.132202] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:30:33 BXT-2 kernel: [ 519.132245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:30:33 BXT-2 kernel: [ 519.132288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:33 BXT-2 kernel: [ 519.132330] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:33 BXT-2 kernel: [ 519.132372] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:33 BXT-2 kernel: [ 519.132379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.132420] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:33 BXT-2 kernel: [ 519.132981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.133040] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:33 BXT-2 kernel: [ 519.133083] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:33 BXT-2 kernel: [ 519.133126] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:30:33 BXT-2 kernel: [ 519.133169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:33 BXT-2 kernel: [ 519.133211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:33 BXT-2 kernel: [ 519.133255] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:30:33 BXT-2 kernel: [ 519.133297] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:33 BXT-2 kernel: [ 519.133341] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 519.133384] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 519.133426] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 519.133888] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:30:33 BXT-2 kernel: [ 519.133959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:33 BXT-2 kernel: [ 519.134013] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 519.134056] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:30:33 BXT-2 kernel: [ 519.134099] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:30:33 BXT-2 kernel: [ 519.135062] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:33 BXT-2 kernel: [ 519.135102] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:33 BXT-2 kernel: [ 519.135392] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:33 BXT-2 kernel: [ 519.136026] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 519.136068] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:33 BXT-2 kernel: [ 519.136169] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:33 BXT-2 kernel: [ 519.138178] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 519.138702] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:33 BXT-2 kernel: [ 519.138752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:33 BXT-2 kernel: [ 519.138796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 519.138838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 519.138881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 519.138924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:33 BXT-2 kernel: [ 519.138967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:33 BXT-2 kernel: [ 519.139009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:33 BXT-2 kernel: [ 519.139052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:33 BXT-2 kernel: [ 519.139095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:33 BXT-2 kernel: [ 519.139143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:33 BXT-2 kernel: [ 519.139188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 519.139262] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:30:33 BXT-2 kernel: [ 519.139305] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 519.140946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:33 BXT-2 kernel: [ 519.140991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:33 BXT-2 kernel: [ 519.141035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:33 BXT-2 kernel: [ 519.141849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:33 BXT-2 kernel: [ 519.141894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:33 BXT-2 kernel: [ 519.142629] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:33 BXT-2 kernel: [ 519.142674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:33 BXT-2 kernel: [ 519.143742] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:33 BXT-2 kernel: [ 519.145841] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:33 BXT-2 kernel: [ 519.146901] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:30:33 BXT-2 kernel: [ 519.163797] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:33 BXT-2 kernel: [ 519.163853] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:30:33 BXT-2 kernel: [ 519.164024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:33 BXT-2 kernel: [ 519.180338] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:33 BXT-2 kernel: [ 519.192499] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:34 BXT-2 kernel: [ 519.848606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:34 BXT-2 kernel: [ 519.848794] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:30:34 BXT-2 kernel: [ 519.865420] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:30:34 BXT-2 kernel: [ 519.865585] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 519.865674] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 519.867350] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 519.867399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:34 BXT-2 kernel: [ 519.867853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 519.867897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 519.867940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 519.867983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:34 BXT-2 kernel: [ 519.868035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 519.868078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 519.868121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 519.868164] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 519.868211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:34 BXT-2 kernel: [ 519.868257] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:34 BXT-2 kernel: [ 519.868301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 519.868373] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:34 BXT-2 kernel: [ 519.868416] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 519.869308] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 519.869376] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:30:34 BXT-2 kernel: [ 519.869426] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:34 BXT-2 kernel: [ 519.870018] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:34 BXT-2 kernel: [ 519.870058] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:34 BXT-2 kernel: [ 519.871291] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:34 BXT-2 kernel: [ 519.896419] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:34 BXT-2 kernel: [ 519.896498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:34 BXT-2 kernel: [ 519.896542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:34 BXT-2 kernel: [ 519.896584] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:34 BXT-2 kernel: [ 519.896625] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:34 BXT-2 kernel: [ 519.896668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:34 BXT-2 kernel: [ 519.896710] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:34 BXT-2 kernel: [ 519.896752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:34 BXT-2 kernel: [ 519.896794] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:34 BXT-2 kernel: [ 519.896835] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:34 BXT-2 kernel: [ 519.896875] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:34 BXT-2 kernel: [ 519.896883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:34 BXT-2 kernel: [ 519.896923] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:34 BXT-2 kernel: [ 519.896928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:34 BXT-2 kernel: [ 519.896970] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:34 BXT-2 kernel: [ 519.897011] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:34 BXT-2 kernel: [ 519.897053] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:34 BXT-2 kernel: [ 519.897094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:34 BXT-2 kernel: [ 519.897135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:34 BXT-2 kernel: [ 519.897178] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:34 BXT-2 kernel: [ 519.897219] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:34 BXT-2 kernel: [ 519.897260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 519.897301] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 519.897342] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 519.897384] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 519.897428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:34 BXT-2 kernel: [ 519.897502] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 519.897545] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:34 BXT-2 kernel: [ 519.897677] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:34 BXT-2 kernel: [ 519.897713] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:34 BXT-2 kernel: [ 519.898001] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:34 BXT-2 kernel: [ 519.898055] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 519.898095] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 519.898150] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:34 BXT-2 kernel: [ 519.898384] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 519.898707] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 519.898750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:34 BXT-2 kernel: [ 519.898792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 519.898833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 519.898874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 519.898916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:34 BXT-2 kernel: [ 519.898957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 519.898999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 519.899040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 519.899082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:34 BXT-2 kernel: [ 519.899127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:34 BXT-2 kernel: [ 519.899171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 519.899244] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:34 BXT-2 kernel: [ 519.899285] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 519.900730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:34 BXT-2 kernel: [ 519.900771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:34 BXT-2 kernel: [ 519.900814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:34 BXT-2 kernel: [ 519.901675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:34 BXT-2 kernel: [ 519.901716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:34 BXT-2 kernel: [ 519.902429] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:34 BXT-2 kernel: [ 519.902488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:34 BXT-2 kernel: [ 519.903517] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:34 BXT-2 kernel: [ 519.905595] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:34 BXT-2 kernel: [ 519.906757] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:34 BXT-2 kernel: [ 519.923654] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 519.923708] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:34 BXT-2 kernel: [ 519.923885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 519.924242] Console: switching to colour frame buffer device 240x67 >May 24 03:30:34 BXT-2 kernel: [ 520.152467] Console: switching to colour dummy device 80x25 >May 24 03:30:34 BXT-2 kernel: [ 520.174566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:34 BXT-2 kernel: [ 520.174628] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:34 BXT-2 kernel: [ 520.174644] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:34 BXT-2 kernel: [ 520.174967] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 520.175013] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 520.175628] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:34 BXT-2 kernel: [ 520.176573] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:34 BXT-2 kernel: [ 520.176618] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:34 BXT-2 kernel: [ 520.176660] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:34 BXT-2 kernel: [ 520.176702] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:34 BXT-2 kernel: [ 520.177183] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:34 BXT-2 kernel: [ 520.177225] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:34 BXT-2 kernel: [ 520.182154] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:34 BXT-2 kernel: [ 520.182216] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:34 BXT-2 kernel: [ 520.182223] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182228] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182233] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182238] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182243] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182248] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182253] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:34 BXT-2 kernel: [ 520.182258] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182263] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.182268] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:34 BXT-2 kernel: [ 520.182274] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:34 BXT-2 kernel: [ 520.182279] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:34 BXT-2 kernel: [ 520.195523] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:34 BXT-2 kernel: [ 520.272738] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:34 BXT-2 kernel: [ 520.272915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:34 BXT-2 kernel: [ 520.273090] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:34 BXT-2 kernel: [ 520.275410] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:34 BXT-2 kernel: [ 520.275546] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 520.275634] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 520.275950] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 520.275994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:34 BXT-2 kernel: [ 520.276037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 520.276080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 520.276123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 520.276165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:34 BXT-2 kernel: [ 520.276211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 520.276254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 520.276296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 520.276339] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 520.276386] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:34 BXT-2 kernel: [ 520.276431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:34 BXT-2 kernel: [ 520.277073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 520.277135] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:34 BXT-2 kernel: [ 520.277177] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 520.277230] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 520.277291] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:34 BXT-2 kernel: [ 520.277343] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:34 BXT-2 kernel: [ 520.277386] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:34 BXT-2 kernel: [ 520.277424] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:34 BXT-2 kernel: [ 520.278355] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:34 BXT-2 kernel: [ 520.279578] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:34 BXT-2 kernel: [ 520.281457] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:34 BXT-2 kernel: [ 520.281508] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 520.281624] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:34 BXT-2 kernel: [ 520.281669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:34 BXT-2 kernel: [ 520.281714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:34 BXT-2 kernel: [ 520.281757] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:34 BXT-2 kernel: [ 520.281799] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:34 BXT-2 kernel: [ 520.281843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:34 BXT-2 kernel: [ 520.281886] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:30:34 BXT-2 kernel: [ 520.281929] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:30:34 BXT-2 kernel: [ 520.281972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:34 BXT-2 kernel: [ 520.282014] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:34 BXT-2 kernel: [ 520.282056] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:34 BXT-2 kernel: [ 520.282062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.282104] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:34 BXT-2 kernel: [ 520.282110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.282152] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:34 BXT-2 kernel: [ 520.282195] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:34 BXT-2 kernel: [ 520.282237] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:30:34 BXT-2 kernel: [ 520.282280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:34 BXT-2 kernel: [ 520.282322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:34 BXT-2 kernel: [ 520.282366] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:30:34 BXT-2 kernel: [ 520.282408] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:34 BXT-2 kernel: [ 520.282484] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 520.282528] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 520.282572] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:30:34 BXT-2 kernel: [ 520.282634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:34 BXT-2 kernel: [ 520.282689] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 520.282734] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:30:34 BXT-2 kernel: [ 520.282780] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:30:34 BXT-2 kernel: [ 520.283379] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:34 BXT-2 kernel: [ 520.283418] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:34 BXT-2 kernel: [ 520.283777] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:34 BXT-2 kernel: [ 520.283835] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 520.283877] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:34 BXT-2 kernel: [ 520.283934] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:34 BXT-2 kernel: [ 520.284189] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 520.284516] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:34 BXT-2 kernel: [ 520.284562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:34 BXT-2 kernel: [ 520.284605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 520.284648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 520.284691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 520.284734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:34 BXT-2 kernel: [ 520.284778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:34 BXT-2 kernel: [ 520.284821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:34 BXT-2 kernel: [ 520.284864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:34 BXT-2 kernel: [ 520.284908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:34 BXT-2 kernel: [ 520.284956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:34 BXT-2 kernel: [ 520.285001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 520.285076] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:30:34 BXT-2 kernel: [ 520.285120] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 520.286650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:34 BXT-2 kernel: [ 520.286696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:34 BXT-2 kernel: [ 520.286741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:34 BXT-2 kernel: [ 520.287531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:34 BXT-2 kernel: [ 520.287576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:34 BXT-2 kernel: [ 520.288350] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:34 BXT-2 kernel: [ 520.288396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:34 BXT-2 kernel: [ 520.289616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:34 BXT-2 kernel: [ 520.291713] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:34 BXT-2 kernel: [ 520.292716] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:30:34 BXT-2 kernel: [ 520.309582] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:34 BXT-2 kernel: [ 520.309640] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:30:34 BXT-2 kernel: [ 520.309810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:34 BXT-2 kernel: [ 520.338072] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:35 BXT-2 kernel: [ 520.994198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:35 BXT-2 kernel: [ 520.994346] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:30:35 BXT-2 kernel: [ 521.009833] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:30:35 BXT-2 kernel: [ 521.009988] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:35 BXT-2 kernel: [ 521.010082] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:35 BXT-2 kernel: [ 521.010412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:35 BXT-2 kernel: [ 521.010517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:35 BXT-2 kernel: [ 521.010561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:35 BXT-2 kernel: [ 521.010606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:35 BXT-2 kernel: [ 521.010649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:35 BXT-2 kernel: [ 521.010692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:35 BXT-2 kernel: [ 521.010742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:35 BXT-2 kernel: [ 521.010785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:35 BXT-2 kernel: [ 521.010828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:35 BXT-2 kernel: [ 521.010871] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:35 BXT-2 kernel: [ 521.010919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:35 BXT-2 kernel: [ 521.010966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:35 BXT-2 kernel: [ 521.011011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:35 BXT-2 kernel: [ 521.011077] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:35 BXT-2 kernel: [ 521.011120] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:35 BXT-2 kernel: [ 521.011174] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:35 BXT-2 kernel: [ 521.011235] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:30:35 BXT-2 kernel: [ 521.011279] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:35 BXT-2 kernel: [ 521.011322] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:35 BXT-2 kernel: [ 521.011361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:35 BXT-2 kernel: [ 521.011969] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:35 BXT-2 kernel: [ 521.036501] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:35 BXT-2 kernel: [ 521.036544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:35 BXT-2 kernel: [ 521.036588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:35 BXT-2 kernel: [ 521.036631] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:35 BXT-2 kernel: [ 521.036672] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:35 BXT-2 kernel: [ 521.036715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:35 BXT-2 kernel: [ 521.036757] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:35 BXT-2 kernel: [ 521.036799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:35 BXT-2 kernel: [ 521.036841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:35 BXT-2 kernel: [ 521.036882] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:35 BXT-2 kernel: [ 521.036922] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:35 BXT-2 kernel: [ 521.036929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.036970] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:35 BXT-2 kernel: [ 521.036975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.037017] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.037058] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:35 BXT-2 kernel: [ 521.037100] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:35 BXT-2 kernel: [ 521.037141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:35 BXT-2 kernel: [ 521.037182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:35 BXT-2 kernel: [ 521.037225] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:35 BXT-2 kernel: [ 521.037266] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:35 BXT-2 kernel: [ 521.037308] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:35 BXT-2 kernel: [ 521.037349] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:35 BXT-2 kernel: [ 521.037390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:35 BXT-2 kernel: [ 521.037432] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:35 BXT-2 kernel: [ 521.037498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:35 BXT-2 kernel: [ 521.037550] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:35 BXT-2 kernel: [ 521.037592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:35 BXT-2 kernel: [ 521.037725] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:35 BXT-2 kernel: [ 521.037761] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:35 BXT-2 kernel: [ 521.038049] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:35 BXT-2 kernel: [ 521.038103] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:35 BXT-2 kernel: [ 521.038142] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:35 BXT-2 kernel: [ 521.038197] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:35 BXT-2 kernel: [ 521.038886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:35 BXT-2 kernel: [ 521.039209] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:35 BXT-2 kernel: [ 521.039252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:35 BXT-2 kernel: [ 521.039294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:35 BXT-2 kernel: [ 521.039335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:35 BXT-2 kernel: [ 521.039377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:35 BXT-2 kernel: [ 521.039419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:35 BXT-2 kernel: [ 521.039530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:35 BXT-2 kernel: [ 521.039572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:35 BXT-2 kernel: [ 521.039613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:35 BXT-2 kernel: [ 521.039654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:35 BXT-2 kernel: [ 521.039700] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:35 BXT-2 kernel: [ 521.039744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:35 BXT-2 kernel: [ 521.039817] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:35 BXT-2 kernel: [ 521.039858] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:35 BXT-2 kernel: [ 521.041293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:35 BXT-2 kernel: [ 521.041334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:35 BXT-2 kernel: [ 521.041377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:35 BXT-2 kernel: [ 521.042159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:35 BXT-2 kernel: [ 521.042200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:35 BXT-2 kernel: [ 521.042919] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:35 BXT-2 kernel: [ 521.042960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:35 BXT-2 kernel: [ 521.043989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:35 BXT-2 kernel: [ 521.046066] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:35 BXT-2 kernel: [ 521.047196] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:35 BXT-2 kernel: [ 521.064041] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:35 BXT-2 kernel: [ 521.064092] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:35 BXT-2 kernel: [ 521.064267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:35 BXT-2 kernel: [ 521.064658] Console: switching to colour frame buffer device 240x67 >May 24 03:30:35 BXT-2 kernel: [ 521.257718] Console: switching to colour dummy device 80x25 >May 24 03:30:35 BXT-2 kernel: [ 521.285000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:35 BXT-2 kernel: [ 521.285062] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:35 BXT-2 kernel: [ 521.285078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:35 BXT-2 kernel: [ 521.285376] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:35 BXT-2 kernel: [ 521.285422] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:35 BXT-2 kernel: [ 521.286247] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:35 BXT-2 kernel: [ 521.287263] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:35 BXT-2 kernel: [ 521.287308] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:35 BXT-2 kernel: [ 521.287350] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:35 BXT-2 kernel: [ 521.287392] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:35 BXT-2 kernel: [ 521.287960] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:35 BXT-2 kernel: [ 521.288006] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:35 BXT-2 kernel: [ 521.292968] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:35 BXT-2 kernel: [ 521.293031] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:35 BXT-2 kernel: [ 521.293038] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293043] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293048] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293053] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293059] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293064] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293069] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:35 BXT-2 kernel: [ 521.293074] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293079] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:35 BXT-2 kernel: [ 521.293084] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:35 BXT-2 kernel: [ 521.293089] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:35 BXT-2 kernel: [ 521.293094] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:35 BXT-2 kernel: [ 521.294793] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:36 BXT-2 kernel: [ 521.387176] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:36 BXT-2 kernel: [ 522.248144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:36 BXT-2 kernel: [ 522.248299] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:36 BXT-2 kernel: [ 522.265941] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:36 BXT-2 kernel: [ 522.266053] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:36 BXT-2 kernel: [ 522.266140] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:36 BXT-2 kernel: [ 522.266506] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:36 BXT-2 kernel: [ 522.266551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:36 BXT-2 kernel: [ 522.266594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:36 BXT-2 kernel: [ 522.266637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:36 BXT-2 kernel: [ 522.266680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:36 BXT-2 kernel: [ 522.266722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:36 BXT-2 kernel: [ 522.266769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:36 BXT-2 kernel: [ 522.266812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:36 BXT-2 kernel: [ 522.266854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:36 BXT-2 kernel: [ 522.266898] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:36 BXT-2 kernel: [ 522.266947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:36 BXT-2 kernel: [ 522.266992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:36 BXT-2 kernel: [ 522.267037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:36 BXT-2 kernel: [ 522.267099] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:36 BXT-2 kernel: [ 522.267142] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:36 BXT-2 kernel: [ 522.267195] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:36 BXT-2 kernel: [ 522.267255] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:36 BXT-2 kernel: [ 522.267308] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:36 BXT-2 kernel: [ 522.267351] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:36 BXT-2 kernel: [ 522.267390] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:36 BXT-2 kernel: [ 522.267978] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:36 BXT-2 kernel: [ 522.294549] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:36 BXT-2 kernel: [ 522.294593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:36 BXT-2 kernel: [ 522.294637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:36 BXT-2 kernel: [ 522.294680] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:36 BXT-2 kernel: [ 522.294721] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:36 BXT-2 kernel: [ 522.294764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:36 BXT-2 kernel: [ 522.294806] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:36 BXT-2 kernel: [ 522.294848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:36 BXT-2 kernel: [ 522.294890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:36 BXT-2 kernel: [ 522.294931] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:36 BXT-2 kernel: [ 522.294972] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:36 BXT-2 kernel: [ 522.294979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:36 BXT-2 kernel: [ 522.295020] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:36 BXT-2 kernel: [ 522.295024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:36 BXT-2 kernel: [ 522.295066] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:36 BXT-2 kernel: [ 522.295108] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:36 BXT-2 kernel: [ 522.295150] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:36 BXT-2 kernel: [ 522.295191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:36 BXT-2 kernel: [ 522.295232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:36 BXT-2 kernel: [ 522.295276] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:36 BXT-2 kernel: [ 522.295317] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:36 BXT-2 kernel: [ 522.295359] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:36 BXT-2 kernel: [ 522.295400] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:36 BXT-2 kernel: [ 522.295462] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:36 BXT-2 kernel: [ 522.295503] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:36 BXT-2 kernel: [ 522.295547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:36 BXT-2 kernel: [ 522.295598] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:36 BXT-2 kernel: [ 522.295641] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:36 BXT-2 kernel: [ 522.295803] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:36 BXT-2 kernel: [ 522.295840] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:36 BXT-2 kernel: [ 522.296128] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:36 BXT-2 kernel: [ 522.296183] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:36 BXT-2 kernel: [ 522.296222] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:36 BXT-2 kernel: [ 522.296277] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:36 BXT-2 kernel: [ 522.296543] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:36 BXT-2 kernel: [ 522.296864] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:36 BXT-2 kernel: [ 522.296907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:36 BXT-2 kernel: [ 522.296949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:36 BXT-2 kernel: [ 522.296991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:36 BXT-2 kernel: [ 522.297032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:36 BXT-2 kernel: [ 522.297074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:36 BXT-2 kernel: [ 522.297116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:36 BXT-2 kernel: [ 522.297157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:36 BXT-2 kernel: [ 522.297199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:36 BXT-2 kernel: [ 522.297241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:36 BXT-2 kernel: [ 522.297286] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:36 BXT-2 kernel: [ 522.297330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:36 BXT-2 kernel: [ 522.297403] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:36 BXT-2 kernel: [ 522.297493] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:36 BXT-2 kernel: [ 522.298953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:36 BXT-2 kernel: [ 522.298994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:36 BXT-2 kernel: [ 522.299038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:36 BXT-2 kernel: [ 522.299814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:36 BXT-2 kernel: [ 522.299854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:36 BXT-2 kernel: [ 522.300593] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:36 BXT-2 kernel: [ 522.300635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:36 BXT-2 kernel: [ 522.301700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:36 BXT-2 kernel: [ 522.303803] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:36 BXT-2 kernel: [ 522.305028] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:36 BXT-2 kernel: [ 522.321903] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:36 BXT-2 kernel: [ 522.321957] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:36 BXT-2 kernel: [ 522.322135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:36 BXT-2 kernel: [ 522.322559] Console: switching to colour frame buffer device 240x67 >May 24 03:30:37 BXT-2 kernel: [ 522.545102] Console: switching to colour dummy device 80x25 >May 24 03:30:37 BXT-2 kernel: [ 522.577991] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:37 BXT-2 kernel: [ 522.578050] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:37 BXT-2 kernel: [ 522.578066] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:37 BXT-2 kernel: [ 522.578394] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:37 BXT-2 kernel: [ 522.578489] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:37 BXT-2 kernel: [ 522.579186] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:37 BXT-2 kernel: [ 522.580101] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:37 BXT-2 kernel: [ 522.580147] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:37 BXT-2 kernel: [ 522.580189] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:37 BXT-2 kernel: [ 522.580231] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:37 BXT-2 kernel: [ 522.580796] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:37 BXT-2 kernel: [ 522.580840] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:37 BXT-2 kernel: [ 522.589341] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:37 BXT-2 kernel: [ 522.589844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:37 BXT-2 kernel: [ 522.589854] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589859] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589864] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589869] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589874] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589879] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589884] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:37 BXT-2 kernel: [ 522.589889] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589894] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:37 BXT-2 kernel: [ 522.589899] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:37 BXT-2 kernel: [ 522.589904] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:37 BXT-2 kernel: [ 522.589909] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:37 BXT-2 kernel: [ 522.591369] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:37 BXT-2 kernel: [ 522.682528] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:38 BXT-2 kernel: [ 523.539903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:38 BXT-2 kernel: [ 523.540086] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:38 BXT-2 kernel: [ 523.555846] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:38 BXT-2 kernel: [ 523.555958] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:38 BXT-2 kernel: [ 523.556044] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:38 BXT-2 kernel: [ 523.556362] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:38 BXT-2 kernel: [ 523.556406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:38 BXT-2 kernel: [ 523.556510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:38 BXT-2 kernel: [ 523.556560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:38 BXT-2 kernel: [ 523.556605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:38 BXT-2 kernel: [ 523.556651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:38 BXT-2 kernel: [ 523.556700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:38 BXT-2 kernel: [ 523.556743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:38 BXT-2 kernel: [ 523.556789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:38 BXT-2 kernel: [ 523.556833] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:38 BXT-2 kernel: [ 523.556881] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:38 BXT-2 kernel: [ 523.556929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:38 BXT-2 kernel: [ 523.556974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:38 BXT-2 kernel: [ 523.557035] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:38 BXT-2 kernel: [ 523.557078] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:38 BXT-2 kernel: [ 523.557132] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:38 BXT-2 kernel: [ 523.557194] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:38 BXT-2 kernel: [ 523.557246] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:38 BXT-2 kernel: [ 523.557290] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:38 BXT-2 kernel: [ 523.557329] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:38 BXT-2 kernel: [ 523.557922] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:38 BXT-2 kernel: [ 523.583516] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:38 BXT-2 kernel: [ 523.583560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:38 BXT-2 kernel: [ 523.583603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:38 BXT-2 kernel: [ 523.583646] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:38 BXT-2 kernel: [ 523.583688] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:38 BXT-2 kernel: [ 523.583731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:38 BXT-2 kernel: [ 523.583775] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:38 BXT-2 kernel: [ 523.583817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:38 BXT-2 kernel: [ 523.583859] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:38 BXT-2 kernel: [ 523.583901] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:38 BXT-2 kernel: [ 523.583941] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:38 BXT-2 kernel: [ 523.583949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.583990] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:38 BXT-2 kernel: [ 523.583994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.584036] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.584077] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:38 BXT-2 kernel: [ 523.584119] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:38 BXT-2 kernel: [ 523.584160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:38 BXT-2 kernel: [ 523.584201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:38 BXT-2 kernel: [ 523.584245] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:38 BXT-2 kernel: [ 523.584286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:38 BXT-2 kernel: [ 523.584328] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:38 BXT-2 kernel: [ 523.584370] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:38 BXT-2 kernel: [ 523.584411] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:38 BXT-2 kernel: [ 523.584480] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:38 BXT-2 kernel: [ 523.584527] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:38 BXT-2 kernel: [ 523.584580] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:38 BXT-2 kernel: [ 523.584622] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:38 BXT-2 kernel: [ 523.584760] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:38 BXT-2 kernel: [ 523.584796] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:38 BXT-2 kernel: [ 523.585087] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:38 BXT-2 kernel: [ 523.585142] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:38 BXT-2 kernel: [ 523.585182] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:38 BXT-2 kernel: [ 523.585239] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:38 BXT-2 kernel: [ 523.586758] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:38 BXT-2 kernel: [ 523.587088] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:38 BXT-2 kernel: [ 523.587131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:38 BXT-2 kernel: [ 523.587173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:38 BXT-2 kernel: [ 523.587214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:38 BXT-2 kernel: [ 523.587256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:38 BXT-2 kernel: [ 523.587298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:38 BXT-2 kernel: [ 523.587340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:38 BXT-2 kernel: [ 523.587381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:38 BXT-2 kernel: [ 523.587423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:38 BXT-2 kernel: [ 523.587511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:38 BXT-2 kernel: [ 523.587558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:38 BXT-2 kernel: [ 523.587602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:38 BXT-2 kernel: [ 523.587676] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:38 BXT-2 kernel: [ 523.587718] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:38 BXT-2 kernel: [ 523.589163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:38 BXT-2 kernel: [ 523.589204] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:38 BXT-2 kernel: [ 523.589247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:38 BXT-2 kernel: [ 523.590013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:38 BXT-2 kernel: [ 523.590054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:38 BXT-2 kernel: [ 523.590777] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:38 BXT-2 kernel: [ 523.590819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:38 BXT-2 kernel: [ 523.591873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:38 BXT-2 kernel: [ 523.593951] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:38 BXT-2 kernel: [ 523.595124] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:38 BXT-2 kernel: [ 523.611991] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:38 BXT-2 kernel: [ 523.612042] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:38 BXT-2 kernel: [ 523.612218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:38 BXT-2 kernel: [ 523.612616] Console: switching to colour frame buffer device 240x67 >May 24 03:30:38 BXT-2 kernel: [ 523.807575] Console: switching to colour dummy device 80x25 >May 24 03:30:38 BXT-2 kernel: [ 523.837578] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:38 BXT-2 kernel: [ 523.837640] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:38 BXT-2 kernel: [ 523.837655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:38 BXT-2 kernel: [ 523.837959] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:38 BXT-2 kernel: [ 523.838006] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:38 BXT-2 kernel: [ 523.838672] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:38 BXT-2 kernel: [ 523.839567] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:38 BXT-2 kernel: [ 523.839615] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:38 BXT-2 kernel: [ 523.839657] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:38 BXT-2 kernel: [ 523.839699] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:38 BXT-2 kernel: [ 523.840199] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:38 BXT-2 kernel: [ 523.840242] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:38 BXT-2 kernel: [ 523.845163] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:38 BXT-2 kernel: [ 523.845228] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:38 BXT-2 kernel: [ 523.845235] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845240] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845245] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845250] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845255] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845260] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845265] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:38 BXT-2 kernel: [ 523.845270] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845275] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:38 BXT-2 kernel: [ 523.845280] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:38 BXT-2 kernel: [ 523.845285] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:38 BXT-2 kernel: [ 523.845290] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:38 BXT-2 kernel: [ 523.846333] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:38 BXT-2 kernel: [ 523.937230] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:39 BXT-2 kernel: [ 524.796507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:39 BXT-2 kernel: [ 524.796670] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:39 BXT-2 kernel: [ 524.812721] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:39 BXT-2 kernel: [ 524.812835] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:39 BXT-2 kernel: [ 524.812924] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:39 BXT-2 kernel: [ 524.813249] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:39 BXT-2 kernel: [ 524.813293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:39 BXT-2 kernel: [ 524.813336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:39 BXT-2 kernel: [ 524.813379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:39 BXT-2 kernel: [ 524.813421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:39 BXT-2 kernel: [ 524.813513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:39 BXT-2 kernel: [ 524.813562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:39 BXT-2 kernel: [ 524.813604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:39 BXT-2 kernel: [ 524.813647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:39 BXT-2 kernel: [ 524.813690] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:39 BXT-2 kernel: [ 524.813737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:39 BXT-2 kernel: [ 524.813782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:39 BXT-2 kernel: [ 524.813827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:39 BXT-2 kernel: [ 524.813886] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:39 BXT-2 kernel: [ 524.813929] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:39 BXT-2 kernel: [ 524.813982] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:39 BXT-2 kernel: [ 524.814045] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:39 BXT-2 kernel: [ 524.814097] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:39 BXT-2 kernel: [ 524.814140] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:39 BXT-2 kernel: [ 524.814179] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:39 BXT-2 kernel: [ 524.814814] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:39 BXT-2 kernel: [ 524.845396] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:39 BXT-2 kernel: [ 524.845502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:39 BXT-2 kernel: [ 524.845546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:39 BXT-2 kernel: [ 524.845589] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:39 BXT-2 kernel: [ 524.845630] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:39 BXT-2 kernel: [ 524.845673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:39 BXT-2 kernel: [ 524.845715] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:39 BXT-2 kernel: [ 524.845757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:39 BXT-2 kernel: [ 524.845799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:39 BXT-2 kernel: [ 524.845840] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:39 BXT-2 kernel: [ 524.845881] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:39 BXT-2 kernel: [ 524.845889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:39 BXT-2 kernel: [ 524.845929] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:39 BXT-2 kernel: [ 524.845934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:39 BXT-2 kernel: [ 524.845976] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:39 BXT-2 kernel: [ 524.846017] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:39 BXT-2 kernel: [ 524.846059] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:39 BXT-2 kernel: [ 524.846100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:39 BXT-2 kernel: [ 524.846141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:39 BXT-2 kernel: [ 524.846184] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:39 BXT-2 kernel: [ 524.846225] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:39 BXT-2 kernel: [ 524.846267] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:39 BXT-2 kernel: [ 524.846308] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:39 BXT-2 kernel: [ 524.846349] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:39 BXT-2 kernel: [ 524.846390] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:39 BXT-2 kernel: [ 524.846455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:39 BXT-2 kernel: [ 524.846505] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:39 BXT-2 kernel: [ 524.846548] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:39 BXT-2 kernel: [ 524.846673] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:39 BXT-2 kernel: [ 524.846709] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:39 BXT-2 kernel: [ 524.847002] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:39 BXT-2 kernel: [ 524.847057] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:39 BXT-2 kernel: [ 524.847096] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:39 BXT-2 kernel: [ 524.847151] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:39 BXT-2 kernel: [ 524.847489] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:39 BXT-2 kernel: [ 524.847822] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:39 BXT-2 kernel: [ 524.847865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:39 BXT-2 kernel: [ 524.847907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:39 BXT-2 kernel: [ 524.847949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:39 BXT-2 kernel: [ 524.847990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:39 BXT-2 kernel: [ 524.848032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:39 BXT-2 kernel: [ 524.848073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:39 BXT-2 kernel: [ 524.848115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:39 BXT-2 kernel: [ 524.848156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:39 BXT-2 kernel: [ 524.848198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:39 BXT-2 kernel: [ 524.848244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:39 BXT-2 kernel: [ 524.848288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:39 BXT-2 kernel: [ 524.848362] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:39 BXT-2 kernel: [ 524.848403] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:39 BXT-2 kernel: [ 524.849969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:39 BXT-2 kernel: [ 524.850011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:39 BXT-2 kernel: [ 524.850055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:39 BXT-2 kernel: [ 524.850848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:39 BXT-2 kernel: [ 524.850890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:39 BXT-2 kernel: [ 524.851644] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:39 BXT-2 kernel: [ 524.851688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:39 BXT-2 kernel: [ 524.852743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:39 BXT-2 kernel: [ 524.854531] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:39 BXT-2 kernel: [ 524.855716] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:39 BXT-2 kernel: [ 524.872629] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:39 BXT-2 kernel: [ 524.872683] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:39 BXT-2 kernel: [ 524.872860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:39 BXT-2 kernel: [ 524.873208] Console: switching to colour frame buffer device 240x67 >May 24 03:30:39 BXT-2 kernel: [ 525.070006] Console: switching to colour dummy device 80x25 >May 24 03:30:39 BXT-2 kernel: [ 525.098907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:39 BXT-2 kernel: [ 525.098966] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:39 BXT-2 kernel: [ 525.098981] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:39 BXT-2 kernel: [ 525.099312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:39 BXT-2 kernel: [ 525.099359] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:39 BXT-2 kernel: [ 525.100106] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:39 BXT-2 kernel: [ 525.101093] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:39 BXT-2 kernel: [ 525.101139] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:39 BXT-2 kernel: [ 525.101181] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:39 BXT-2 kernel: [ 525.101223] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:39 BXT-2 kernel: [ 525.101952] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:39 BXT-2 kernel: [ 525.101996] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:39 BXT-2 kernel: [ 525.106934] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:39 BXT-2 kernel: [ 525.107001] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:39 BXT-2 kernel: [ 525.107008] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107013] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107018] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107023] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107028] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107033] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107038] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:39 BXT-2 kernel: [ 525.107043] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107049] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:39 BXT-2 kernel: [ 525.107053] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:39 BXT-2 kernel: [ 525.107058] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:39 BXT-2 kernel: [ 525.107063] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:39 BXT-2 kernel: [ 525.108713] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:39 BXT-2 kernel: [ 525.198576] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:39 BXT-2 kernel: [ 525.198869] [drm:drm_mode_addfb2] [FB:81] >May 24 03:30:40 BXT-2 kernel: [ 526.057281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:40 BXT-2 kernel: [ 526.057498] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:40 BXT-2 kernel: [ 526.073796] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:40 BXT-2 kernel: [ 526.073913] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:40 BXT-2 kernel: [ 526.074002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:40 BXT-2 kernel: [ 526.074326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:40 BXT-2 kernel: [ 526.074371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:40 BXT-2 kernel: [ 526.074414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:40 BXT-2 kernel: [ 526.074542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:40 BXT-2 kernel: [ 526.074586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:40 BXT-2 kernel: [ 526.074631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:40 BXT-2 kernel: [ 526.074680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:40 BXT-2 kernel: [ 526.074723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:40 BXT-2 kernel: [ 526.074767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:40 BXT-2 kernel: [ 526.074810] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:40 BXT-2 kernel: [ 526.074858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:40 BXT-2 kernel: [ 526.074903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:40 BXT-2 kernel: [ 526.074949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:40 BXT-2 kernel: [ 526.075010] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:40 BXT-2 kernel: [ 526.075053] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:40 BXT-2 kernel: [ 526.075106] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:40 BXT-2 kernel: [ 526.075169] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:40 BXT-2 kernel: [ 526.075220] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:40 BXT-2 kernel: [ 526.075263] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:40 BXT-2 kernel: [ 526.075302] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:40 BXT-2 kernel: [ 526.075886] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:40 BXT-2 kernel: [ 526.104553] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:40 BXT-2 kernel: [ 526.104598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:40 BXT-2 kernel: [ 526.104642] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:40 BXT-2 kernel: [ 526.104685] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:40 BXT-2 kernel: [ 526.104726] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:40 BXT-2 kernel: [ 526.104770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:40 BXT-2 kernel: [ 526.104813] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:40 BXT-2 kernel: [ 526.104855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:40 BXT-2 kernel: [ 526.104897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:40 BXT-2 kernel: [ 526.104938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:40 BXT-2 kernel: [ 526.104979] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:40 BXT-2 kernel: [ 526.104987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:40 BXT-2 kernel: [ 526.105027] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:40 BXT-2 kernel: [ 526.105032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:40 BXT-2 kernel: [ 526.105074] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:40 BXT-2 kernel: [ 526.105115] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:40 BXT-2 kernel: [ 526.105157] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:40 BXT-2 kernel: [ 526.105198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:40 BXT-2 kernel: [ 526.105239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:40 BXT-2 kernel: [ 526.105283] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:40 BXT-2 kernel: [ 526.105323] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:40 BXT-2 kernel: [ 526.105365] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:40 BXT-2 kernel: [ 526.105406] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:40 BXT-2 kernel: [ 526.105477] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:40 BXT-2 kernel: [ 526.105518] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:40 BXT-2 kernel: [ 526.105565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:40 BXT-2 kernel: [ 526.105617] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:40 BXT-2 kernel: [ 526.105660] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:40 BXT-2 kernel: [ 526.105793] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:40 BXT-2 kernel: [ 526.105830] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:40 BXT-2 kernel: [ 526.106128] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:40 BXT-2 kernel: [ 526.106186] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:40 BXT-2 kernel: [ 526.106225] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:40 BXT-2 kernel: [ 526.106282] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:40 BXT-2 kernel: [ 526.106544] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:40 BXT-2 kernel: [ 526.106914] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:40 BXT-2 kernel: [ 526.106972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:40 BXT-2 kernel: [ 526.107025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:40 BXT-2 kernel: [ 526.107074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:40 BXT-2 kernel: [ 526.107124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:40 BXT-2 kernel: [ 526.107172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:40 BXT-2 kernel: [ 526.107221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:40 BXT-2 kernel: [ 526.107270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:40 BXT-2 kernel: [ 526.107312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:40 BXT-2 kernel: [ 526.107355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:40 BXT-2 kernel: [ 526.107405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:40 BXT-2 kernel: [ 526.107503] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:40 BXT-2 kernel: [ 526.107579] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:40 BXT-2 kernel: [ 526.107621] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:40 BXT-2 kernel: [ 526.109060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:40 BXT-2 kernel: [ 526.109102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:40 BXT-2 kernel: [ 526.109146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:40 BXT-2 kernel: [ 526.109906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:40 BXT-2 kernel: [ 526.109946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:40 BXT-2 kernel: [ 526.111006] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:40 BXT-2 kernel: [ 526.111048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:40 BXT-2 kernel: [ 526.112075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:40 BXT-2 kernel: [ 526.113460] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:40 BXT-2 kernel: [ 526.114629] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:40 BXT-2 kernel: [ 526.131534] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:40 BXT-2 kernel: [ 526.131586] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:40 BXT-2 kernel: [ 526.131761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:40 BXT-2 kernel: [ 526.132106] Console: switching to colour frame buffer device 240x67 >May 24 03:30:40 BXT-2 kernel: [ 526.330967] Console: switching to colour dummy device 80x25 >May 24 03:30:41 BXT-2 kernel: [ 526.356198] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:41 BXT-2 kernel: [ 526.356260] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:41 BXT-2 kernel: [ 526.356278] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:41 BXT-2 kernel: [ 526.356774] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:41 BXT-2 kernel: [ 526.356837] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:41 BXT-2 kernel: [ 526.357396] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:41 BXT-2 kernel: [ 526.358406] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:41 BXT-2 kernel: [ 526.358556] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:41 BXT-2 kernel: [ 526.358599] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:41 BXT-2 kernel: [ 526.358646] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:41 BXT-2 kernel: [ 526.359153] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:41 BXT-2 kernel: [ 526.359197] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:41 BXT-2 kernel: [ 526.364161] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:41 BXT-2 kernel: [ 526.364226] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:41 BXT-2 kernel: [ 526.364233] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364238] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364243] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364248] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364253] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364258] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364263] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:41 BXT-2 kernel: [ 526.364268] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364273] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:41 BXT-2 kernel: [ 526.364278] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:41 BXT-2 kernel: [ 526.364283] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:41 BXT-2 kernel: [ 526.364288] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:41 BXT-2 kernel: [ 526.365515] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:41 BXT-2 kernel: [ 526.460937] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:41 BXT-2 kernel: [ 526.461252] [drm:drm_mode_addfb2] [FB:81] >May 24 03:30:41 BXT-2 kernel: [ 527.315925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:41 BXT-2 kernel: [ 527.316108] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:41 BXT-2 kernel: [ 527.332807] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:41 BXT-2 kernel: [ 527.332918] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:41 BXT-2 kernel: [ 527.333006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:41 BXT-2 kernel: [ 527.333329] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:41 BXT-2 kernel: [ 527.333373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:41 BXT-2 kernel: [ 527.333415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:41 BXT-2 kernel: [ 527.333507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:41 BXT-2 kernel: [ 527.333557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:41 BXT-2 kernel: [ 527.333603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:41 BXT-2 kernel: [ 527.333653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:41 BXT-2 kernel: [ 527.333697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:41 BXT-2 kernel: [ 527.333744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:41 BXT-2 kernel: [ 527.333788] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:41 BXT-2 kernel: [ 527.333836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:41 BXT-2 kernel: [ 527.333881] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:41 BXT-2 kernel: [ 527.333926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:41 BXT-2 kernel: [ 527.333987] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:41 BXT-2 kernel: [ 527.334029] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:41 BXT-2 kernel: [ 527.334083] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:41 BXT-2 kernel: [ 527.334146] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:41 BXT-2 kernel: [ 527.334196] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:41 BXT-2 kernel: [ 527.334239] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:41 BXT-2 kernel: [ 527.334278] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:41 BXT-2 kernel: [ 527.334873] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:42 BXT-2 kernel: [ 527.364319] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:42 BXT-2 kernel: [ 527.364362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:42 BXT-2 kernel: [ 527.364406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:42 BXT-2 kernel: [ 527.364479] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:42 BXT-2 kernel: [ 527.364520] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:42 BXT-2 kernel: [ 527.364563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:42 BXT-2 kernel: [ 527.364607] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:42 BXT-2 kernel: [ 527.364649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:42 BXT-2 kernel: [ 527.364690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:42 BXT-2 kernel: [ 527.364731] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:42 BXT-2 kernel: [ 527.364772] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:42 BXT-2 kernel: [ 527.364779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.364820] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:42 BXT-2 kernel: [ 527.364824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.364866] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.364908] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:42 BXT-2 kernel: [ 527.364949] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:42 BXT-2 kernel: [ 527.364991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:42 BXT-2 kernel: [ 527.365032] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:42 BXT-2 kernel: [ 527.365075] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:42 BXT-2 kernel: [ 527.365116] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:42 BXT-2 kernel: [ 527.365158] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:42 BXT-2 kernel: [ 527.365199] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:42 BXT-2 kernel: [ 527.365240] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:42 BXT-2 kernel: [ 527.365281] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:42 BXT-2 kernel: [ 527.365325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:42 BXT-2 kernel: [ 527.365375] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:42 BXT-2 kernel: [ 527.365417] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:42 BXT-2 kernel: [ 527.365598] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:42 BXT-2 kernel: [ 527.365633] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:42 BXT-2 kernel: [ 527.365922] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:42 BXT-2 kernel: [ 527.365976] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:42 BXT-2 kernel: [ 527.366015] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:42 BXT-2 kernel: [ 527.366070] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:42 BXT-2 kernel: [ 527.366323] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:42 BXT-2 kernel: [ 527.366639] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:42 BXT-2 kernel: [ 527.366682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:42 BXT-2 kernel: [ 527.366723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:42 BXT-2 kernel: [ 527.366765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:42 BXT-2 kernel: [ 527.366806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:42 BXT-2 kernel: [ 527.366847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:42 BXT-2 kernel: [ 527.366888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:42 BXT-2 kernel: [ 527.366929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:42 BXT-2 kernel: [ 527.366971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:42 BXT-2 kernel: [ 527.367013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:42 BXT-2 kernel: [ 527.367058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:42 BXT-2 kernel: [ 527.367101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:42 BXT-2 kernel: [ 527.367174] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:42 BXT-2 kernel: [ 527.367215] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:42 BXT-2 kernel: [ 527.368734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:42 BXT-2 kernel: [ 527.368775] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:42 BXT-2 kernel: [ 527.368818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:42 BXT-2 kernel: [ 527.369589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:42 BXT-2 kernel: [ 527.369630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:42 BXT-2 kernel: [ 527.370358] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:42 BXT-2 kernel: [ 527.370400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:42 BXT-2 kernel: [ 527.371485] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:42 BXT-2 kernel: [ 527.373562] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:42 BXT-2 kernel: [ 527.374730] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:42 BXT-2 kernel: [ 527.391649] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:42 BXT-2 kernel: [ 527.391708] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:42 BXT-2 kernel: [ 527.391886] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:42 BXT-2 kernel: [ 527.392255] Console: switching to colour frame buffer device 240x67 >May 24 03:30:42 BXT-2 kernel: [ 527.626157] Console: switching to colour dummy device 80x25 >May 24 03:30:42 BXT-2 kernel: [ 527.646744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:42 BXT-2 kernel: [ 527.646804] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:42 BXT-2 kernel: [ 527.646820] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:42 BXT-2 kernel: [ 527.647154] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:42 BXT-2 kernel: [ 527.647203] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:42 BXT-2 kernel: [ 527.648071] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:42 BXT-2 kernel: [ 527.649168] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:42 BXT-2 kernel: [ 527.649214] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:42 BXT-2 kernel: [ 527.649256] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:42 BXT-2 kernel: [ 527.649298] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:42 BXT-2 kernel: [ 527.649852] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:42 BXT-2 kernel: [ 527.649896] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:42 BXT-2 kernel: [ 527.654732] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:42 BXT-2 kernel: [ 527.654801] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:42 BXT-2 kernel: [ 527.654808] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654813] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654818] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654823] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654828] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654833] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654838] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:42 BXT-2 kernel: [ 527.654843] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654848] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:42 BXT-2 kernel: [ 527.654853] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:42 BXT-2 kernel: [ 527.654858] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:42 BXT-2 kernel: [ 527.654863] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:42 BXT-2 kernel: [ 527.656004] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:42 BXT-2 kernel: [ 527.743466] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:43 BXT-2 kernel: [ 528.609608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:43 BXT-2 kernel: [ 528.609779] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:43 BXT-2 kernel: [ 528.626268] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:43 BXT-2 kernel: [ 528.626379] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:43 BXT-2 kernel: [ 528.626844] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:43 BXT-2 kernel: [ 528.627176] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:43 BXT-2 kernel: [ 528.627220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:43 BXT-2 kernel: [ 528.627263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:43 BXT-2 kernel: [ 528.627305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:43 BXT-2 kernel: [ 528.627348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:43 BXT-2 kernel: [ 528.627390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:43 BXT-2 kernel: [ 528.627672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:43 BXT-2 kernel: [ 528.627716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:43 BXT-2 kernel: [ 528.627760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:43 BXT-2 kernel: [ 528.627803] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:43 BXT-2 kernel: [ 528.627850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:43 BXT-2 kernel: [ 528.627896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:43 BXT-2 kernel: [ 528.627941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:43 BXT-2 kernel: [ 528.628000] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:43 BXT-2 kernel: [ 528.628044] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:43 BXT-2 kernel: [ 528.628098] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:43 BXT-2 kernel: [ 528.628160] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:43 BXT-2 kernel: [ 528.628212] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:43 BXT-2 kernel: [ 528.628256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:43 BXT-2 kernel: [ 528.628295] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:43 BXT-2 kernel: [ 528.629490] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:43 BXT-2 kernel: [ 528.662316] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:43 BXT-2 kernel: [ 528.662359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:43 BXT-2 kernel: [ 528.662402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:43 BXT-2 kernel: [ 528.662476] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:43 BXT-2 kernel: [ 528.662517] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:43 BXT-2 kernel: [ 528.662561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:43 BXT-2 kernel: [ 528.662603] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:43 BXT-2 kernel: [ 528.662644] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:43 BXT-2 kernel: [ 528.662686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:43 BXT-2 kernel: [ 528.662727] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:43 BXT-2 kernel: [ 528.662768] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:43 BXT-2 kernel: [ 528.662775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.662816] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:43 BXT-2 kernel: [ 528.662820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.662862] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.662903] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:43 BXT-2 kernel: [ 528.662945] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:43 BXT-2 kernel: [ 528.662986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:43 BXT-2 kernel: [ 528.663027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:43 BXT-2 kernel: [ 528.663071] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:43 BXT-2 kernel: [ 528.663112] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:43 BXT-2 kernel: [ 528.663153] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:43 BXT-2 kernel: [ 528.663195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:43 BXT-2 kernel: [ 528.663236] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:43 BXT-2 kernel: [ 528.663277] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:43 BXT-2 kernel: [ 528.663321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:43 BXT-2 kernel: [ 528.663372] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:43 BXT-2 kernel: [ 528.663414] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:43 BXT-2 kernel: [ 528.663624] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:43 BXT-2 kernel: [ 528.663661] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:43 BXT-2 kernel: [ 528.663949] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:43 BXT-2 kernel: [ 528.664003] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:43 BXT-2 kernel: [ 528.664044] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:43 BXT-2 kernel: [ 528.664100] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:43 BXT-2 kernel: [ 528.664380] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:43 BXT-2 kernel: [ 528.664703] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:43 BXT-2 kernel: [ 528.664746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:43 BXT-2 kernel: [ 528.664789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:43 BXT-2 kernel: [ 528.664830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:43 BXT-2 kernel: [ 528.664872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:43 BXT-2 kernel: [ 528.664913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:43 BXT-2 kernel: [ 528.664955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:43 BXT-2 kernel: [ 528.664996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:43 BXT-2 kernel: [ 528.665037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:43 BXT-2 kernel: [ 528.665079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:43 BXT-2 kernel: [ 528.665124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:43 BXT-2 kernel: [ 528.665168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:43 BXT-2 kernel: [ 528.665241] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:43 BXT-2 kernel: [ 528.665282] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:43 BXT-2 kernel: [ 528.666719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:43 BXT-2 kernel: [ 528.666760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:43 BXT-2 kernel: [ 528.666803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:43 BXT-2 kernel: [ 528.667568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:43 BXT-2 kernel: [ 528.667608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:43 BXT-2 kernel: [ 528.668326] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:43 BXT-2 kernel: [ 528.668367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:43 BXT-2 kernel: [ 528.669401] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:43 BXT-2 kernel: [ 528.671553] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:43 BXT-2 kernel: [ 528.672745] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:43 BXT-2 kernel: [ 528.689611] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:43 BXT-2 kernel: [ 528.689664] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:43 BXT-2 kernel: [ 528.689839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:43 BXT-2 kernel: [ 528.690193] Console: switching to colour frame buffer device 240x67 >May 24 03:30:43 BXT-2 kernel: [ 528.912604] Console: switching to colour dummy device 80x25 >May 24 03:30:43 BXT-2 kernel: [ 528.944019] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:43 BXT-2 kernel: [ 528.944078] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:43 BXT-2 kernel: [ 528.944094] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:43 BXT-2 kernel: [ 528.944724] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:43 BXT-2 kernel: [ 528.944785] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:43 BXT-2 kernel: [ 528.945325] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:43 BXT-2 kernel: [ 528.946439] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:43 BXT-2 kernel: [ 528.946524] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:43 BXT-2 kernel: [ 528.946567] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:43 BXT-2 kernel: [ 528.946609] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:43 BXT-2 kernel: [ 528.947095] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:43 BXT-2 kernel: [ 528.947137] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:43 BXT-2 kernel: [ 528.952045] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:43 BXT-2 kernel: [ 528.952108] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:43 BXT-2 kernel: [ 528.952115] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952120] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952125] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952130] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952135] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952140] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952145] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:43 BXT-2 kernel: [ 528.952150] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952155] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:43 BXT-2 kernel: [ 528.952160] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:43 BXT-2 kernel: [ 528.952165] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:43 BXT-2 kernel: [ 528.952170] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:43 BXT-2 kernel: [ 528.953633] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:43 BXT-2 kernel: [ 529.043112] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:44 BXT-2 kernel: [ 529.907322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:44 BXT-2 kernel: [ 529.907692] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:44 BXT-2 kernel: [ 529.923801] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:44 BXT-2 kernel: [ 529.923912] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:44 BXT-2 kernel: [ 529.923999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:44 BXT-2 kernel: [ 529.924321] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:44 BXT-2 kernel: [ 529.924365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:44 BXT-2 kernel: [ 529.924408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:44 BXT-2 kernel: [ 529.924515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:44 BXT-2 kernel: [ 529.924558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:44 BXT-2 kernel: [ 529.924601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:44 BXT-2 kernel: [ 529.924648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:44 BXT-2 kernel: [ 529.924691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:44 BXT-2 kernel: [ 529.924734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:44 BXT-2 kernel: [ 529.924777] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:44 BXT-2 kernel: [ 529.924827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:44 BXT-2 kernel: [ 529.924872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:44 BXT-2 kernel: [ 529.924919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:44 BXT-2 kernel: [ 529.924981] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:44 BXT-2 kernel: [ 529.925024] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:44 BXT-2 kernel: [ 529.925078] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:44 BXT-2 kernel: [ 529.925142] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:44 BXT-2 kernel: [ 529.925194] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:44 BXT-2 kernel: [ 529.925238] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:44 BXT-2 kernel: [ 529.925278] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:44 BXT-2 kernel: [ 529.925897] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:44 BXT-2 kernel: [ 529.949367] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:44 BXT-2 kernel: [ 529.949410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:44 BXT-2 kernel: [ 529.949484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:44 BXT-2 kernel: [ 529.949527] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:44 BXT-2 kernel: [ 529.949568] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:44 BXT-2 kernel: [ 529.949611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:44 BXT-2 kernel: [ 529.949654] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:44 BXT-2 kernel: [ 529.949696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:44 BXT-2 kernel: [ 529.949738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:44 BXT-2 kernel: [ 529.949779] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:44 BXT-2 kernel: [ 529.949819] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:44 BXT-2 kernel: [ 529.949827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:44 BXT-2 kernel: [ 529.949867] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:44 BXT-2 kernel: [ 529.949872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:44 BXT-2 kernel: [ 529.949914] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:44 BXT-2 kernel: [ 529.949955] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:44 BXT-2 kernel: [ 529.949997] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:44 BXT-2 kernel: [ 529.950038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:44 BXT-2 kernel: [ 529.950079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:44 BXT-2 kernel: [ 529.950122] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:44 BXT-2 kernel: [ 529.950163] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:44 BXT-2 kernel: [ 529.950205] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:44 BXT-2 kernel: [ 529.950246] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:44 BXT-2 kernel: [ 529.950287] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:44 BXT-2 kernel: [ 529.950328] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:44 BXT-2 kernel: [ 529.950372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:44 BXT-2 kernel: [ 529.950422] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:44 BXT-2 kernel: [ 529.950480] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:44 BXT-2 kernel: [ 529.950603] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:44 BXT-2 kernel: [ 529.950639] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:44 BXT-2 kernel: [ 529.950926] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:44 BXT-2 kernel: [ 529.950981] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:44 BXT-2 kernel: [ 529.951020] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:44 BXT-2 kernel: [ 529.951075] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:44 BXT-2 kernel: [ 529.951365] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:44 BXT-2 kernel: [ 529.951686] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:44 BXT-2 kernel: [ 529.951729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:44 BXT-2 kernel: [ 529.951771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:44 BXT-2 kernel: [ 529.951812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:44 BXT-2 kernel: [ 529.951854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:44 BXT-2 kernel: [ 529.951896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:44 BXT-2 kernel: [ 529.951938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:44 BXT-2 kernel: [ 529.951979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:44 BXT-2 kernel: [ 529.952020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:44 BXT-2 kernel: [ 529.952062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:44 BXT-2 kernel: [ 529.952107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:44 BXT-2 kernel: [ 529.952150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:44 BXT-2 kernel: [ 529.952223] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:44 BXT-2 kernel: [ 529.952264] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:44 BXT-2 kernel: [ 529.953824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:44 BXT-2 kernel: [ 529.953864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:44 BXT-2 kernel: [ 529.953908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:44 BXT-2 kernel: [ 529.954667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:44 BXT-2 kernel: [ 529.954707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:44 BXT-2 kernel: [ 529.955425] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:44 BXT-2 kernel: [ 529.955651] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:44 BXT-2 kernel: [ 529.956695] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:44 BXT-2 kernel: [ 529.958770] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:44 BXT-2 kernel: [ 529.959920] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:44 BXT-2 kernel: [ 529.976773] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:44 BXT-2 kernel: [ 529.976825] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:44 BXT-2 kernel: [ 529.977000] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:44 BXT-2 kernel: [ 529.977351] Console: switching to colour frame buffer device 240x67 >May 24 03:30:44 BXT-2 kernel: [ 530.188471] Console: switching to colour dummy device 80x25 >May 24 03:30:44 BXT-2 kernel: [ 530.220046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:44 BXT-2 kernel: [ 530.220105] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:44 BXT-2 kernel: [ 530.220120] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:44 BXT-2 kernel: [ 530.220469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:44 BXT-2 kernel: [ 530.220521] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:44 BXT-2 kernel: [ 530.221256] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:44 BXT-2 kernel: [ 530.222260] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:44 BXT-2 kernel: [ 530.222306] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:44 BXT-2 kernel: [ 530.222349] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:44 BXT-2 kernel: [ 530.222391] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:44 BXT-2 kernel: [ 530.223124] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:44 BXT-2 kernel: [ 530.223167] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:44 BXT-2 kernel: [ 530.227938] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:44 BXT-2 kernel: [ 530.228002] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:44 BXT-2 kernel: [ 530.228009] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228014] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228019] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228024] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228029] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228034] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228039] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:44 BXT-2 kernel: [ 530.228044] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228050] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:44 BXT-2 kernel: [ 530.228054] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:44 BXT-2 kernel: [ 530.228059] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:44 BXT-2 kernel: [ 530.228064] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:44 BXT-2 kernel: [ 530.229127] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:44 BXT-2 kernel: [ 530.319157] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:45 BXT-2 kernel: [ 531.177451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:45 BXT-2 kernel: [ 531.177650] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:45 BXT-2 kernel: [ 531.194119] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:45 BXT-2 kernel: [ 531.194230] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:45 BXT-2 kernel: [ 531.194316] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:45 BXT-2 kernel: [ 531.194646] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:45 BXT-2 kernel: [ 531.194691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:45 BXT-2 kernel: [ 531.194735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:45 BXT-2 kernel: [ 531.194778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:45 BXT-2 kernel: [ 531.194822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:45 BXT-2 kernel: [ 531.194866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:45 BXT-2 kernel: [ 531.194914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:45 BXT-2 kernel: [ 531.194957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:45 BXT-2 kernel: [ 531.195000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:45 BXT-2 kernel: [ 531.195043] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:45 BXT-2 kernel: [ 531.195090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:45 BXT-2 kernel: [ 531.195136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:45 BXT-2 kernel: [ 531.195180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:45 BXT-2 kernel: [ 531.195239] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:45 BXT-2 kernel: [ 531.195282] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:45 BXT-2 kernel: [ 531.195335] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:45 BXT-2 kernel: [ 531.195397] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:45 BXT-2 kernel: [ 531.195492] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:45 BXT-2 kernel: [ 531.195536] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:45 BXT-2 kernel: [ 531.195574] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:45 BXT-2 kernel: [ 531.196129] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:45 BXT-2 kernel: [ 531.222331] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:45 BXT-2 kernel: [ 531.222374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:45 BXT-2 kernel: [ 531.222417] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:45 BXT-2 kernel: [ 531.222527] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:45 BXT-2 kernel: [ 531.222568] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:45 BXT-2 kernel: [ 531.222611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:45 BXT-2 kernel: [ 531.222653] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:45 BXT-2 kernel: [ 531.222695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:45 BXT-2 kernel: [ 531.222737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:45 BXT-2 kernel: [ 531.222778] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:45 BXT-2 kernel: [ 531.222819] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:45 BXT-2 kernel: [ 531.222826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:45 BXT-2 kernel: [ 531.222867] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:45 BXT-2 kernel: [ 531.222871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:45 BXT-2 kernel: [ 531.222913] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:45 BXT-2 kernel: [ 531.222954] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:45 BXT-2 kernel: [ 531.222996] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:45 BXT-2 kernel: [ 531.223037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:45 BXT-2 kernel: [ 531.223078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:45 BXT-2 kernel: [ 531.223122] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:45 BXT-2 kernel: [ 531.223162] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:45 BXT-2 kernel: [ 531.223204] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:45 BXT-2 kernel: [ 531.223245] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:45 BXT-2 kernel: [ 531.223286] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:45 BXT-2 kernel: [ 531.223328] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:45 BXT-2 kernel: [ 531.223371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:45 BXT-2 kernel: [ 531.223422] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:45 BXT-2 kernel: [ 531.223486] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:45 BXT-2 kernel: [ 531.223610] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:45 BXT-2 kernel: [ 531.223646] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:45 BXT-2 kernel: [ 531.223934] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:45 BXT-2 kernel: [ 531.223988] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:45 BXT-2 kernel: [ 531.224027] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:45 BXT-2 kernel: [ 531.224082] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:45 BXT-2 kernel: [ 531.224320] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:45 BXT-2 kernel: [ 531.224642] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:45 BXT-2 kernel: [ 531.224684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:45 BXT-2 kernel: [ 531.224726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:45 BXT-2 kernel: [ 531.224767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:45 BXT-2 kernel: [ 531.224809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:45 BXT-2 kernel: [ 531.224851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:45 BXT-2 kernel: [ 531.224892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:45 BXT-2 kernel: [ 531.224933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:45 BXT-2 kernel: [ 531.224976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:45 BXT-2 kernel: [ 531.225018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:45 BXT-2 kernel: [ 531.225063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:45 BXT-2 kernel: [ 531.225106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:45 BXT-2 kernel: [ 531.225178] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:45 BXT-2 kernel: [ 531.225220] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:45 BXT-2 kernel: [ 531.226691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:45 BXT-2 kernel: [ 531.226732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:45 BXT-2 kernel: [ 531.226775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:45 BXT-2 kernel: [ 531.227534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:45 BXT-2 kernel: [ 531.227575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:45 BXT-2 kernel: [ 531.228291] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:45 BXT-2 kernel: [ 531.228332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:45 BXT-2 kernel: [ 531.229363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:45 BXT-2 kernel: [ 531.231466] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:45 BXT-2 kernel: [ 531.232620] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:45 BXT-2 kernel: [ 531.249495] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:45 BXT-2 kernel: [ 531.249546] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:45 BXT-2 kernel: [ 531.249720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:45 BXT-2 kernel: [ 531.250061] Console: switching to colour frame buffer device 240x67 >May 24 03:30:46 BXT-2 kernel: [ 531.439472] Console: switching to colour dummy device 80x25 >May 24 03:30:46 BXT-2 kernel: [ 531.465033] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:46 BXT-2 kernel: [ 531.465094] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:46 BXT-2 kernel: [ 531.465109] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:46 BXT-2 kernel: [ 531.465132] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:46 BXT-2 kernel: [ 531.465177] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:46 BXT-2 kernel: [ 531.465815] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:46 BXT-2 kernel: [ 531.466690] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:46 BXT-2 kernel: [ 531.466736] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:46 BXT-2 kernel: [ 531.466779] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:46 BXT-2 kernel: [ 531.466821] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:46 BXT-2 kernel: [ 531.467299] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:46 BXT-2 kernel: [ 531.467342] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:46 BXT-2 kernel: [ 531.472382] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:46 BXT-2 kernel: [ 531.472598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:46 BXT-2 kernel: [ 531.472607] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472612] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472617] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472623] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472628] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472633] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472638] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:46 BXT-2 kernel: [ 531.472644] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472649] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.472654] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:46 BXT-2 kernel: [ 531.472659] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:46 BXT-2 kernel: [ 531.472664] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:46 BXT-2 kernel: [ 531.474228] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:46 BXT-2 kernel: [ 531.474329] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:46 BXT-2 kernel: [ 531.596317] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:46 BXT-2 kernel: [ 531.596662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:46 BXT-2 kernel: [ 531.596837] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:46 BXT-2 kernel: [ 531.601209] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:46 BXT-2 kernel: [ 531.601322] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:46 BXT-2 kernel: [ 531.601410] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:46 BXT-2 kernel: [ 531.602052] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:46 BXT-2 kernel: [ 531.602097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:46 BXT-2 kernel: [ 531.602141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:46 BXT-2 kernel: [ 531.602184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:46 BXT-2 kernel: [ 531.602226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:46 BXT-2 kernel: [ 531.602270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:46 BXT-2 kernel: [ 531.602319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:46 BXT-2 kernel: [ 531.602362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:46 BXT-2 kernel: [ 531.602405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:46 BXT-2 kernel: [ 531.602761] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:46 BXT-2 kernel: [ 531.602813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:46 BXT-2 kernel: [ 531.602860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:46 BXT-2 kernel: [ 531.602906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:46 BXT-2 kernel: [ 531.602967] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:46 BXT-2 kernel: [ 531.603010] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:46 BXT-2 kernel: [ 531.603064] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:46 BXT-2 kernel: [ 531.603127] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:46 BXT-2 kernel: [ 531.603180] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:46 BXT-2 kernel: [ 531.603223] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:46 BXT-2 kernel: [ 531.603262] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:46 BXT-2 kernel: [ 531.604435] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:46 BXT-2 kernel: [ 531.604575] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:46 BXT-2 kernel: [ 531.605045] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:46 BXT-2 kernel: [ 531.605950] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:46 BXT-2 kernel: [ 531.606011] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:46 BXT-2 kernel: [ 531.606155] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:46 BXT-2 kernel: [ 531.606207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:46 BXT-2 kernel: [ 531.606255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:46 BXT-2 kernel: [ 531.606300] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:46 BXT-2 kernel: [ 531.606344] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:46 BXT-2 kernel: [ 531.606391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:46 BXT-2 kernel: [ 531.606833] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:46 BXT-2 kernel: [ 531.606879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:46 BXT-2 kernel: [ 531.606922] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:46 BXT-2 kernel: [ 531.606965] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:46 BXT-2 kernel: [ 531.607007] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:46 BXT-2 kernel: [ 531.607017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.607059] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:46 BXT-2 kernel: [ 531.607066] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.607109] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:46 BXT-2 kernel: [ 531.607154] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:46 BXT-2 kernel: [ 531.607197] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:46 BXT-2 kernel: [ 531.607240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:46 BXT-2 kernel: [ 531.607283] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:46 BXT-2 kernel: [ 531.607330] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:46 BXT-2 kernel: [ 531.607373] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:46 BXT-2 kernel: [ 531.607416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:46 BXT-2 kernel: [ 531.607737] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:46 BXT-2 kernel: [ 531.607780] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:46 BXT-2 kernel: [ 531.607823] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:46 BXT-2 kernel: [ 531.607891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:46 BXT-2 kernel: [ 531.607944] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:46 BXT-2 kernel: [ 531.607988] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:46 BXT-2 kernel: [ 531.608958] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:46 BXT-2 kernel: [ 531.608999] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:46 BXT-2 kernel: [ 531.609298] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:46 BXT-2 kernel: [ 531.609357] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:46 BXT-2 kernel: [ 531.609399] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:46 BXT-2 kernel: [ 531.609872] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:46 BXT-2 kernel: [ 531.610148] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:46 BXT-2 kernel: [ 531.610774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:46 BXT-2 kernel: [ 531.610823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:46 BXT-2 kernel: [ 531.610867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:46 BXT-2 kernel: [ 531.610910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:46 BXT-2 kernel: [ 531.610952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:46 BXT-2 kernel: [ 531.610996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:46 BXT-2 kernel: [ 531.611038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:46 BXT-2 kernel: [ 531.611081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:46 BXT-2 kernel: [ 531.611124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:46 BXT-2 kernel: [ 531.611167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:46 BXT-2 kernel: [ 531.611217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:46 BXT-2 kernel: [ 531.611262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:46 BXT-2 kernel: [ 531.611338] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:46 BXT-2 kernel: [ 531.611383] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:46 BXT-2 kernel: [ 531.613173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:46 BXT-2 kernel: [ 531.613219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:46 BXT-2 kernel: [ 531.613264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:46 BXT-2 kernel: [ 531.614304] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:46 BXT-2 kernel: [ 531.614353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:46 BXT-2 kernel: [ 531.615608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:46 BXT-2 kernel: [ 531.617718] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:46 BXT-2 kernel: [ 531.618818] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:46 BXT-2 kernel: [ 531.635731] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:46 BXT-2 kernel: [ 531.635788] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:46 BXT-2 kernel: [ 531.635958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:49 BXT-2 kernel: [ 534.986168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:49 BXT-2 kernel: [ 534.987767] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:49 BXT-2 kernel: [ 535.004723] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:49 BXT-2 kernel: [ 535.004899] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:49 BXT-2 kernel: [ 535.005023] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:49 BXT-2 kernel: [ 535.005357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:49 BXT-2 kernel: [ 535.005401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:49 BXT-2 kernel: [ 535.005494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:49 BXT-2 kernel: [ 535.005538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:49 BXT-2 kernel: [ 535.005581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:49 BXT-2 kernel: [ 535.005625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:49 BXT-2 kernel: [ 535.005672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:49 BXT-2 kernel: [ 535.005716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:49 BXT-2 kernel: [ 535.005758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:49 BXT-2 kernel: [ 535.005801] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:49 BXT-2 kernel: [ 535.005849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:49 BXT-2 kernel: [ 535.005895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:49 BXT-2 kernel: [ 535.005940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:49 BXT-2 kernel: [ 535.006046] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:49 BXT-2 kernel: [ 535.006130] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:49 BXT-2 kernel: [ 535.006272] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:49 BXT-2 kernel: [ 535.006358] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:49 BXT-2 kernel: [ 535.006425] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:49 BXT-2 kernel: [ 535.006496] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:49 BXT-2 kernel: [ 535.006536] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:49 BXT-2 kernel: [ 535.007094] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:49 BXT-2 kernel: [ 535.007555] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:49 BXT-2 kernel: [ 535.007617] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:49 BXT-2 kernel: [ 535.067048] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:49 BXT-2 kernel: [ 535.067671] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:49 BXT-2 kernel: [ 535.068101] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:49 BXT-2 kernel: [ 535.068845] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:49 BXT-2 kernel: [ 535.068897] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:49 BXT-2 kernel: [ 535.069012] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:49 BXT-2 kernel: [ 535.069057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:49 BXT-2 kernel: [ 535.069101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:49 BXT-2 kernel: [ 535.069145] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:49 BXT-2 kernel: [ 535.069187] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:49 BXT-2 kernel: [ 535.069230] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:49 BXT-2 kernel: [ 535.069273] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:30:49 BXT-2 kernel: [ 535.069316] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:30:49 BXT-2 kernel: [ 535.069359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:49 BXT-2 kernel: [ 535.069401] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:49 BXT-2 kernel: [ 535.069929] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:49 BXT-2 kernel: [ 535.069938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:49 BXT-2 kernel: [ 535.069980] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:49 BXT-2 kernel: [ 535.069986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:49 BXT-2 kernel: [ 535.070029] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:49 BXT-2 kernel: [ 535.070072] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:49 BXT-2 kernel: [ 535.070115] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:49 BXT-2 kernel: [ 535.070157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:49 BXT-2 kernel: [ 535.070199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:49 BXT-2 kernel: [ 535.070244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:49 BXT-2 kernel: [ 535.070286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:49 BXT-2 kernel: [ 535.070329] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:30:49 BXT-2 kernel: [ 535.070372] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:30:49 BXT-2 kernel: [ 535.070414] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:30:49 BXT-2 kernel: [ 535.070969] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:30:49 BXT-2 kernel: [ 535.071038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:49 BXT-2 kernel: [ 535.071092] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:30:49 BXT-2 kernel: [ 535.071135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:30:49 BXT-2 kernel: [ 535.071935] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:49 BXT-2 kernel: [ 535.071973] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:49 BXT-2 kernel: [ 535.072261] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:49 BXT-2 kernel: [ 535.072314] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:49 BXT-2 kernel: [ 535.072355] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:49 BXT-2 kernel: [ 535.072411] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:49 BXT-2 kernel: [ 535.072978] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:49 BXT-2 kernel: [ 535.073301] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:49 BXT-2 kernel: [ 535.073344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:49 BXT-2 kernel: [ 535.073388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:49 BXT-2 kernel: [ 535.073430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:49 BXT-2 kernel: [ 535.073731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:49 BXT-2 kernel: [ 535.073775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:49 BXT-2 kernel: [ 535.073817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:49 BXT-2 kernel: [ 535.073860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:49 BXT-2 kernel: [ 535.073903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:49 BXT-2 kernel: [ 535.073946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:49 BXT-2 kernel: [ 535.074017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:49 BXT-2 kernel: [ 535.074063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:49 BXT-2 kernel: [ 535.074138] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:30:49 BXT-2 kernel: [ 535.074181] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:49 BXT-2 kernel: [ 535.075858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:49 BXT-2 kernel: [ 535.075905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:49 BXT-2 kernel: [ 535.075949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:49 BXT-2 kernel: [ 535.076976] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:49 BXT-2 kernel: [ 535.077021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:49 BXT-2 kernel: [ 535.078071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:49 BXT-2 kernel: [ 535.080173] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:49 BXT-2 kernel: [ 535.081232] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:30:49 BXT-2 kernel: [ 535.098123] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:49 BXT-2 kernel: [ 535.098178] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:30:49 BXT-2 kernel: [ 535.098348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:53 BXT-2 kernel: [ 538.448261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:53 BXT-2 kernel: [ 538.448387] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:30:53 BXT-2 kernel: [ 538.466722] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:30:53 BXT-2 kernel: [ 538.466835] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:53 BXT-2 kernel: [ 538.466925] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:53 BXT-2 kernel: [ 538.467245] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:53 BXT-2 kernel: [ 538.467288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:53 BXT-2 kernel: [ 538.467331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:53 BXT-2 kernel: [ 538.467375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:53 BXT-2 kernel: [ 538.467418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:53 BXT-2 kernel: [ 538.467507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:53 BXT-2 kernel: [ 538.467558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:53 BXT-2 kernel: [ 538.467602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:53 BXT-2 kernel: [ 538.467645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:53 BXT-2 kernel: [ 538.467689] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:53 BXT-2 kernel: [ 538.467737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:53 BXT-2 kernel: [ 538.467782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:53 BXT-2 kernel: [ 538.467827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:53 BXT-2 kernel: [ 538.467889] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:53 BXT-2 kernel: [ 538.467931] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:53 BXT-2 kernel: [ 538.467985] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:53 BXT-2 kernel: [ 538.468050] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:30:53 BXT-2 kernel: [ 538.468097] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:53 BXT-2 kernel: [ 538.468141] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:53 BXT-2 kernel: [ 538.468183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:53 BXT-2 kernel: [ 538.468769] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:53 BXT-2 kernel: [ 538.469182] [drm:drm_mode_addfb2] [FB:76] >May 24 03:30:53 BXT-2 kernel: [ 538.469245] [drm:drm_mode_addfb2] [FB:79] >May 24 03:30:53 BXT-2 kernel: [ 538.527824] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:53 BXT-2 kernel: [ 538.528279] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:53 BXT-2 kernel: [ 538.529075] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:53 BXT-2 kernel: [ 538.529621] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:53 BXT-2 kernel: [ 538.529673] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:53 BXT-2 kernel: [ 538.529794] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:53 BXT-2 kernel: [ 538.529838] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:53 BXT-2 kernel: [ 538.529883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:53 BXT-2 kernel: [ 538.529926] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:53 BXT-2 kernel: [ 538.529968] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:53 BXT-2 kernel: [ 538.530012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:53 BXT-2 kernel: [ 538.530055] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:30:53 BXT-2 kernel: [ 538.530098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:30:53 BXT-2 kernel: [ 538.530141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:53 BXT-2 kernel: [ 538.530183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:53 BXT-2 kernel: [ 538.530225] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:53 BXT-2 kernel: [ 538.530231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:53 BXT-2 kernel: [ 538.530273] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:53 BXT-2 kernel: [ 538.530279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:53 BXT-2 kernel: [ 538.530322] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:53 BXT-2 kernel: [ 538.530364] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:53 BXT-2 kernel: [ 538.530407] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:53 BXT-2 kernel: [ 538.531151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:53 BXT-2 kernel: [ 538.531194] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:53 BXT-2 kernel: [ 538.531238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:53 BXT-2 kernel: [ 538.531280] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:53 BXT-2 kernel: [ 538.531324] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:30:53 BXT-2 kernel: [ 538.531367] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:30:53 BXT-2 kernel: [ 538.531410] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:30:53 BXT-2 kernel: [ 538.531777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:53 BXT-2 kernel: [ 538.531832] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:30:53 BXT-2 kernel: [ 538.531875] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:30:53 BXT-2 kernel: [ 538.532650] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:53 BXT-2 kernel: [ 538.532689] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:53 BXT-2 kernel: [ 538.532979] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:53 BXT-2 kernel: [ 538.533032] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:53 BXT-2 kernel: [ 538.533072] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:53 BXT-2 kernel: [ 538.533128] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:53 BXT-2 kernel: [ 538.533420] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:53 BXT-2 kernel: [ 538.534074] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:53 BXT-2 kernel: [ 538.534119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:53 BXT-2 kernel: [ 538.534162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:53 BXT-2 kernel: [ 538.534205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:53 BXT-2 kernel: [ 538.534248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:53 BXT-2 kernel: [ 538.534291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:53 BXT-2 kernel: [ 538.534334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:53 BXT-2 kernel: [ 538.534376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:53 BXT-2 kernel: [ 538.534419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:53 BXT-2 kernel: [ 538.534590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:53 BXT-2 kernel: [ 538.534640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:53 BXT-2 kernel: [ 538.534685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:53 BXT-2 kernel: [ 538.534760] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:30:53 BXT-2 kernel: [ 538.534804] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:53 BXT-2 kernel: [ 538.536427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:53 BXT-2 kernel: [ 538.536503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:53 BXT-2 kernel: [ 538.536548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:53 BXT-2 kernel: [ 538.537306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:53 BXT-2 kernel: [ 538.537349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:53 BXT-2 kernel: [ 538.538354] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:53 BXT-2 kernel: [ 538.538401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:53 BXT-2 kernel: [ 538.539814] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:53 BXT-2 kernel: [ 538.541506] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:53 BXT-2 kernel: [ 538.542539] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:30:53 BXT-2 kernel: [ 538.559406] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:53 BXT-2 kernel: [ 538.559498] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:30:53 BXT-2 kernel: [ 538.559675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.909502] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:56 BXT-2 kernel: [ 541.909627] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:30:56 BXT-2 kernel: [ 541.928099] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:30:56 BXT-2 kernel: [ 541.928210] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.928289] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:56 BXT-2 kernel: [ 541.928658] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:56 BXT-2 kernel: [ 541.928704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:56 BXT-2 kernel: [ 541.928749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:56 BXT-2 kernel: [ 541.928792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:56 BXT-2 kernel: [ 541.928835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:56 BXT-2 kernel: [ 541.928879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:56 BXT-2 kernel: [ 541.928927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:56 BXT-2 kernel: [ 541.928970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:56 BXT-2 kernel: [ 541.929013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:56 BXT-2 kernel: [ 541.929057] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:56 BXT-2 kernel: [ 541.929104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:56 BXT-2 kernel: [ 541.929152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:56 BXT-2 kernel: [ 541.929197] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.929259] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:56 BXT-2 kernel: [ 541.929301] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:56 BXT-2 kernel: [ 541.929355] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:56 BXT-2 kernel: [ 541.929415] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:30:56 BXT-2 kernel: [ 541.929500] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:56 BXT-2 kernel: [ 541.929543] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:56 BXT-2 kernel: [ 541.929585] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:56 BXT-2 kernel: [ 541.930140] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:56 BXT-2 kernel: [ 541.965367] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:56 BXT-2 kernel: [ 541.965411] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:56 BXT-2 kernel: [ 541.965523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:56 BXT-2 kernel: [ 541.965566] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:56 BXT-2 kernel: [ 541.965607] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:56 BXT-2 kernel: [ 541.965650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:56 BXT-2 kernel: [ 541.965692] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:56 BXT-2 kernel: [ 541.965734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:56 BXT-2 kernel: [ 541.965776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:56 BXT-2 kernel: [ 541.965817] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:56 BXT-2 kernel: [ 541.965857] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:56 BXT-2 kernel: [ 541.965865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:56 BXT-2 kernel: [ 541.965905] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:56 BXT-2 kernel: [ 541.965910] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:56 BXT-2 kernel: [ 541.965952] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:56 BXT-2 kernel: [ 541.965993] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:56 BXT-2 kernel: [ 541.966035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:56 BXT-2 kernel: [ 541.966076] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:56 BXT-2 kernel: [ 541.966117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:56 BXT-2 kernel: [ 541.966161] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:56 BXT-2 kernel: [ 541.966201] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:56 BXT-2 kernel: [ 541.966244] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:56 BXT-2 kernel: [ 541.966286] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:56 BXT-2 kernel: [ 541.966327] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:56 BXT-2 kernel: [ 541.966370] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:56 BXT-2 kernel: [ 541.966414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:56 BXT-2 kernel: [ 541.966485] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.966528] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:56 BXT-2 kernel: [ 541.966669] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:56 BXT-2 kernel: [ 541.966705] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:56 BXT-2 kernel: [ 541.966992] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:56 BXT-2 kernel: [ 541.967047] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:56 BXT-2 kernel: [ 541.967086] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:56 BXT-2 kernel: [ 541.967140] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:56 BXT-2 kernel: [ 541.967379] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:56 BXT-2 kernel: [ 541.967695] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:56 BXT-2 kernel: [ 541.967738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:56 BXT-2 kernel: [ 541.967780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:56 BXT-2 kernel: [ 541.967821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:56 BXT-2 kernel: [ 541.967862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:56 BXT-2 kernel: [ 541.967904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:56 BXT-2 kernel: [ 541.967945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:56 BXT-2 kernel: [ 541.967986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:56 BXT-2 kernel: [ 541.968027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:56 BXT-2 kernel: [ 541.968069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:56 BXT-2 kernel: [ 541.968114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:56 BXT-2 kernel: [ 541.968157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.968229] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:56 BXT-2 kernel: [ 541.968271] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.969704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:56 BXT-2 kernel: [ 541.969745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:56 BXT-2 kernel: [ 541.969790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:56 BXT-2 kernel: [ 541.970551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:56 BXT-2 kernel: [ 541.970591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:56 BXT-2 kernel: [ 541.971305] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:56 BXT-2 kernel: [ 541.971347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:56 BXT-2 kernel: [ 541.972381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:56 BXT-2 kernel: [ 541.974462] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:56 BXT-2 kernel: [ 541.975625] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:56 BXT-2 kernel: [ 541.992526] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:56 BXT-2 kernel: [ 541.992577] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:56 BXT-2 kernel: [ 541.992751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 541.993099] Console: switching to colour frame buffer device 240x67 >May 24 03:30:56 BXT-2 kernel: [ 542.184276] Console: switching to colour dummy device 80x25 >May 24 03:30:56 BXT-2 kernel: [ 542.207968] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:30:56 BXT-2 kernel: [ 542.208029] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:30:56 BXT-2 kernel: [ 542.208043] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:30:56 BXT-2 kernel: [ 542.208066] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:30:56 BXT-2 kernel: [ 542.208111] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:56 BXT-2 kernel: [ 542.208812] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:30:56 BXT-2 kernel: [ 542.209701] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:30:56 BXT-2 kernel: [ 542.209747] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:30:56 BXT-2 kernel: [ 542.209789] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:30:56 BXT-2 kernel: [ 542.209831] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:30:56 BXT-2 kernel: [ 542.210316] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:30:56 BXT-2 kernel: [ 542.210358] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:30:56 BXT-2 kernel: [ 542.215102] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:30:56 BXT-2 kernel: [ 542.215169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:30:56 BXT-2 kernel: [ 542.215176] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215181] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215186] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215191] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215196] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215202] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215207] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:30:56 BXT-2 kernel: [ 542.215212] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215217] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.215222] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:30:56 BXT-2 kernel: [ 542.215227] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:30:56 BXT-2 kernel: [ 542.215231] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:30:56 BXT-2 kernel: [ 542.216477] [drm:drm_mode_addfb2] [FB:78] >May 24 03:30:56 BXT-2 kernel: [ 542.216538] [drm:drm_mode_addfb2] [FB:80] >May 24 03:30:56 BXT-2 kernel: [ 542.329103] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:56 BXT-2 kernel: [ 542.329278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:30:56 BXT-2 kernel: [ 542.329511] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:56 BXT-2 kernel: [ 542.343959] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:56 BXT-2 kernel: [ 542.344069] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 542.344155] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:56 BXT-2 kernel: [ 542.344680] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:56 BXT-2 kernel: [ 542.344725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:56 BXT-2 kernel: [ 542.344769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:56 BXT-2 kernel: [ 542.344811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:56 BXT-2 kernel: [ 542.344854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:56 BXT-2 kernel: [ 542.344897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:56 BXT-2 kernel: [ 542.344946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:56 BXT-2 kernel: [ 542.344988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:56 BXT-2 kernel: [ 542.345031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:56 BXT-2 kernel: [ 542.345074] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:56 BXT-2 kernel: [ 542.345123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:56 BXT-2 kernel: [ 542.345169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:56 BXT-2 kernel: [ 542.345213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:56 BXT-2 kernel: [ 542.345276] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:56 BXT-2 kernel: [ 542.345318] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:56 BXT-2 kernel: [ 542.345371] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:56 BXT-2 kernel: [ 542.345433] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:56 BXT-2 kernel: [ 542.346148] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:56 BXT-2 kernel: [ 542.346192] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:56 BXT-2 kernel: [ 542.346230] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:56 BXT-2 kernel: [ 542.347395] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:56 BXT-2 kernel: [ 542.347537] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:30:56 BXT-2 kernel: [ 542.347988] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:30:56 BXT-2 kernel: [ 542.348773] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:30:56 BXT-2 kernel: [ 542.348825] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:30:56 BXT-2 kernel: [ 542.348947] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:56 BXT-2 kernel: [ 542.348990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:56 BXT-2 kernel: [ 542.349034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:56 BXT-2 kernel: [ 542.349078] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:56 BXT-2 kernel: [ 542.349120] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:56 BXT-2 kernel: [ 542.349163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:56 BXT-2 kernel: [ 542.349206] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:56 BXT-2 kernel: [ 542.349249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:56 BXT-2 kernel: [ 542.349292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:56 BXT-2 kernel: [ 542.349334] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:56 BXT-2 kernel: [ 542.349376] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:56 BXT-2 kernel: [ 542.349382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.349424] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:56 BXT-2 kernel: [ 542.349973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.350029] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:56 BXT-2 kernel: [ 542.350073] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:56 BXT-2 kernel: [ 542.350115] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:56 BXT-2 kernel: [ 542.350158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:56 BXT-2 kernel: [ 542.350200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:56 BXT-2 kernel: [ 542.350245] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:56 BXT-2 kernel: [ 542.350287] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:56 BXT-2 kernel: [ 542.350329] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:30:56 BXT-2 kernel: [ 542.350372] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:56 BXT-2 kernel: [ 542.350415] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.350873] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.350942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.350994] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.351038] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.351854] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.351893] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.352181] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.352235] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.352275] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.352330] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.352882] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.353208] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.353252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.353295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.353338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.353380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.353423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.353524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.353567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.353610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.353655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.353702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.353747] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.353821] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.353864] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.355529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.355573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.355617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.356369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.356411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.357416] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.357602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.358802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.360896] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.361940] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.378799] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.378854] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.379024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.412256] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.412302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.412347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.412391] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.412693] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.412740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.412785] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.412828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.412871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.412913] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.412955] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.412964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.413006] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.413012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.413055] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.413098] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.413140] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.413183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.413225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.413273] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.413315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.413359] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.413402] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.414133] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.414177] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.414219] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.414290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.414345] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.414388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.428950] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.447384] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.447569] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.447828] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.448156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.448200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.448243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.448286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.448330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.448375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.448417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.448498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.448543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.448586] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.448633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.448678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.448738] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.448780] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.448834] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.448887] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.448934] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.448987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.449032] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.449077] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.449117] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.449697] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.450792] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.450837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.450883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.450926] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.450968] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.451012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.451055] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.451098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.451141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.451183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.451224] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.451233] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.451274] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.451280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.451323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.451366] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.451408] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.451486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.451530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.451575] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.451617] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.451663] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.451706] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.451750] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.451794] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.451839] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.451906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.451959] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.452002] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.452149] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.452187] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.452500] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.452556] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.452598] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.452654] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.453529] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.453861] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.453907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.453950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.453992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.454035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.454081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.454126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.454168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.454212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.454255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.454301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.454347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.454420] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.454493] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.456154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.456199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.456244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.457138] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.457183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.458240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.460335] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.461359] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.461762] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.461816] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.461985] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.478545] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.478592] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.478636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.478680] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.478722] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.478765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.478808] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.478851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.478894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.478936] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.478977] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.478987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.479029] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.479035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.479077] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.479120] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.479162] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.479204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.479246] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.479291] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.479333] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.479380] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.479423] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.480313] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.480357] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.480399] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.480638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.480693] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.480736] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.494926] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.513415] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.513559] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.513645] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.513973] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.514017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.514061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.514106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.514150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.514196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.514239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.514281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.514324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.514368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.514413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.514995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.515057] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.515101] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.515154] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.515206] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.515253] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.515305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.515351] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.515393] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.515784] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.516331] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.516879] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.516924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.516968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.517012] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.517054] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.517098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.517142] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.517187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.517230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.517272] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.517314] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.517323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.517365] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.517370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.517413] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.518038] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.518081] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.518124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.518166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.518211] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.518253] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.518298] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.518340] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.518383] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.518426] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.518845] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.518912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.518967] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.519009] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.519156] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.519194] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.519812] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.520120] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.520160] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.520216] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.520696] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.521015] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.521059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.521102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.521145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.521187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.521230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.521273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.521315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.521360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.521402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.521868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.521913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.521988] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.522031] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.523493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.523537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.523581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.524338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.524380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.525372] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.525417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.526620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.528719] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.529779] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.529980] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.530032] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.530202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.546934] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.546980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.547025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.547068] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.547110] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.547154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.547197] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.547239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.547282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.547324] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.547366] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.547375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.547417] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.547974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.548032] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.548075] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.548118] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.548161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.548203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.548248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.548290] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.548335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.548378] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.548420] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.548892] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.548936] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.549005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.549057] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.549100] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.563371] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.581880] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.581990] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.582077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.582396] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.582671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.582716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.582759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.582802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.582848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.582890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.582933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.582976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.583019] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.583066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.583110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.583171] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.583213] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.583266] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.583315] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.583360] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.583412] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.584105] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.584148] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.584187] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.585353] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.585881] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.585926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.585971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.586015] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.586057] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.586101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.586144] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.586187] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.586230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.586272] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.586314] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.586323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.586364] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.586370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.586413] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.587042] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.587085] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.587128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.587170] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.587215] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.587257] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.587302] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.587344] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.587387] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.587430] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.587863] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.587931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.587985] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.588028] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.588173] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.588211] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.588765] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.589122] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.589162] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.589218] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.589708] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.590026] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.590070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.590114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.590157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.590200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.590243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.590285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.590328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.590370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.590413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.590878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.590923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.590998] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.591041] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.592692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.592737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.592781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.593677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.593720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.594597] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.594641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.595838] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.597938] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.598970] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.599169] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.599221] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.599391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.616115] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.616160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.616205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.616249] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.616290] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.616334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.616377] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.616420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.616844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.616886] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.616928] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.616937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.616979] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.616985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.617027] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.617070] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.617113] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.617155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.617197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.617244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.617286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.617330] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.617373] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.617415] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.618060] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.618104] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.618173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.618226] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.618269] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.632591] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.651082] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.651192] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.651280] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.651830] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.651876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.651920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.651962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.652005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.652048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.652091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.652133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.652176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.652219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.652266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.652310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.652370] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.652411] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.652982] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.653034] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.653083] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.653135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.653183] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.653227] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.653267] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.654433] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.654878] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.654921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.654966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.655010] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.655052] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.655095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.655138] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.655181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.655224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.655267] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.655308] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.655317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.655359] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.655365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.655408] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.656076] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.656119] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.656162] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.656204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.656249] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.656291] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.656336] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.656379] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.656422] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.656825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.656868] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.656938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.656993] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.657036] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.657184] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.657222] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.657885] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.658195] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.658238] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.658293] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.658787] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.659109] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.659154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.659197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.659241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.659284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.659327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.659371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.659414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.659840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.659886] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.659934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.659979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.660055] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.660099] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.661771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.661815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.661859] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.662682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.662725] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.663606] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.663652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.664833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.666935] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.668001] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.668194] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.668246] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.668415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.685134] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.685178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.685223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.685266] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.685308] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.685352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.685395] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.685785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.685828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.685870] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.685912] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.685921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.685963] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.685969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.686011] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.686054] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.686096] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.686139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.686181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.686225] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.686267] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.686311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.686354] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.686397] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.687065] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.687108] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.687176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.687231] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.687274] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.701586] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.720074] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.720186] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.720273] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.720822] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.720870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.720915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.720958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.721002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.721046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.721091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.721133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.721176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.721219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.721265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.721309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.721369] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.721411] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.722004] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.722055] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.722102] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.722155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.722203] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.722246] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.722284] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.723468] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.723883] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.723927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.723972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.724015] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.724057] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.724101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.724146] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.724189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.724231] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.724274] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.724315] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.724325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.724367] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.724373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.724416] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.725070] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.725114] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.725156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.725198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.725244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.725286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.725331] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.725374] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.725417] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.725828] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.725871] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.725939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.725992] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.726035] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.726180] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.726217] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.726814] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.727129] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.727169] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.727225] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.727708] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.728032] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.728076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.728119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.728161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.728204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.728247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.728289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.728332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.728374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.728417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.728888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.728933] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.729009] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.729053] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.730715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.730759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.730803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.731678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.731721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.732597] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.732642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.733837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.735939] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.736974] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.737168] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.737221] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.737391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.754109] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.754155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.754201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.754244] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.754286] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.754330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.754375] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.754417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.754881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.754924] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.754965] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.754975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.755016] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.755022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.755065] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.755108] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.755150] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.755193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.755234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.755279] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.755321] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.755366] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.755408] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.756007] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.756050] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.756093] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.756161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.756215] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.756258] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.770602] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.789085] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.789195] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.789281] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.789782] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.789828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.789872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.789915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.789959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.790002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.790045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.790087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.790130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.790173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.790219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.790263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.790322] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.790364] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.790417] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.791025] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.791072] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.791125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.791173] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.791216] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.791254] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.792422] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.792859] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.792903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.792950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.792993] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.793035] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.793079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.793124] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.793166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.793209] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.793252] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.793293] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.793302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.793344] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.793349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.793392] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.794054] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.794098] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.794140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.794183] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.794228] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.794269] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.794315] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.794357] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.794400] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.794815] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.794858] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.794927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.794980] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.795022] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.795167] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.795205] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.795810] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.796119] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.796159] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.796215] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.796700] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.797021] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.797064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.797107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.797150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.797192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.797235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.797278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.797320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.797363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.797406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.797878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.797924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.797998] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.798041] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.799698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.799742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.799786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.800666] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.800710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.801433] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.801666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.802819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.804921] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.805953] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.806151] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.806203] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.806373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.823089] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.823135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.823179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.823223] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.823265] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.823308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.823351] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.823394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.823856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.823898] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.823940] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.823949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.823991] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.823998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.824041] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.824085] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.824128] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.824172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.824213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.824262] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.824303] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.824351] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.824394] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.824987] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.825030] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.825073] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.825141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.825194] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.825236] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.839565] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.858057] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.858168] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.858256] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.858816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.858863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.858908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.858951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.858995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.859042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.859086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.859129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.859173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.859217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.859264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.859309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.859371] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.859413] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.860002] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.860054] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.860101] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.860153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.860202] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.860244] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.860283] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.861470] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.861877] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.861921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.861968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.862011] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.862053] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.862097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.862142] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.862184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.862227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.862269] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.862311] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.862320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.862361] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.862367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.862410] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.863058] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.863101] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.863144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.863186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.863234] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.863276] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.863325] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.863368] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.863411] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.863827] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.863871] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.863941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.863994] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.864037] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.864186] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.864223] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.864811] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.865134] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.865177] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.865232] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.865692] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.866022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.866066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.866109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.866153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.866198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.866244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.866286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.866329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.866371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.866414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.866887] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.866932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.867006] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.867049] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.868714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.868757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.868803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.869687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.869732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.870612] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.870657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.871829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.873925] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.874989] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.875193] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.875246] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.875415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.892143] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.892188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.892234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.892277] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.892319] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.892363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.892406] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.892799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.892842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.892884] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.892926] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.892937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.892978] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.892986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.893029] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.893071] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.893114] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.893156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.893198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.893248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.893289] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.893334] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.893377] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.893420] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.894085] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.894128] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.894196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.894249] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.894292] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.908587] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.926745] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.926857] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.926945] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.927274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.927318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.927361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.927404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.927827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.927870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.927913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.927955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.927998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.928041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.928089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.928134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.928193] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.928236] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.928289] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.928338] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.928384] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.928942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.928996] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.929039] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 542.929077] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 542.930245] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.930788] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.930834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.930880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.930923] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.930965] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.931009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.931052] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.931095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.931138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.931180] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.931221] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.931230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.931272] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.931277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.931320] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.931363] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.931406] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.932087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.932129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.932174] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.932216] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.932261] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.932304] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.932347] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.932390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.932433] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.932866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.932921] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.932964] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.933111] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 542.933148] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 542.933682] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 542.934062] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.934103] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.934158] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.934679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.934999] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.935043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.935086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.935128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.935171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.935214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.935256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.935299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.935341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.935384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.935431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.935922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.935997] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.936040] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.937644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.937688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.937732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 542.938649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.938692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 542.939410] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 542.939626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 542.940771] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 542.942866] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 542.943866] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.944073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.944126] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 542.944294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.961066] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 542.961113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 542.961158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 542.961202] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 542.961244] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 542.961288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.961331] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 542.961374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.961417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 542.961943] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.961985] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 542.961994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.962036] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 542.962042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.962085] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 542.962128] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 542.962171] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 542.962214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 542.962256] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 542.962301] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 542.962343] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 542.962388] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 542.962432] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 542.963112] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.963156] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.963199] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 542.963272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.963327] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.963370] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.977596] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 542.996233] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 542.996351] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.996996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.997331] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 542.997376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 542.997420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.998074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.998117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.998161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 542.998204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 542.998247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 542.998290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 542.998334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 542.998385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 542.998430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 542.999201] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 542.999246] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.999301] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 542.999351] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 542.999398] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.000024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.000077] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.000121] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 543.000160] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 543.001517] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.001966] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.002011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.002058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.002102] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.002145] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.002190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.002234] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.002277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.002320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.002363] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.002405] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.003292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.003349] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.003355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.003399] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.004017] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.004061] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.004104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.004147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.004194] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.004236] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.004282] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.004326] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.004369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.004413] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.005217] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.005293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.005348] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.005392] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.006068] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.006107] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.006398] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 543.007219] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.007261] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.007318] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.008128] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.008880] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.008930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.008974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.009018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.009061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.009105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.009148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.009191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.009234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.009278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.009327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.009372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.010358] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.010405] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.012313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.012360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.012406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 543.013775] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 543.013824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 543.015351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 543.017261] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 543.018317] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.019025] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.019082] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.019253] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.035625] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.035673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.035719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.035764] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.035806] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.035851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.035894] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.035938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.035981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.036023] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.036066] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.036075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.036117] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.036123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.036166] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.036210] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.036253] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.036295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.036338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.036384] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.036426] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.037772] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.037816] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.037860] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.037904] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.037947] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.038025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.038081] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.038125] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.052000] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.068700] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.068812] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.068900] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.069219] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.069264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.069307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.069349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.069392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.070098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.070141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.070184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.070226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.070269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.070318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.070363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.070424] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.071103] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.071157] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.071208] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.071256] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.071309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.071358] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.071401] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 543.072042] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 543.073211] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.073968] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.074014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.074059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.074103] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.074145] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.074189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.074232] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.074275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.074318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.074360] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.074402] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.075187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.075245] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.075251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.075296] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.075339] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.075382] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.075425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.076125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.076171] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.076214] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.076260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.076304] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.076348] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.076391] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.077132] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.077204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.077259] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.077302] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.077940] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.077981] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.078274] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 543.078331] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.078372] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.079103] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.079377] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.080145] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.080213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.080270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.080327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.080383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.080428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.081241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.081296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.081351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.081406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.082110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.082168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.082267] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.082326] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.084394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.084505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.084551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 543.085350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.085398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.086797] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 543.086847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 543.088372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 543.090514] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 543.091615] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.091849] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.091903] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.092077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.108907] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.108955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.109001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.109045] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.109088] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.109132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.109177] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.109221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.109264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.109306] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.109348] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.109358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.109400] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.110453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.110512] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.110556] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.110599] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.110642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.110685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.110731] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.110774] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.110821] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.110865] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.110909] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.110952] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.110995] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.111083] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.111143] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.111187] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.125299] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.142831] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.142943] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.143031] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.143350] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.143394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.144020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.144064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.144107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.144150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.144193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.144237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.144280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.144323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.144375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.144420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.145368] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.145413] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.145956] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.146010] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.146059] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.146112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.146165] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.146209] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 543.146248] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 543.147884] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.148325] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.148370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.148416] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.149043] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.149086] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.149132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.149178] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.149221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.149264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.149306] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.149348] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.149357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.149399] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.150168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.150225] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.150268] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.150312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.150354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.150397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.151067] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.151110] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.151156] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.151199] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.151242] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.151285] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.151327] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.151400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.152112] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.152156] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.152313] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.152351] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.153191] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 543.153870] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.153914] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.153970] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.154285] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.155115] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.155163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.155207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.155250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.155293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.155336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.155379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.155422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.156175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.156219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.156270] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.156315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.156390] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.157028] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.158958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.159005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.159050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 543.160277] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 543.160326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 543.161793] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 543.163903] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 543.164977] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.165199] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.165251] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.165422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.182217] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.182266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.182312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.182356] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.182399] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.183041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.183088] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.183131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.183174] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.183217] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.183258] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.183268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.183309] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.183315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.183358] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.183401] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.184362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.184405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.184882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.184928] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.184971] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.185016] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.185059] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.185103] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.185146] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.185189] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.185259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.185313] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.185356] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.198657] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.217334] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.217927] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.218023] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.218342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.218386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.218430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.219018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.219061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.219105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.219148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.219191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.219233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.219277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.219327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.219372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.220133] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.220180] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.220235] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.220285] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.220332] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.220387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.221093] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.221142] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 543.221181] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 543.222487] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.223434] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.223946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.223993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.224038] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.224080] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.224125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.224171] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.224214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.224257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.224299] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.224341] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.224349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.224392] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.225283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.225341] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.225386] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.225429] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.226000] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.226043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.226089] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.226131] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.226177] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.226220] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.226263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.226306] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.226349] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.226417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.227268] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.227311] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.227914] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.227955] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.228245] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 543.228301] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.228341] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.228397] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.229392] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.230158] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.230204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.230248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.230290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.230333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.230376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.230419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.231130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.231174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.231218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.231269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.231314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.231390] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.232026] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.233914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.233961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.234006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 543.235224] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 543.235272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 543.236781] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 543.238892] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 543.240010] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.240212] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.240265] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.240963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.257235] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.257282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.257327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.257372] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.257414] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.258132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.258180] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.258223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.258266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.258309] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.258350] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.258359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.258401] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.259198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.259255] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.259298] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.259342] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.259385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.259427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.260076] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.260119] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.260165] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.260208] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.260252] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.260295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.260338] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.260411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.261137] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.261181] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.273682] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.291746] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.291860] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.291948] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.292277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.292321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.292365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.292407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.292648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.292692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.292735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.292778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.292821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.292866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.292917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.292962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.293023] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.293067] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.293121] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.293173] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.293221] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.293273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.293320] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.293366] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:57 BXT-2 kernel: [ 543.293404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:57 BXT-2 kernel: [ 543.294098] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.294844] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.294890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.294936] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.294980] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.295022] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.295067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.295110] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.295153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.295196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.295239] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.295280] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.295289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.295331] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.295337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.295380] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.295422] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.295881] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.295924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.295967] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.296013] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.296055] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.296100] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.296144] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.296187] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.296232] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.296275] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.296342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.296397] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.296760] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.296916] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:57 BXT-2 kernel: [ 543.296954] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:57 BXT-2 kernel: [ 543.297252] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:57 BXT-2 kernel: [ 543.297308] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.297349] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:57 BXT-2 kernel: [ 543.297405] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:57 BXT-2 kernel: [ 543.298019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.298346] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.298390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:57 BXT-2 kernel: [ 543.298752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.298798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.298841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.298884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:57 BXT-2 kernel: [ 543.298927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:57 BXT-2 kernel: [ 543.298970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:57 BXT-2 kernel: [ 543.299013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:57 BXT-2 kernel: [ 543.299056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:57 BXT-2 kernel: [ 543.299106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:57 BXT-2 kernel: [ 543.299151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.299226] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:57 BXT-2 kernel: [ 543.299269] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.301099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.301145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:57 BXT-2 kernel: [ 543.301190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:57 BXT-2 kernel: [ 543.302179] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:57 BXT-2 kernel: [ 543.302226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:57 BXT-2 kernel: [ 543.303647] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:57 BXT-2 kernel: [ 543.305763] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:57 BXT-2 kernel: [ 543.306851] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.307060] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:57 BXT-2 kernel: [ 543.307113] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:57 BXT-2 kernel: [ 543.307283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.323987] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:57 BXT-2 kernel: [ 543.324033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:57 BXT-2 kernel: [ 543.324078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:57 BXT-2 kernel: [ 543.324122] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:57 BXT-2 kernel: [ 543.324164] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:57 BXT-2 kernel: [ 543.324208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.324251] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:57 BXT-2 kernel: [ 543.324294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.324337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:57 BXT-2 kernel: [ 543.324379] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.324421] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:57 BXT-2 kernel: [ 543.324479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.324523] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:57 BXT-2 kernel: [ 543.324530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.324575] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:57 BXT-2 kernel: [ 543.324619] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:57 BXT-2 kernel: [ 543.324665] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:57 BXT-2 kernel: [ 543.324708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:57 BXT-2 kernel: [ 543.324751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:57 BXT-2 kernel: [ 543.324798] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:57 BXT-2 kernel: [ 543.324841] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:57 BXT-2 kernel: [ 543.324886] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:57 BXT-2 kernel: [ 543.324929] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:57 BXT-2 kernel: [ 543.324972] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.325015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.325058] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:57 BXT-2 kernel: [ 543.325121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:57 BXT-2 kernel: [ 543.325173] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:57 BXT-2 kernel: [ 543.325218] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:57 BXT-2 kernel: [ 543.340523] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.358909] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.359023] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.359112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.359432] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.359532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.359579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.359623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.359666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.359711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.359754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.359797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.359840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.359883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.359929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.359976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.360035] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.360078] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.360132] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.360182] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.360230] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.360282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.360329] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.360373] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.360412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.361005] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.361429] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.361533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.361581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.361626] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.361668] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.361715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.361759] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.361802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.361845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.361887] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.361929] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.361938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.361980] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.361987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.362030] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.362074] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.362117] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.362160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.362203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.362248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.362291] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.362338] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.362381] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.362425] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.362498] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.362545] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.362611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.362666] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.362710] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.362867] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.362905] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.363202] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.363257] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.363299] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.363356] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.363726] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.364047] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.364092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.364135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.364178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.364222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.364267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.364310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.364353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.364396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.364484] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.364534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.364583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.364660] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.364703] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.366155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.366201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.366246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.367307] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.367355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.368551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.370508] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.371564] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.371776] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.371829] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.372002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.388739] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.388786] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.388831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.388875] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.388918] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.388962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.389005] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.389048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.389091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.389134] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.389176] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.389185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.389227] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.389232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.389276] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.389319] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.389361] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.389404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.389496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.389542] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.389587] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.389632] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.389675] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.389720] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.389763] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.389806] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.389873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.389929] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.389972] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.405135] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.422748] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.422860] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.422949] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.423275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.423319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.423362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.423405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.423527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.423574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.423617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.423660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.423704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.423748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.423796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.423841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.423902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.423945] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.423999] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.424049] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.424096] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.424148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.424195] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.424239] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.424279] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.424871] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.425309] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.425355] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.425401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.425485] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.425527] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.425574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.425620] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.425665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.425709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.425754] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.425797] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.425806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.425847] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.425853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.425896] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.425940] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.425984] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.426026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.426069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.426115] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.426157] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.426203] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.426247] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.426290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.426334] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.426377] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.426471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.426526] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.426569] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.426720] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.426758] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.427047] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.427102] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.427143] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.427201] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.427535] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.427860] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.427905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.427949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.427992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.428035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.428079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.428122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.428165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.428208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.428252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.428300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.428345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.428420] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.428498] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.429948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.429992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.430036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.431038] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.431085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.432173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.434284] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.435290] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.435809] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.435865] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.436036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.454403] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.454624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.454671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.454715] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.454757] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.454801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.454846] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.454889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.454932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.454974] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.455016] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.455025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.455067] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.455073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.455116] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.455159] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.455201] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.455244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.455286] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.455330] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.455372] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.455417] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.457295] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.457339] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.457381] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.457424] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.457756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.457812] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.457855] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.468855] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.487054] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.487167] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.487256] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.487648] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.487695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.487738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.487781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.487824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.487867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.487910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.487953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.487996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.488039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.488086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.488131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.488192] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.488234] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.488288] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.488337] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.488383] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.488463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.488510] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.488553] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.488592] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.489149] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.489627] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.489673] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.489718] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.489762] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.489804] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.489848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.489892] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.489935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.489978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.490021] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.490062] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.490071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.490113] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.490119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.490162] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.490205] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.490247] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.490290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.490333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.490378] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.490421] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.490494] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.490538] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.490581] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.490624] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.490668] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.490736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.490792] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.490835] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.493252] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.493292] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.493850] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.494978] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.495022] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.495078] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.495335] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.496000] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.496048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.496092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.496134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.496177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.496220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.496263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.496306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.496349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.496393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.497102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.497149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.497226] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.497270] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.499059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.499107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.499151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.500261] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.500336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.501593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.503505] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.504576] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.504780] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.504833] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.505004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.521743] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.521790] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.521835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.521879] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.521921] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.521965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.522008] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.522051] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.522094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.522136] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.522178] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.522187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.522229] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.522234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.522277] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.522320] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.522362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.522405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.522531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.522576] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.522618] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.522663] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.522706] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.522750] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.522793] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.522835] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.522903] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.522956] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.522999] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.538188] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.555819] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.555931] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.556019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.556339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.556383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.556426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.556529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.556572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.556618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.556661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.556705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.556748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.556791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.556839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.556884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.556946] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.556989] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.557043] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.557092] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.557141] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.557193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.557240] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.557285] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.557324] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.557919] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.558351] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.558398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.558498] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.558542] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.558585] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.558629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.558674] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.558718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.558762] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.558804] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.558848] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.558857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.558899] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.558906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.558949] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.558992] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.559035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.559078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.559121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.559166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.559209] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.559254] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.559297] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.559340] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.559385] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.559428] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.559537] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.559592] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.559637] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.559796] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.559833] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.560132] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.560188] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.560230] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.560286] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.560630] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.560956] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.561000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.561044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.561087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.561131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.561174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.561218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.561260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.561304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.561347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.561395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.561573] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.561648] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.561691] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.563130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.563175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.563219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.564035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.564078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.564856] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.564901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.566010] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.568139] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.569227] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.569456] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.569894] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.570064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.586378] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.586425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.586535] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.586858] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.586900] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.586945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.586990] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.587033] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.587076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.587118] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.587160] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.587169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.587210] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.587216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.587259] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.587302] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.587345] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.587387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.587429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.587511] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.587554] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.587600] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.587647] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.587694] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.587739] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.587786] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.587851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.588199] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.588242] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.602828] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.620728] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.620842] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.620933] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.621267] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.621312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.621355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.621398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.621850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.621895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.621937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.621980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.622023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.622066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.622116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.622161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.622224] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.622267] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.622320] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.622369] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.622415] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.622846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.622898] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.622943] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.622982] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.624152] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.625309] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.625357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.625403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.625492] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.625538] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.625585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.625629] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.625676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.625720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.625763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.625806] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.625815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.625857] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.625863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.625907] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.625950] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.625994] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.626037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.626080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.626126] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.626169] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.626214] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.626258] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.626301] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.626345] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.626388] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.626488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.626543] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.626587] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.626740] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.626779] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.627070] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.627125] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.627168] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.627225] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.627504] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.627836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.627880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.627924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.627966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.628009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.628052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.628094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.628136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.628179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.628222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.628268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.628314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.628387] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.628430] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.629892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.629935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.629979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.630762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.630805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.631639] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.631683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.632852] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.634945] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.635977] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.636177] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.636229] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.636398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.653121] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.653167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.653212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.653256] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.653298] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.653342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.653385] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.653428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.653523] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.653805] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.653848] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.653858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.653899] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.653906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.653949] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.653992] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.654036] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.654078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.654121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.654167] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.654209] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.654254] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.654298] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.654342] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.654385] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.654428] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.654885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.654942] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.654986] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.669602] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.687761] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.687875] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.687965] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.688289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.688333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.688376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.688419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.688518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.688562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.688608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.688651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.688695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.688739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.688790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.688837] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.688902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.688946] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.689001] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.689051] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.689100] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.689153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.689200] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.689244] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.689283] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.689877] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.690962] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.691016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.691062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.691110] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.691153] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.691200] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.691246] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.691291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.691336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.691380] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.691424] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.691996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.692054] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.692060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.692104] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.692148] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.692191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.692234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.692277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.692322] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.692364] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.692409] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.692498] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.692542] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.692587] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.692631] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.692706] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.692761] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.692807] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.692961] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.693000] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.693299] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.693357] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.693398] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.693493] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.694078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.694411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.694975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.695020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.695063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.695105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.695148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.695191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.695234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.695276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.695319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.695369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.695414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.695875] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.695925] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.697616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.697662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.697707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.698826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.698872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.699779] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.699826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.701159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.702527] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.703601] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.703805] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.703858] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.704029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.720788] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.720835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.720880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.720923] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.720965] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.721009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.721052] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.721095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.721138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.721180] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.721222] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.721231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.721272] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.721278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.721321] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.721364] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.721407] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.721498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.721542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.721593] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.721636] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.721682] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.721727] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.721773] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.721819] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.721864] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.721928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.721978] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.722024] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.737258] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.754713] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.754826] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.754914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.755237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.755281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.755324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.755367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.755409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.755488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.755535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.755585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.755630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.755675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.755724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.755769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.755831] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.755874] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.755928] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.755978] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.756027] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.756079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.756128] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.756172] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.756211] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.756789] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.757206] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.757251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.757296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.757340] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.757381] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.757425] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.757506] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.757552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.757599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.757643] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.757688] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.757698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.757741] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.757749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.757794] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.757838] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.757882] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.757925] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.757968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.758013] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.758056] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.758101] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.758145] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.758188] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.758232] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.758274] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.758340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.758394] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.758499] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.758655] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.758694] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.758985] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.759040] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.759082] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.759138] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.759389] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.759924] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.759969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.760012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.760055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.760097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.760140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.760183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.760225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.760268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.760311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.760357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.760401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.760513] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.760557] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.761993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.762038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.762082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.762863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.762906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.763642] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.763687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.764788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.766875] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.767903] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.768093] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.768145] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.768314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.785096] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.785143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.785189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.785233] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.785275] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.785318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.785361] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.785404] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.785496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.785542] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.785589] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.785600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.785643] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.785651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.785695] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.785739] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.786098] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.786142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.786186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.786231] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.786274] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.786319] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.786363] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.786407] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.786857] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.786900] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.786969] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.787023] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.787066] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.801483] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.819847] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.819959] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.820048] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.820370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.820414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.820497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.820542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.820588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.820633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.820678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.820721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.820766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.820809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.820855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.820900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.820959] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.821002] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.821055] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.821107] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.821154] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.821207] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.821255] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.821299] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.821338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.821919] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.822353] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.822399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.822503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.822547] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.822591] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.822636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.822681] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.822725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.822768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.822811] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.822853] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.822863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.822904] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.822911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.822955] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.822998] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.823041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.823084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.823127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.823172] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.823215] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.823260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.823303] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.823346] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.823390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.823432] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.823570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.823624] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.823667] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.823820] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.823858] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.824148] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.824203] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.824244] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.824301] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.824846] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.825523] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.825570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.825614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.825657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.825701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.825744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.825787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.825830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.825874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.825917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.825966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.826011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.826087] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.826131] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.827874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.827919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.827963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.828760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.828805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.829526] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.829570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.830616] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.832492] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.833501] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.833711] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.833764] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.833935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.850674] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.850721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.850766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.850810] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.850852] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.850896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.850938] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.850981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.851024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.851066] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.851108] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.851117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.851159] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.851165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.851208] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.851251] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.851293] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.851335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.851378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.851422] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.851517] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.851565] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.851610] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.851655] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.851701] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.851745] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.851807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.851857] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.851902] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.867144] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.884748] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.884860] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.884949] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.885272] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.885317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.885360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.885403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.885500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.885545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.885589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.885632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.885675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.885718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.885765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.885810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.885871] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.885914] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.885968] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.886018] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.886064] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.886117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.886164] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.886207] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.886246] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.886832] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.887256] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.887303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.887349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.887395] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.887488] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.887534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.887578] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.887621] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.887665] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.887707] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.887750] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.887759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.887802] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.887808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.887852] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.887895] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.887938] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.887981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.888023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.888068] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.888111] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.888156] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.888200] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.888243] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.888286] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.888329] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.888394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.888470] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.888514] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.888671] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.888709] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.888998] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.889052] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.889094] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.889151] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.889934] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.890257] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.890301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.890344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.890387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.890430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.890546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.890589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.890632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.890675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.890719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.890767] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.890812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.890886] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.890930] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.892743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.892787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.892832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.893702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.893746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.894505] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.894551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.895621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.897510] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.898583] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.898782] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.898835] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.899004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.915731] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.915777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.915822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.915866] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.915908] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.915951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.915994] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.916037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.916080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.916122] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.916164] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.916173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.916215] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.916220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.916263] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.916306] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.916348] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.916390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.916493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.916540] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.916584] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.916630] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.916676] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.916721] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.916766] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.916811] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.916872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.916922] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.916967] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.932166] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.949728] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.949841] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.949929] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.950248] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.950292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.950335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.950378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.950421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.950524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.950574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.950619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.950663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.950711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.950759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.950804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.950870] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.950912] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.950966] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.951016] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.951064] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.951117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.951163] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.951207] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 543.951245] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 543.951838] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.952257] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.952303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.952348] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.952392] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.952521] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.952566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.952611] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.952654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.952698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.952741] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.952783] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.952793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.952835] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.952841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.952885] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.952928] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.952971] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.953014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.953056] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.953101] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.953144] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.953189] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.953233] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.953276] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.953319] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.953362] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.953429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.953513] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.953556] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.953710] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 543.953748] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 543.954037] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 543.954091] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.954134] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 543.954190] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 543.954679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.955010] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.955054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 543.955097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.955139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.955182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.955225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 543.955267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 543.955310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 543.955352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 543.955395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 543.955509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 543.955556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.955632] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 543.955676] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.957226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.957271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 543.957315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 543.958159] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 543.958204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 543.959305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 543.961406] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 543.962485] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.962676] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 543.962728] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 543.962898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.979630] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 543.979676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 543.979721] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 543.979764] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 543.979806] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 543.979850] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.979892] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 543.979935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.979978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 543.980020] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.980062] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 543.980071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.980112] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 543.980118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.980161] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 543.980204] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 543.980246] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 543.980288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 543.980331] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 543.980375] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 543.980417] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 543.980498] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 543.980544] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 543.980589] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.980634] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.980678] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 543.980738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 543.980788] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 543.980831] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 543.996112] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.013718] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.013831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.013920] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.014242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.014286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.014329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.014372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.014415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.014516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.014560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.014603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.014645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.014689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.014736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.014781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.014844] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.014887] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.014940] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.014990] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.015036] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.015089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.015135] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.015178] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 544.015217] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 544.015796] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.016222] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.016267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.016313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.016357] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.016399] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.016493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.016539] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.016582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.016626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.016669] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.016711] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.016721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.016763] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.016769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.016812] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.016856] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.016899] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.016942] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.016985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.017030] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.017073] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.017118] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.017161] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.017205] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.017248] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.017291] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.017359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.017415] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.017479] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.017637] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.017674] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.017964] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 544.018018] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.018060] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.018117] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.018897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.019224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.019268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.019311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.019354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.019396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.019490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.019535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.019577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.019620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.019664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.019712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.019757] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.019832] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.019876] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.021705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.021752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.021796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 544.022865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.022911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.023971] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 544.024018] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 544.025182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 544.027351] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 544.028750] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.028943] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.028995] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.029164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.045896] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.045943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.045988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.046031] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.046073] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.046117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.046160] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.046203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.046246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.046288] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.046330] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.046339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.046380] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.046386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.046429] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.046519] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.046564] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.046608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.046651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.046698] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.046743] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.046789] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.046835] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.046879] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.046922] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.046967] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.047028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.047077] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.047120] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.062318] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.080785] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.080899] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.080988] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.081310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.081355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.081398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.081810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.081854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.081897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.081941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.081983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.082026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.082069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.082120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.082165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.082229] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.082273] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.082327] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.082377] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.082423] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.083078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.083130] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.083174] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 544.083213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 544.084384] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.085350] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.085397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.085650] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.085694] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.085736] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.085781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.085826] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.085869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.085912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.085954] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.085995] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.086004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.086046] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.086052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.086096] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.086138] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.086181] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.086224] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.086269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.086316] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.086361] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.086408] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.087204] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.087249] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.087292] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.087334] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.087402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.087759] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.087803] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.088301] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.088846] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.089137] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 544.089194] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.089234] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.089290] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.089782] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.090109] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.090154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.090197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.090239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.090284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.090326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.090369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.090412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.090849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.090892] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.090941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.090986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.091061] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.091103] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.092765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.092809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.092854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 544.093686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.093730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.094595] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 544.094639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 544.095808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 544.097913] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 544.099029] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.099231] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.099284] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.099687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.116241] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.116288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.116333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.116377] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.116419] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.116868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.116915] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.116958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.117001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.117043] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.117085] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.117094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.117136] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.117142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.117185] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.117228] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.117270] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.117313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.117355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.117400] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.118091] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.118137] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.118180] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.118224] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.118266] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.118309] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.118381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.118774] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.118819] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.132667] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.151198] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.151311] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.151400] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.152065] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.152111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.152155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.152198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.152241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.152284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.152326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.152369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.152412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.152820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.152872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.152917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.152979] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.153022] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.153077] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.153127] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.153175] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.153227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.153274] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.153318] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 544.153356] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 544.154551] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.154968] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.155014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.155059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.155103] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.155146] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.155190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.155233] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.155276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.155319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.155362] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.155403] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.155827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.155886] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.155893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.155937] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.155980] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.156024] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.156067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.156110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.156155] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.156198] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.156244] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.156287] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.156331] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.156375] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.156418] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.156808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.156863] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.156906] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.157057] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.157095] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.157391] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 544.158071] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.158113] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.158169] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.158411] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.159037] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.159082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.159125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.159168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.159211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.159255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.159298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.159342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.159385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.159428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.159857] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.159903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.159979] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.160023] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.162741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.162786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.162831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 544.163750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.163794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.164625] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 544.164670] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 544.165824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 544.167924] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 544.168950] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.169156] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.169208] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.169377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.186092] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.186138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.186183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.186226] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.186269] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.186312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.186356] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.186399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.186967] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.187009] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.187051] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.187061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.187102] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.187108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.187151] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.187193] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.187236] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.187279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.187321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.187366] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.187408] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.187961] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.188005] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.188048] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.188091] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.188133] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.188202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.188256] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.188299] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.202649] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.221184] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.221296] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.221385] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.221845] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.221891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.221935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.221978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.222021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.222064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.222106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.222149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.222191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.222234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.222281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.222325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.222386] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.222942] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.222998] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.223049] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.223096] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.223148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.223197] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.223239] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 544.223278] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 544.224466] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.224882] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.224926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.224971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.225014] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.225056] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.225100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.225143] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.225186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.225229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.225271] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.225312] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.225321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.225363] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.225368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.225411] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.226100] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.226144] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.226186] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.226228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.226274] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.226315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.226360] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.226403] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.226777] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.226820] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.226863] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.226931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.226985] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.227027] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.227177] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.227214] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.227874] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 544.228181] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.228222] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.228277] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.228791] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.229113] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.229157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.229200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.229243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.229285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.229328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.229370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.229413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.229861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.229905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.229953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.229997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.230347] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.230391] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.231962] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.232005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.232050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 544.232892] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 544.232937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 544.234002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 544.236096] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 544.237112] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.237304] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.237358] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.237759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.254316] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.254364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.254410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.254734] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.254776] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.254822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.254867] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.254910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.254953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.254995] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.255036] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.255046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.255088] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.255093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.255136] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.255179] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.255221] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.255264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.255306] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.255351] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.255393] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.256182] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.256225] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.256269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.256311] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.256354] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.256425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.256801] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.256844] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.270763] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.288744] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.288857] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.288946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.289267] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.289313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.289358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.289401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.289830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.289875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.289917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.289960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.290003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.290046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.290094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.290138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.290201] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.290243] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.290296] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.290345] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.290391] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.291002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.291054] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.291097] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:58 BXT-2 kernel: [ 544.291136] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:58 BXT-2 kernel: [ 544.292302] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.292835] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.292880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.292925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.292968] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.293010] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.293054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.293097] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.293140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.293183] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.293225] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.293267] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.293275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.293317] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.293323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.293366] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.293408] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.294090] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.294134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.294390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.294531] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.294574] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.294619] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.294663] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.294706] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.294749] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.294791] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.294861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.294914] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.294957] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.295113] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:58 BXT-2 kernel: [ 544.295150] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:58 BXT-2 kernel: [ 544.295940] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:58 BXT-2 kernel: [ 544.296249] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.296290] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:58 BXT-2 kernel: [ 544.296346] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:58 BXT-2 kernel: [ 544.296859] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.297178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.297222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:58 BXT-2 kernel: [ 544.297265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.297308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.297350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.297393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:58 BXT-2 kernel: [ 544.297746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:58 BXT-2 kernel: [ 544.297789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:58 BXT-2 kernel: [ 544.297831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:58 BXT-2 kernel: [ 544.297874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:58 BXT-2 kernel: [ 544.297923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:58 BXT-2 kernel: [ 544.297967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.298041] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:58 BXT-2 kernel: [ 544.298084] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.299838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.299883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:58 BXT-2 kernel: [ 544.299927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:58 BXT-2 kernel: [ 544.300879] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:58 BXT-2 kernel: [ 544.300924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:58 BXT-2 kernel: [ 544.301995] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:58 BXT-2 kernel: [ 544.304098] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:58 BXT-2 kernel: [ 544.305399] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.305646] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:58 BXT-2 kernel: [ 544.305700] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:58 BXT-2 kernel: [ 544.305871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.322665] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:58 BXT-2 kernel: [ 544.322712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:58 BXT-2 kernel: [ 544.322757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:58 BXT-2 kernel: [ 544.322800] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:58 BXT-2 kernel: [ 544.322842] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:58 BXT-2 kernel: [ 544.322886] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.322930] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:58 BXT-2 kernel: [ 544.322972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.323015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:58 BXT-2 kernel: [ 544.323058] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.323099] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:58 BXT-2 kernel: [ 544.323108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.323150] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:58 BXT-2 kernel: [ 544.323156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.323199] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:58 BXT-2 kernel: [ 544.323241] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:58 BXT-2 kernel: [ 544.323284] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:58 BXT-2 kernel: [ 544.323326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:58 BXT-2 kernel: [ 544.323368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:58 BXT-2 kernel: [ 544.323413] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:58 BXT-2 kernel: [ 544.324264] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:58 BXT-2 kernel: [ 544.324310] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:58 BXT-2 kernel: [ 544.324354] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:58 BXT-2 kernel: [ 544.324397] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.324663] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.324707] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:58 BXT-2 kernel: [ 544.324777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:58 BXT-2 kernel: [ 544.324831] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:58 BXT-2 kernel: [ 544.324874] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:58 BXT-2 kernel: [ 544.339021] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.356746] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.356860] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.356950] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.357280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.357325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.357368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.357410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.357900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.357944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.357987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.358030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.358073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.358116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.358166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.358211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.358275] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.358318] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.358372] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.358421] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.358987] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.359042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.359098] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.359143] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.359184] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.360360] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.360932] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.360977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.361023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.361067] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.361109] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.361153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.361197] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.361240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.361283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.361325] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.361367] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.361375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.361417] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.361996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.362056] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.362099] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.362142] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.362185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.362227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.362272] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.362314] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.362359] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.362402] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.362883] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.362926] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.362969] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.363038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.363093] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.363136] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.363298] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.363337] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.364023] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.364338] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.364378] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.364642] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.364906] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.365236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.365280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.365323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.365366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.365409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.365888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.365932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.365975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.366018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.366061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.366110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.366156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.366232] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.366275] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.368152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.368199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.368243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.370264] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.370313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.371776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.373513] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.374502] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.374686] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.374738] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.374908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.391747] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.391795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.391840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.391884] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.391926] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.391970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.392014] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.392057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.392100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.392142] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.392184] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.392193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.392235] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.392241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.392284] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.392327] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.392370] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.392412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.392957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.393003] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.393046] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.393091] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.393135] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.393179] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.393223] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.393266] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.393336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.393389] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.393433] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.408077] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.426661] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.426773] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.426862] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.427178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.427222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.427265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.427308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.427350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.427393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.427485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.427530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.427573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.427616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.427663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.427707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.427770] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.427812] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.427866] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.427915] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.427961] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.428013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.428062] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.428105] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.428144] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.428726] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.429142] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.429188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.429234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.429278] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.429321] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.429365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.429409] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.429495] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.429540] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.429585] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.429629] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.429640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.429684] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.429691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.429734] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.429777] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.429823] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.429866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.429908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.429953] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.429995] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.430040] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.430084] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.430128] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.430171] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.430214] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.430279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.430334] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.430377] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.430569] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.430608] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.430903] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.430958] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.431000] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.431057] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.431364] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.431696] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.431743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.431787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.431830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.431874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.431917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.431961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.432004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.432048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.432091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.432139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.432184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.432259] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.432302] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.433782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.433826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.433871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.434686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.434729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.435623] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.435667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.436805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.438925] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.440045] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.440268] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.440322] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.440824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.457186] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.457233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.457278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.457322] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.457364] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.457408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.457504] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.457549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.457592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.457634] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.457677] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.457686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.457728] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.457734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.457777] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.457822] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.457865] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.457908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.457951] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.457996] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.458038] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.458083] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.458127] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.458170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.458213] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.458256] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.458320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.458370] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.458413] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.473633] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.491695] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.491808] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.491895] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.492213] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.492256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.492299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.492342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.492385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.492427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.492506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.492556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.492604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.492650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.492699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.492745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.493037] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.493080] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.493134] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.493184] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.493231] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.493283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.493329] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.493373] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.493411] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.494661] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.495769] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.495814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.495860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.495903] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.495945] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.495989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.496032] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.496075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.496118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.496160] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.496202] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.496211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.496253] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.496258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.496301] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.496344] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.496387] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.496429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.496506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.496554] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.496600] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.496646] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.496692] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.496737] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.496783] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.496828] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.496896] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.497303] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.497347] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.497668] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.497707] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.497997] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.498051] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.498093] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.498149] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.498400] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.499007] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.499052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.499095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.499138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.499181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.499224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.499267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.499309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.499352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.499395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.499487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.499534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.499852] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.499897] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.501334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.501378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.501422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.502250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.502293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.503263] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.503311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.504617] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.506725] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.507817] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.508025] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.508078] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.508251] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.524953] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.525000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.525045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.525088] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.525130] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.525174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.525217] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.525260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.525303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.525345] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.525387] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.525396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.525536] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.525825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.525882] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.525926] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.525970] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.526013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.526055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.526101] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.526143] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.526189] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.526233] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.526277] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.526320] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.526363] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.526428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.526514] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.526559] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.541534] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.559799] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.559912] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.560002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.560326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.560371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.560414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.560505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.560550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.560599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.560644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.560687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.560733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.560777] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.560824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.560869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.560932] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.560975] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.561029] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.561079] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.561128] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.561181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.561228] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.561272] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.561311] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.561894] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.562322] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.562368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.562412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.562491] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.562537] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.562583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.562628] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.562672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.562718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.562761] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.562803] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.562813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.562857] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.562864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.562908] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.562951] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.562995] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.563037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.563080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.563125] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.563168] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.563214] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.563257] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.563300] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.563344] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.563387] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.563499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.563555] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.563600] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.563754] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.563793] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.564088] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.564143] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.564184] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.564241] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.564717] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.565041] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.565085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.565129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.565171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.565214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.565257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.565299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.565342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.565384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.565427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.565508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.565555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.565631] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.565675] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.567121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.567164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.567208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.567999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.568042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.568793] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.568837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.569877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.571478] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.572614] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.572813] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.572866] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.573034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.589800] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.589847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.589892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.589935] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.589978] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.590021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.590065] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.590108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.590151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.590193] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.590235] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.590244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.590285] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.590291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.590334] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.590377] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.590419] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.590524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.590572] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.590620] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.590663] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.590710] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.590755] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.590800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.591197] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.591240] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.591305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.591359] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.591402] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.606206] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.624710] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.624821] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.624908] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.625228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.625273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.625316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.625358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.625401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.625503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.625548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.625593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.625637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.625681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.625729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.625775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.625837] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.625880] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.625934] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.625984] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.626032] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.626085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.626133] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.626177] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.626216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.626800] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.627215] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.627260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.627304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.627348] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.627390] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.627467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.627514] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.627561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.627606] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.627650] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.627693] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.627704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.627747] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.627755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.627798] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.627843] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.627889] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.627932] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.627975] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.628021] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.628064] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.628109] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.628153] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.628197] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.628241] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.628285] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.628351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.628406] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.628514] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.628680] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.628719] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.629016] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.629073] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.629116] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.629174] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.629910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.630234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.630278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.630321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.630364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.630407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.630807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.630859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.630910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.630961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.631013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.631077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.631133] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.631225] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.631278] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.633177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.633222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.633267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.634055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.634099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.634872] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.634917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.635962] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.638052] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.639090] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.639299] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.639352] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.639730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.656232] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.656279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.656324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.656367] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.656409] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.656546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.656590] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.656633] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.656677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.656720] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.656762] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.656771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.656813] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.656820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.656863] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.656906] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.656949] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.656992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.657035] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.657080] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.657122] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.657167] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.657211] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.657254] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.657297] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.657340] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.657404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.657480] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.657523] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.672714] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.690897] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.691011] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.691099] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.691424] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.691847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.691892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.691935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.691977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.692021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.692063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.692106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.692148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.692191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.692242] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.692287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.692351] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.692393] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.692886] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.692938] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.692987] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.693041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.693090] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.693133] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.693172] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.694347] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.695059] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.695105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.695151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.695195] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.695237] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.695281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.695324] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.695367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.695410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.695824] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.695866] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.695876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.695918] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.695924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.695968] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.696011] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.696055] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.696098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.696141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.696187] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.696229] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.696275] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.696319] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.696362] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.696405] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.696820] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.696889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.696943] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.696988] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.697138] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.697175] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.697749] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.698100] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.698142] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.698200] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.699995] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.700321] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.700366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.700409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.700940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.700983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.701026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.701069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.701112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.701155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.701198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.701246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.701291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.701365] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.701409] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.703286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.703330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.703374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.704321] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.704368] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.705510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.707602] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.708651] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.708841] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.708894] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.709062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.725794] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.725841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.725886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.725929] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.725971] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.726015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.726058] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.726101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.726144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.726186] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.726228] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.726237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.726278] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.726284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.726327] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.726370] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.726413] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.727178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.727220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.727266] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.727308] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.727353] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.727396] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.727711] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.727757] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.727802] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.727871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.727924] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.727967] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.742336] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.759932] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.760044] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.760133] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.760491] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.760538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.760581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.760624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.760668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.760711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.760755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.760798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.760841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.760885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.760931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.760976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.761040] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.761083] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.761136] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.761186] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.761233] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.761285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.761331] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.761375] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.761413] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.761991] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.762423] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.762524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.762570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.762614] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.762656] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.762701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.762746] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.762789] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.762833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.762876] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.762918] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.762927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.762969] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.762975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.763018] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.763062] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.763105] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.763148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.763191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.763238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.763280] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.763325] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.763369] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.763412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.763486] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.763529] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.763594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.763648] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.763691] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.763875] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.763913] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.764203] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.764257] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.764299] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.764355] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.765138] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.765504] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.765732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.765776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.765819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.765862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.765905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.765948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.765990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.766033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.766076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.766124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.766169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.766243] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.766286] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.767917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.767963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.768007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.769022] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.769067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.770138] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.771532] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.772554] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.772746] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.772799] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.772968] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.789728] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.789775] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.789819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.789863] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.789905] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.789949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.789992] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.790035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.790078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.790120] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.790162] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.790171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.790213] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.790219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.790261] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.790304] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.790347] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.790389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.790431] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.790549] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.790591] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.790638] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.790681] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.790724] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.790767] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.790809] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.790872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.790923] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.790966] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.806122] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.823157] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.823270] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.823358] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.823748] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.823794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.823839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.823882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.823925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.823969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.824012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.824056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.824099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.824142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.824190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.824235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.824295] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.824338] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.824392] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.824478] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.824524] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.824576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.824623] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.824666] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.824705] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.825269] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.825775] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.825822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.825868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.825911] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.825953] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.825997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.826041] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.826083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.826127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.826169] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.826210] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.826219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.826261] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.826267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.826310] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.826352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.826395] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.826483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.826527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.826572] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.826614] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.826659] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.826703] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.826746] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.826789] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.826832] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.826898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.826950] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.826993] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.827149] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.827187] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.827497] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.827552] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.827592] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.827649] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.828415] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.829019] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.829064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.829107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.829150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.829193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.829236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.829278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.829321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.829363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.829406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.829495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.829543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.829619] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.829662] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.831088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.831133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.831177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.831976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.832021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.832891] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.832935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.833989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.836083] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.837081] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.837290] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.837343] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.837557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.854239] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.854286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.854333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.854378] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.854420] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.854792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.854841] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.854887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.854930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.854973] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.855014] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.855025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.855067] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.855074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.855117] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.855162] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.855205] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.855247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.855289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.855334] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.855375] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.855420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.856110] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.856155] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.856198] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.856240] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.856309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.856361] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.856404] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.870735] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.888956] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.889069] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.889156] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.889703] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.889749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.889792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.889835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.889878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.889921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.889964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.890006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.890049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.890092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.890139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.890183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.890245] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.890287] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.890340] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.890389] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.891152] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.891210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.891260] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.891303] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.891341] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.892529] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.892946] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.892989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.893034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.893079] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.893121] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.893165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.893208] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.893252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.893295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.893337] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.893379] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.893387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.893429] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.893989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.894050] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.894094] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.894136] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.894180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.894222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.894271] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.894312] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.894360] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.894403] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.894858] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.894901] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.894944] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.895015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.895069] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.895112] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.895264] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.895303] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.895948] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.896256] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.896298] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.896353] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.896870] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.897201] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.897245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.897289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.897332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.897376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.897419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.897802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.897845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.897888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.897931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.897981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.898026] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.898101] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.898145] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.899906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.899952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.899999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.901039] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.901087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.902159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.904287] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.905336] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.906026] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.906100] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.906308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.922448] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.922518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.922570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.922614] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.922657] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.922701] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.922745] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.922788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.922831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.922873] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.922915] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.922924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.922966] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.922972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.923015] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.923058] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.923100] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.923143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.923185] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.923230] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.923272] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.923317] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.923359] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.923402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.923493] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.923538] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.923605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.923659] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.923702] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.938900] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.955692] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.955804] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.955893] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.956213] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.956256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.956300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.956343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.956385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.956428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.956572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.956615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.956658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.956702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.956749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.956794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.956855] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.956898] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.956952] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.957002] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.957048] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.957101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.957148] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.957192] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 544.957230] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 544.957811] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.958246] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.958293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.958338] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.958382] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.958424] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.958513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.958559] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.958602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.958645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.958688] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.958730] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.958740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.958782] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.958788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.958832] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.958875] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.958918] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.958961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.959004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.959049] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.959092] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.959137] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.959181] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.959224] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.959267] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.959310] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.959377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.959431] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.959493] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.959647] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 544.959684] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 544.959974] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 544.960028] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.960068] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 544.960125] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 544.960922] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.961244] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.961287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 544.961331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.961373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.961416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.961552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 544.961595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 544.961639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 544.961682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 544.961726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 544.961774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 544.961819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.961894] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 544.961938] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.963628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.963674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.963719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 544.964560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.964604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 544.965344] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 544.965388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 544.966505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 544.968598] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 544.969657] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 544.969870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 544.969923] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 544.970092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.986800] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 544.986846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 544.986891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 544.986934] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 544.986976] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 544.987020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.987063] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 544.987106] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.987149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 544.987191] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.987233] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 544.987242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.987284] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 544.987290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.987333] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 544.987375] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 544.987418] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 544.987508] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 544.987552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 544.987597] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 544.987639] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 544.987684] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 544.987728] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 544.987772] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.987815] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.987858] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 544.987920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 544.987969] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 544.988013] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.003331] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.021909] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.022023] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.022111] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.022429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.022540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.022583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.022629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.022672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.022716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.022759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.022802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.022845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.022889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.022936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.022981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.023040] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.023083] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.023137] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.023187] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.023233] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.023285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.023332] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.023375] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 545.023414] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 545.023998] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.024403] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.024495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.024542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.024586] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.024628] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.024673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.024717] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.024760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.024804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.024919] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.024962] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.024971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.025013] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.025019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.025063] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.025106] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.025149] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.025192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.025235] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.025281] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.025323] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.025372] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.025415] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.025478] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.025522] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.025565] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.025629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.025682] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.025725] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.025878] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.025916] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.026206] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 545.026260] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.026302] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.026358] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.027021] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.027352] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.027396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.027501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.027546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.027588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.027632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.027675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.027718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.027762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.027807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.027855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.027900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.027975] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.028018] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.029572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.029617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.029662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 545.030428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.030637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.031371] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 545.031416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 545.032551] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 545.034492] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 545.035753] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.035946] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.035999] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.036172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.052855] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.052902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.052947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.052991] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.053033] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.053077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.053120] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.053162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.053205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.053247] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.053289] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.053298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.053339] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.053345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.053388] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.053431] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.053548] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.053591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.053641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.053687] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.053729] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.053775] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.053819] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.053863] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.053906] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.053950] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.054015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.054068] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.054111] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.069328] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.087798] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.087913] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.088002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.088326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.088371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.088414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.088508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.088553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.088602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.088648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.088691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.088736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.088780] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.088829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.088875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.088937] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.088981] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.089036] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.089086] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.089134] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.089187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.089235] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.089280] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 545.089320] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 545.089923] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.090924] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.090972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.091018] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.091061] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.091104] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.091148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.091192] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.091235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.091278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.091320] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.091362] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.091371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.091413] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.091472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.091520] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.091566] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.091611] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.091656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.091702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.091750] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.091795] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.091842] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.091886] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.091931] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.091974] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.092020] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.092086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.092142] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.092186] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.092961] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.093003] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.093299] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 545.093356] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.093397] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.093828] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.094099] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.094429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.094799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.094844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.094887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.094930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.094973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.095016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.095059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.095101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.095144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.095194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.095239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.095314] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.095357] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.097137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.097184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.097229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 545.098280] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 545.098328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 545.099560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 545.101678] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 545.102761] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.102956] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.103010] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.103178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.119906] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.119953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.119998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.120042] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.120084] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.120128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.120172] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.120215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.120258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.120301] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.120343] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.120351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.120394] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.120493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.120544] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.120590] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.120636] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.120682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.120725] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.120773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.120816] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.120864] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.120910] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.120956] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.121001] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.121045] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.121113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.121168] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.121212] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.136357] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.154737] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.154850] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.154938] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.155259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.155303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.155346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.155389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.155432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.155511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.155560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.155609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.155654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.155699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.155748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.156136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.156198] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.156241] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.156296] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.156347] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.156395] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.156676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.156725] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.156768] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 545.156808] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 545.157361] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.157860] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.157907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.157953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.157997] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.158039] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.158084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.158128] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.158171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.158214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.158256] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.158299] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.158307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.158349] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.158355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.158398] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.158481] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.158564] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.158607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.158651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.158697] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.158739] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.158786] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.158830] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.158873] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.158917] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.158960] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.159027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.159081] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.159124] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.159288] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.159327] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.159651] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 545.159709] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.159752] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.159809] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.160734] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.161065] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.161110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.161154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.161198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.161241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.161284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.161327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.161370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.161413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.161883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.161934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.161979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.162055] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.162099] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.163800] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.163846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.163890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 545.164931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.164976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.165757] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 545.165804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 545.166894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 545.168473] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 545.169433] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.169659] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.169712] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.169882] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.186629] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.186676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.186721] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.186765] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.186807] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.186851] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.186894] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.186936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.186980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.187022] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.187063] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.187072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.187114] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.187120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.187163] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.187206] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.187248] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.187290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.187332] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.187378] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.187420] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.187526] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.187571] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.187617] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.187660] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.187703] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.187771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.187825] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.187868] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.203115] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.220748] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.220861] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.220950] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.221273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.221317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.221360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.221403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.221504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.221551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.221595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.221640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.221683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.221727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.221774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.221819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.221881] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.221924] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.221979] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.222029] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.222077] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.222129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.222176] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.222219] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 545.222258] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 545.222843] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.223254] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.223300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.223345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.223388] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.223430] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.223516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.223562] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.223607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.223652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.223695] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.223739] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.223749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.223791] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.223798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.223841] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.223885] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.223929] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.223972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.224015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.224060] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.224103] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.224149] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.224193] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.224236] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.224280] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.224323] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.224386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.224469] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.224517] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.224670] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.224708] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.225002] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 545.225057] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.225098] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.225155] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.225405] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.225816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.225862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.225905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.225948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.225990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.226033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.226076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.226118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.226161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.226204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.226253] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.226297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.226372] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.226415] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.227890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.227934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.227978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 545.228800] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 545.228848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 545.230009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 545.232120] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 545.233277] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.233798] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.233854] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.234025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.250422] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.250490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.250536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.250580] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.250623] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.250667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.250710] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.250754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.250797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.250839] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.250881] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.250890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.250932] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.250938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.250981] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.251023] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.251066] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.251109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.251151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.251196] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.251238] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.251283] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.251326] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.251369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.251411] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.251827] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.252144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.252201] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.252245] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.266869] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.284725] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.284841] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.284932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.285264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.285309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.285352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.285395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.285495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.285542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.285590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.285636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.285681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.285727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.286194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.286243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.286304] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.286347] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.286401] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.286798] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.286846] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.286899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.286949] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.286992] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:30:59 BXT-2 kernel: [ 545.287031] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:30:59 BXT-2 kernel: [ 545.288205] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.288915] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.288961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.289007] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.289051] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.289094] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.289138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.289182] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.289225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.289268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.289310] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.289352] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.289361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.289402] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.289735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.289795] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.289839] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.289883] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.289926] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.289970] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.290016] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.290059] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.290104] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.290148] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.290192] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.290235] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.290278] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.290348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.290401] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.290897] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.291068] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:30:59 BXT-2 kernel: [ 545.291107] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:30:59 BXT-2 kernel: [ 545.291402] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:30:59 BXT-2 kernel: [ 545.292039] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.292081] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:30:59 BXT-2 kernel: [ 545.292138] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:30:59 BXT-2 kernel: [ 545.292742] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.293076] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.293121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:30:59 BXT-2 kernel: [ 545.293165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.293207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.293250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.293293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:30:59 BXT-2 kernel: [ 545.293336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:30:59 BXT-2 kernel: [ 545.293378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:30:59 BXT-2 kernel: [ 545.293421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:30:59 BXT-2 kernel: [ 545.293794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:30:59 BXT-2 kernel: [ 545.293846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:30:59 BXT-2 kernel: [ 545.293893] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.293970] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:30:59 BXT-2 kernel: [ 545.294013] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.295532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.295578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.295622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:30:59 BXT-2 kernel: [ 545.296406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.296797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:30:59 BXT-2 kernel: [ 545.297835] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:30:59 BXT-2 kernel: [ 545.297882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:30:59 BXT-2 kernel: [ 545.299188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:30:59 BXT-2 kernel: [ 545.301299] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:30:59 BXT-2 kernel: [ 545.302341] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.302571] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:30:59 BXT-2 kernel: [ 545.302625] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:30:59 BXT-2 kernel: [ 545.302798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.319493] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:30:59 BXT-2 kernel: [ 545.319540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:30:59 BXT-2 kernel: [ 545.319585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:30:59 BXT-2 kernel: [ 545.319629] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:30:59 BXT-2 kernel: [ 545.319671] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:30:59 BXT-2 kernel: [ 545.319715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.319758] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:30:59 BXT-2 kernel: [ 545.319801] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.319844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:30:59 BXT-2 kernel: [ 545.319886] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.319928] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:30:59 BXT-2 kernel: [ 545.319936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.319978] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:30:59 BXT-2 kernel: [ 545.319984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.320027] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:30:59 BXT-2 kernel: [ 545.320069] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:30:59 BXT-2 kernel: [ 545.320112] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:30:59 BXT-2 kernel: [ 545.320154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:30:59 BXT-2 kernel: [ 545.320196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:30:59 BXT-2 kernel: [ 545.320241] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:30:59 BXT-2 kernel: [ 545.320282] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:30:59 BXT-2 kernel: [ 545.320327] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:30:59 BXT-2 kernel: [ 545.320370] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:30:59 BXT-2 kernel: [ 545.320412] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.321028] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.321073] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:30:59 BXT-2 kernel: [ 545.321144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:30:59 BXT-2 kernel: [ 545.321198] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:30:59 BXT-2 kernel: [ 545.321241] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:30:59 BXT-2 kernel: [ 545.335917] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.353702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.353814] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.353903] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.354221] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.354265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.354308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.354351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.354394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.354913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.354957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.354999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.355042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.355085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.355134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.355179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.355241] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.355283] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.355335] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.355384] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.355431] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.355972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.356022] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.356065] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.356103] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.357306] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.358702] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.358747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.358793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.358836] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.358878] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.358922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.358966] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.359009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.359052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.359094] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.359136] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.359144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.359186] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.359192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.359235] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.359277] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.359320] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.359363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.359405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.360192] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.360235] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.360280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.360323] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.360367] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.360409] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.360723] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.360792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.360846] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.360889] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.361038] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.361076] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.361364] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.361418] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.361831] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.361889] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.362173] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.362637] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.362683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.362726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.362769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.362812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.362855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.362898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.362940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.362984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.363026] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.363074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.363118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.363192] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.363235] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.365191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.365236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.365280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.366136] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.366180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.367239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.369332] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.370309] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.370738] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.370792] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.370961] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.387608] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.387683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.387737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.387783] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.387826] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.387872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.387918] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.387961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.388004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.388047] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.388088] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.388097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.388139] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.388145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.388188] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.388230] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.388273] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.388316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.388359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.388404] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.389304] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.389351] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.389394] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.389630] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.389674] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.389717] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.389787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.389841] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.389883] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.403900] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.422436] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.422593] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.422682] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.423013] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.423058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.423101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.423144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.423187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.423230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.423273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.423315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.423358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.423401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.424023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.424069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.424133] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.424176] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.424229] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.424280] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.424326] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.424378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.424425] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.424925] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.424964] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.426134] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.426735] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.426781] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.426826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.426870] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.426913] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.426959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.427004] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.427047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.427091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.427135] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.427177] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.427186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.427233] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.427239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.427292] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.427343] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.427395] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.428284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.428339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.428392] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.428706] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.428752] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.428795] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.428839] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.428882] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.428924] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.428992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.429046] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.429089] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.429250] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.429288] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.430085] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.430396] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.430477] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.430535] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.430858] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.431181] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.431224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.431268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.431311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.431353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.431396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.431488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.431531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.431574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.431617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.431664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.431710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.431785] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.431828] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.433368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.433414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.433507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.434299] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.434343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.435182] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.435226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.436444] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.438578] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.439625] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.439817] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.439869] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.440039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.456776] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.456822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.456868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.456911] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.456953] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.456997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.457040] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.457083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.457126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.457168] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.457209] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.457218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.457259] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.457265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.457308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.457351] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.457393] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.458152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.458194] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.458241] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.458283] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.458327] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.458370] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.458413] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.458757] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.458801] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.458871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.458925] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.458968] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.473264] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.491769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.491884] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.491971] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.492300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.492344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.492388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.492431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.492533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.492578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.492623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.492668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.492713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.492756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.493130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.493175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.493237] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.493280] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.493333] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.493385] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.493432] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.493528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.493576] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.493619] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.493658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.494863] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.496060] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.496105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.496151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.496194] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.496236] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.496280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.496323] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.496366] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.496409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.496497] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.496540] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.496548] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.496590] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.496596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.496640] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.496683] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.496726] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.496769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.496812] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.496857] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.496900] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.496945] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.496988] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.497031] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.497075] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.497117] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.497180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.497233] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.497276] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.497425] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.497485] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.497776] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.497831] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.497873] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.497929] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.498861] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.499179] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.499225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.499268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.499311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.499355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.499398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.499481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.499525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.499568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.499611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.499659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.499706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.499780] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.499823] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.501566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.501611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.501655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.502406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.502492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.503420] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.503530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.504603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.506506] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.507588] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.507797] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.507850] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.508020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.524756] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.524803] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.524847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.524891] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.524933] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.524977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.525020] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.525062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.525105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.525148] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.525190] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.525198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.525240] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.525246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.525289] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.525331] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.525374] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.525416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.526215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.526262] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.526304] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.526349] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.526393] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.526742] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.526785] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.526828] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.526898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.526952] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.527380] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.541155] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.559781] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.559896] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.559987] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.560316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.560361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.560405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.560500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.560544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.560589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.560632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.560675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.560719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.560762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.560811] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.560856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.560920] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.560964] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.561018] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.561068] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.561114] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.561167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.561214] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.561257] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.561296] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.561916] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.562841] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.562887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.562934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.562978] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.563020] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.563064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.563108] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.563151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.563195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.563237] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.563279] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.563288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.563329] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.563335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.563378] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.563421] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.563512] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.563555] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.563599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.563645] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.563687] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.563733] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.563776] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.563820] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.563863] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.563906] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.563972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.564026] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.564069] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.564244] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.564282] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.564611] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.564665] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.564707] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.564764] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.565019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.565341] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.565385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.565428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.565499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.565542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.565586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.565629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.565673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.565716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.565759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.565807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.565852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.565926] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.565970] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.568038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.568084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.568129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.569301] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.569348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.570558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.572682] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.573769] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.573988] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.574041] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.574214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.590903] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.590950] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.590995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.591039] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.591080] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.591124] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.591167] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.591212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.591255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.591297] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.591339] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.591347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.591389] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.591395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.591506] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.591553] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.591600] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.591645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.591690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.591737] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.591782] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.591828] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.591879] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.591924] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.591968] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.592010] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.592075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.592125] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.592168] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.607375] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.625802] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.625916] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.626004] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.626322] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.626366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.626409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.626519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.626562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.626605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.626648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.626692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.626735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.626779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.626826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.626871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.626936] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.626979] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.627032] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.627082] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.627130] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.627182] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.627229] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.627273] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.627312] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.627910] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.628877] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.628924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.628970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.629013] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.629055] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.629099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.629142] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.629185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.629228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.629270] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.629312] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.629321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.629363] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.629369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.629412] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.629509] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.629553] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.629596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.629638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.629684] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.629726] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.629771] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.629815] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.629858] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.629902] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.629945] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.630008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.630062] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.630105] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.630256] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.630294] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.630607] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.630661] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.630703] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.630760] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.631614] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.631936] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.631981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.632024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.632067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.632110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.632152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.632195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.632238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.632280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.632323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.632370] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.632430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.632539] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.632582] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.634346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.634391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.634473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.635253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.635296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.636080] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.636125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.637189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.639283] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.640257] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.640645] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.640699] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.640867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.657399] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.657468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.657514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.657557] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.657600] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.657643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.657687] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.657729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.657772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.657815] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.657856] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.657865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.657907] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.657913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.657956] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.657998] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.658041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.658083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.658125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.658169] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.658211] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.658256] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.658298] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.658341] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.658384] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.658426] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.659554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.659610] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.659653] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.673848] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.691717] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.691831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.691920] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.692250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.692294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.692337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.692380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.692422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.692925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.692968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.693011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.693054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.693097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.693147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.693191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.693252] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.693295] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.693349] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.693398] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.693973] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.694027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.694078] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.694122] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.694160] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.695332] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.695886] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.695932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.695978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.696022] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.696064] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.696108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.696153] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.696195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.696238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.696280] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.696322] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.696331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.696374] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.696379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.696423] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.697087] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.697131] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.697174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.697216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.697261] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.697304] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.697349] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.697392] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.697818] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.697861] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.697904] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.697973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.698028] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.698071] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.698236] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.698274] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.698989] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.699306] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.699347] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.699403] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.700187] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.700693] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.700740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.700784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.700827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.700869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.700913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.700956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.700998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.701041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.701084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.701133] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.701178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.701253] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.701296] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.703563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.703609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.703654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.704417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.704727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.705589] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.705634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.706803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.708901] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.709915] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.710107] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.710159] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.710329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.727087] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.727134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.727180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.727224] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.727266] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.727310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.727354] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.727397] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.727538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.727582] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.727623] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.727633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.727676] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.727682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.727726] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.727769] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.727813] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.727856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.727898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.727945] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.727988] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.728033] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.728077] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.728120] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.728163] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.728206] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.728280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.728333] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.728376] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.743523] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.761798] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.761909] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.761997] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.762323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.762367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.762410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.762809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.762852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.762896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.762939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.762983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.763028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.763072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.763121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.763166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.763228] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.763270] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.763324] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.763374] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.763420] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.764067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.764118] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.764161] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.764199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.765367] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.765892] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.765937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.765982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.766026] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.766068] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.766111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.766160] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.766203] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.766246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.766288] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.766330] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.766339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.766381] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.766387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.766430] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.767075] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.767118] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.767161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.767204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.767250] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.767291] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.767336] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.767379] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.767423] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.767853] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.767896] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.767966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.768020] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.768062] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.768214] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.768252] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.768871] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.769180] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.769221] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.769276] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.769800] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.770127] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.770171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.770215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.770257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.770300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.770342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.770385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.770428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.770865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.770909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.770957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.771002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.771076] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.771119] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.773131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.773178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.773223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.774096] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.774143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.775286] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.776521] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.777601] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.777807] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.777860] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.778029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.794785] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.794832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.794877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.794920] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.794962] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.795006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.795049] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.795092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.795135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.795177] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.795219] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.795228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.795270] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.795276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.795319] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.795361] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.795404] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.796189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.796232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.796277] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.796319] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.796364] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.796407] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.796727] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.796770] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.796813] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.796880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.796934] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.796977] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.811195] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.828782] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.828896] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.828986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.829312] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.829356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.829399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.829496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.829539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.829584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.829627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.829671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.829715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.829758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.829807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.829853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.829915] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.829958] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.830012] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.830061] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.830109] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.830162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.830208] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.830252] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.830291] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.830910] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.831861] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.831907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.831953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.831997] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.832039] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.832084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.832127] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.832170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.832213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.832255] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.832297] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.832306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.832348] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.832354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.832397] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.832541] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.832585] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.832627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.832670] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.832716] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.832759] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.832807] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.832977] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.833020] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.833064] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.833106] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.833179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.833234] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.833277] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.833427] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.833490] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.833780] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.833835] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.833875] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.833932] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.834188] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.834540] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.834585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.834628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.834671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.834713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.834756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.834800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.834842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.834885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.834928] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.834976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.835021] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.835097] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.835140] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.838171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.838217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.838261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.839215] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.839262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.840425] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.842497] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.843543] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.843729] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.843783] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.843954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.860731] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.860777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.860823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.860866] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.860908] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.860952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.860996] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.861038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.861081] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.861124] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.861165] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.861174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.861217] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.861223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.861266] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.861309] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.861353] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.861395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.861495] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.861542] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.861586] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.861640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.861691] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.861743] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.861794] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.861845] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.861951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.862024] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.862077] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.877104] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.894767] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.894880] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.894969] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.895285] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.895328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.895374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.895416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.895518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.895561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.895606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.895651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.895694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.895738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.895784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.895829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.895888] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.895931] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.895985] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.896035] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.896081] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.896133] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.896180] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.896224] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.896263] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.896849] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.897265] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.897311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.897357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.897400] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.897498] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.897544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.897589] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.897632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.897676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.897718] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.897761] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.897770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.897813] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.897819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.897863] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.897905] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.897949] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.897992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.898034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.898079] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.898122] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.898167] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.898211] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.898254] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.898298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.898340] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.898407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.898479] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.898523] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.898681] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.898719] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.899009] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.899063] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.899105] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.899162] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.899846] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.900175] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.900219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.900262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.900305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.900348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.900391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.900507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.900550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.900594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.900637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.900686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.900731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.900805] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.900849] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.902379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.902425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.902616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.903751] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.903798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.905319] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.907439] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.908563] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.908772] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.908825] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.908994] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.925728] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.925775] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.925820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.925864] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.925906] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.925950] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.925994] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.926037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.926080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.926123] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.926164] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.926174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.926216] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.926221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.926264] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.926307] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.926350] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.926392] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.926537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.926582] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.926624] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.926670] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.926714] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.926757] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.926800] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.926844] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.926909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.926960] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.927004] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.942168] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.959755] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.959871] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.959960] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.960285] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.960330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.960373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.960416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.960797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.960841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.960884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.960927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.960969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.961012] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.961063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.961108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.961171] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.961213] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.961267] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.961316] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.961362] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.961414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.961875] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.961919] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 545.961958] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 545.963129] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.963899] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.963945] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.963990] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.964034] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.964076] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.964120] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.964164] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.964206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.964250] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.964292] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.964334] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.964342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.964384] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.964390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.964837] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.964883] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.964926] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.964969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.965011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.965056] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.965098] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.965144] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.965187] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.965230] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.965273] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.965316] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.965383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.965878] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.965924] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.966078] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 545.966115] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 545.966407] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 545.967064] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.967106] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 545.967164] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 545.967766] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.968103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.968147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 545.969003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.969047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.969091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.969134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 545.969178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 545.969221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 545.969264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 545.969309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 545.969360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 545.969405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.969803] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 545.969847] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.971305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.971350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.971394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 545.972364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.972406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 545.973329] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 545.973375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 545.974653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 545.976757] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 545.977897] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 545.978105] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 545.978158] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 545.978327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.995069] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 545.995116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 545.995162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 545.995206] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 545.995248] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 545.995292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.995336] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 545.995380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.995423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 545.995934] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.995976] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 545.995986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.996028] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 545.996034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.996077] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 545.996119] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 545.996162] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 545.996204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 545.996246] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 545.996292] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 545.996334] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 545.996379] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 545.996422] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 545.997096] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.997145] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.997189] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 545.997270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 545.997327] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 545.997371] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.011519] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.029718] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.029831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.029919] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.030239] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.030283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.030327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.030370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.030412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.030907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.030951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.030994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.031037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.031080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.031130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.031174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.031238] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.031280] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.031334] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.031384] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.031430] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.032025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.032077] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.032120] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 546.032159] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 546.033938] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.034390] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.034657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.034704] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.034748] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.034790] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.034835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.034880] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.034922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.034966] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.035008] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.035050] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.035059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.035100] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.035106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.035149] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.035192] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.035234] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.035277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.035319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.035364] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.035406] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.036296] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.036350] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.036402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.036721] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.036765] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.036835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.036892] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.036942] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.037165] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.037216] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.037927] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 546.038242] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.038283] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.038339] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.038857] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.039186] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.039231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.039276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.039319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.039361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.039404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.039845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.039888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.039931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.039974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.040024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.040069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.040144] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.040187] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.041835] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.041880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.041926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 546.042743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.042786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.043553] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 546.043597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 546.044646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 546.046738] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 546.047775] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.047971] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.048023] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.048192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.064917] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.064964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.065009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.065052] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.065094] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.065138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.065181] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.065224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.065267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.065309] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.065351] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.065360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.065401] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.065450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.065494] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.065537] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.065582] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.065624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.065667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.065712] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.065755] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.065800] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.065843] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.065887] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.065929] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.065972] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.066036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.066085] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.066129] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.081383] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.099904] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.100017] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.100107] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.100436] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.100698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.100742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.100786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.100829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.100873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.100916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.100959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.101003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.101046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.101095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.101140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.101201] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.101244] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.101298] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.101348] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.101394] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.101557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.101605] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.101648] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 546.101687] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 546.102245] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.102784] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.102831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.102876] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.102920] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.102962] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.103007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.103050] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.103093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.103136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.103178] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.103220] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.103228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.103270] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.103276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.103319] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.103362] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.103405] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.103648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.103691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.103738] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.103780] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.103825] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.103869] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.103912] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.103955] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.103999] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.104067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.104121] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.104164] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.104324] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.104362] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.104804] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 546.105288] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.105329] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.105385] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.105951] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.106284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.106328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.106372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.106415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.106889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.106933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.106975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.107018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.107061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.107104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.107154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.107199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.107274] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.107317] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.110587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.110633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.110677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 546.111427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.111744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.112591] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 546.112636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 546.113893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 546.115991] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 546.117012] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.117187] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.117239] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.117408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.134141] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.134189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.134234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.134277] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.134320] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.134364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.134407] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.134882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.134926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.134969] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.135010] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.135020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.135061] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.135067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.135111] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.135153] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.135196] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.135239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.135281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.135327] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.135370] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.135415] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.136125] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.136170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.136213] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.136256] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.136326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.136381] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.136424] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.150637] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.168821] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.168934] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.169022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.169343] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.169387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.169430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.169511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.169556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.169602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.169647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.169692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.169735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.169779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.169826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.169871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.169932] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.169974] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.170028] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.170077] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.170123] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.170175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.170224] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.170268] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 546.170307] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 546.171500] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.171920] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.171964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.172009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.172053] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.172095] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.172139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.172182] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.172225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.172268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.172310] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.172352] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.172361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.172402] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.172458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.172503] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.172547] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.172589] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.172632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.172675] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.172721] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.172763] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.172809] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.172852] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.172896] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.172939] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.172982] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.173044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.173098] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.173141] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.173293] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.173330] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.173645] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 546.173701] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.173742] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.173799] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.174244] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.174638] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.174685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.174729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.174771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.174814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.174858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.174901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.174944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.174986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.175029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.175077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.175121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.175195] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.175238] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.176901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.176946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.176990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 546.177977] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 546.178022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 546.179184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 546.181283] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 546.182293] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.182707] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.182762] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.182931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.199493] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.199540] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.199586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.199630] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.199673] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.199717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.199760] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.199803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.199846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.199889] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.199930] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.199939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.199980] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.199986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.200029] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.200072] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.200115] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.200157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.200199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.200244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.200286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.200330] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.200373] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.200416] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.201389] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.201433] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.201646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.201700] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.201742] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.215856] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.233765] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.233881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.233969] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.234288] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.234332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.234376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.234418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.234528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.234572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.234615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.234658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.234701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.234745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.234792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.234837] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.234905] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.234947] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.235001] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.235051] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.235097] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.235150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.235196] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.235239] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 546.235278] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 546.235860] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.236296] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.236340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.236385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.236430] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.236515] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.236561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.236604] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.236648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.236692] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.236734] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.236777] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.236786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.236829] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.236835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.236879] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.236922] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.236965] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.237007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.237050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.237095] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.237138] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.237183] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.237227] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.237270] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.237313] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.237356] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.237420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.237495] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.237539] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.237693] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.237730] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.238020] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 546.238073] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.238116] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.238172] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.239089] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.239411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.239511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.239555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.239599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.239642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.239685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.239729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.239772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.239815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.239858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.239906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.239951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.240025] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.240069] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.241803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.241847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.241891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 546.242723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.242767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.243598] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 546.243642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 546.244803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 546.246919] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 546.248024] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.248273] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.248337] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.248903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.265139] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.265186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.265232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.265275] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.265317] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.265361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.265404] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.265512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.265556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.265600] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.265643] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.265653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.265694] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.265702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.265745] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.265788] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.265830] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.265873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.265916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.265961] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.266004] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.266049] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.266093] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.266136] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.266180] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.266223] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.266288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.266339] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.266382] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.281600] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.299705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.299818] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.299906] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.300228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.300272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.300315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.300358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.300400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.300493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.300538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.300583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.300628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.300671] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.300719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.300764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.300822] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.300864] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.300917] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.300966] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.301013] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.301066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.301112] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.301155] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:00 BXT-2 kernel: [ 546.301194] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:00 BXT-2 kernel: [ 546.301783] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.302195] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.302240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.302285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.302329] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.302371] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.302415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.302505] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.302549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.302592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.302634] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.302677] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.302687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.302731] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.302737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.302780] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.302823] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.302866] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.302909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.302952] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.302997] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.303039] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.303084] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.303128] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.303171] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.303214] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.303257] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.303321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.303374] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.303417] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.303633] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:00 BXT-2 kernel: [ 546.303671] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:00 BXT-2 kernel: [ 546.303960] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:00 BXT-2 kernel: [ 546.304015] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.304055] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:00 BXT-2 kernel: [ 546.304111] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:00 BXT-2 kernel: [ 546.304837] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.305158] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.305202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:00 BXT-2 kernel: [ 546.305245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.305287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.305330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.305373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:00 BXT-2 kernel: [ 546.305416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:00 BXT-2 kernel: [ 546.305515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:00 BXT-2 kernel: [ 546.305559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:00 BXT-2 kernel: [ 546.305604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:00 BXT-2 kernel: [ 546.305653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:00 BXT-2 kernel: [ 546.305951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.306026] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:00 BXT-2 kernel: [ 546.306070] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.307694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.307739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.307783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:00 BXT-2 kernel: [ 546.308720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.308764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:00 BXT-2 kernel: [ 546.310167] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:00 BXT-2 kernel: [ 546.310402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:00 BXT-2 kernel: [ 546.311738] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:00 BXT-2 kernel: [ 546.313834] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:00 BXT-2 kernel: [ 546.314877] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.315072] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:00 BXT-2 kernel: [ 546.315125] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:00 BXT-2 kernel: [ 546.315294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.332030] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:00 BXT-2 kernel: [ 546.332076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:00 BXT-2 kernel: [ 546.332121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:00 BXT-2 kernel: [ 546.332164] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:00 BXT-2 kernel: [ 546.332206] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:00 BXT-2 kernel: [ 546.332250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.332293] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:00 BXT-2 kernel: [ 546.332336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.332379] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:00 BXT-2 kernel: [ 546.332421] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.332946] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:00 BXT-2 kernel: [ 546.332956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.332998] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:00 BXT-2 kernel: [ 546.333004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.333047] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:00 BXT-2 kernel: [ 546.333090] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:00 BXT-2 kernel: [ 546.333133] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:00 BXT-2 kernel: [ 546.333175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:00 BXT-2 kernel: [ 546.333217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:00 BXT-2 kernel: [ 546.333262] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:00 BXT-2 kernel: [ 546.333304] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:00 BXT-2 kernel: [ 546.333349] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:00 BXT-2 kernel: [ 546.333392] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:00 BXT-2 kernel: [ 546.333970] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.334014] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.334057] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:00 BXT-2 kernel: [ 546.334129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:00 BXT-2 kernel: [ 546.334183] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:00 BXT-2 kernel: [ 546.334226] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:00 BXT-2 kernel: [ 546.348570] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.366701] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.366813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.366901] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.367217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.367261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.367304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.367346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.367389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.367432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.367542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.367585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.367628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.367672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.367720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.367765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.367824] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.367867] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.367921] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.367970] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.368017] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.368069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.368116] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.368160] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.368198] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.368789] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.369217] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.369263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.369309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.369353] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.369396] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.369482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.369528] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.369571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.369615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.369657] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.369700] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.369709] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.369752] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.369758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.369802] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.369845] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.369888] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.369931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.369974] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.370019] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.370061] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.370106] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.370150] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.370193] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.370237] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.370280] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.370346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.370399] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.370506] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.370665] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.370703] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.370995] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.371049] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.371089] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.371145] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.371908] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.372233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.372277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.372320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.372362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.372405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.372710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.372753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.372796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.372839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.372882] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.372929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.372974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.373048] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.373091] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.374709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.374753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.374797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.375702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.375745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.376670] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.376714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.377880] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.379979] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.380990] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.381175] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.381228] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.381396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.398146] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.398194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.398240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.398284] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.398326] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.398370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.398414] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.399126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.399171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.399213] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.399255] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.399264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.399306] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.399312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.399355] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.399398] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.400161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.400205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.400247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.400294] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.400336] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.400382] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.400425] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.401037] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.401082] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.401125] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.401195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.401250] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.401292] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.414595] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.432757] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.432897] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.433015] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.433378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.433434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.433833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.433883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.433926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.433969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.434012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.434055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.434101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.434144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.434196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.434241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.434312] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.434356] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.434410] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.434506] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.434554] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.434606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.434657] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.434700] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.434739] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.435286] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.435750] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.435797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.435843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.435887] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.435930] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.435975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.436019] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.436062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.436106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.436149] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.436191] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.436201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.436242] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.436248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.436292] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.436335] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.436379] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.436421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.436515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.436561] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.436604] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.436649] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.436693] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.436736] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.436780] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.436822] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.436888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.436942] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.436985] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.437142] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.437180] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.437494] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.437549] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.437592] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.437649] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.437915] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.438246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.438291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.438333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.438376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.438419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.438507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.438551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.438594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.438636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.438679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.438727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.438772] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.438849] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.438893] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.441020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.441066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.441110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.442007] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.442052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.443105] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.445206] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.446201] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.446407] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.446730] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.446900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.463348] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.463395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.463681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.463725] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.463768] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.463813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.463859] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.463902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.463945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.463987] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.464029] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.464038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.464080] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.464086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.464128] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.464171] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.464214] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.464256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.464298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.464344] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.464385] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.464430] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.465271] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.465315] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.465358] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.465401] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.465700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.465757] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.465800] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.479796] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.497794] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.497906] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.497995] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.498314] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.498358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.498401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.498789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.498832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.498874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.498917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.498960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.499003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.499045] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.499094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.499139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.499200] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.499242] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.499295] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.499344] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.499390] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.500024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.500075] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.500118] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.500157] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.501325] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.501859] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.501904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.501949] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.501993] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.502034] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.502078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.502122] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.502164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.502207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.502249] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.502291] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.502300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.502341] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.502347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.502390] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.502433] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.503148] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.503192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.503234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.503279] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.503321] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.503366] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.503410] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.503825] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.503868] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.503911] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.503982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.504036] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.504082] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.504236] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.504274] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.504988] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.505308] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.505349] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.505405] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.505932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.506257] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.506301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.506344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.506387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.506429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.506794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.506837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.506879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.506922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.506965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.507014] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.507058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.507133] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.507176] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.508876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.508920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.508964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.509875] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.509919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.511016] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.513120] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.514185] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.514380] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.514433] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.514875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.531361] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.531407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.531715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.531759] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.531801] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.531846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.531893] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.531936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.531980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.532026] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.532070] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.532081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.532129] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.532135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.532181] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.532226] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.532270] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.532313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.532356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.532401] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.533212] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.533260] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.533304] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.533347] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.533390] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.533727] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.533799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.533855] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.533897] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.547768] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.566274] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.566387] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.566539] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.566873] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.566917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.566961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.567003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.567046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.567089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.567132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.567174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.567217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.567260] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.567306] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.567351] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.567412] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.567498] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.567554] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.567604] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.567653] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.567705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.567753] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.567796] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.567835] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.568390] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.568854] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.568900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.568945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.568989] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.569031] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.569076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.569119] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.569162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.569205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.569247] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.569289] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.569298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.569340] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.569346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.569389] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.569431] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.569513] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.569556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.569598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.569643] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.569684] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.569729] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.569772] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.569815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.569858] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.569900] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.569968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.570022] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.570065] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.570229] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.570266] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.570582] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.570636] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.570677] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.570733] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.571597] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.571926] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.571970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.572014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.572056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.572099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.572142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.572185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.572228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.572270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.572314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.572363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.572409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.572860] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.572904] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.576997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.577042] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.577086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.577942] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.577987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.579030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.580491] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.581486] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.581689] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.581742] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.581911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.598683] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.598729] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.598774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.598818] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.598860] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.598904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.598947] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.598990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.599033] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.599075] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.599117] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.599126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.599168] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.599174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.599217] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.599260] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.599302] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.599345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.599387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.599432] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.600285] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.600331] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.600374] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.600417] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.600680] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.600723] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.600793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.600848] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.600890] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.615086] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.632716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.632861] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.632951] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.633840] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.633889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.633933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.633976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.634020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.634063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.634106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.634148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.634191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.634234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.634282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.634327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.634388] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.635165] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.635221] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.635275] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.635322] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.635375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.635424] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.635755] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.635794] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.636364] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.637015] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.637061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.637106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.637150] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.637192] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.637236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.637279] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.637322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.637365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.637407] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.637912] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.637922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.637967] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.637973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.638017] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.638061] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.638105] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.638148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.638190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.638237] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.638279] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.638329] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.638372] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.638414] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.639025] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.639068] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.639138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.639192] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.639234] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.639386] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.639424] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.640033] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.640090] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.640130] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.640186] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.640710] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.641031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.641075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.641120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.641164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.641207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.641250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.641292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.641335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.641377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.641420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.641920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.641965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.642040] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.642083] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.643881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.643926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.643970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.644896] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.644940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.645989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.647490] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.648529] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.648715] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.648768] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.648936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.665744] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.665791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.665836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.665880] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.665922] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.665966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.666010] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.666053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.666096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.666138] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.666180] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.666189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.666231] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.666237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.666280] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.666323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.666365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.666408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.667243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.667290] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.667332] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.667377] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.667421] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.667771] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.667814] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.667857] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.667926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.667979] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.668022] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.682187] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.699760] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.699874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.699962] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.700281] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.700325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.700368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.700410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.700950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.700994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.701037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.701080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.701123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.701165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.701214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.701259] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.701321] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.701364] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.701417] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.701930] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.701977] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.702030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.702079] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.702121] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.702160] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.703329] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.703944] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.703990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.704036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.704080] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.704122] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.704166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.704210] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.704253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.704297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.704339] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.704380] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.704389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.704431] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.705156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.705217] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.705262] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.705305] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.705348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.705390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.705792] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.705836] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.705882] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.705925] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.705969] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.706012] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.706056] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.706127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.706180] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.706223] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.706376] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.706414] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.707245] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.707304] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.707344] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.707401] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.707977] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.708298] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.708342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.708385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.708428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.708768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.708812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.708855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.708897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.708940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.708983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.709031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.709076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.709150] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.709193] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.710941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.710986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.711031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.712322] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.712370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.713445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.715656] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.716726] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.716930] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.716984] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.717156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.733870] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.733917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.733962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.734006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.734048] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.734092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.734134] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.734177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.734220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.734263] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.734304] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.734313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.734355] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.734361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.734404] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.734536] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.734578] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.734623] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.734666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.734712] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.734755] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.734800] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.734843] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.734887] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.734930] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.734973] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.735036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.735088] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.735131] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.750409] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.768803] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.768916] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.769005] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.769336] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.769381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.769424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.769512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.769556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.769601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.769644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.769687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.769730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.769774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.769823] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.769867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.769931] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.769974] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.770028] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.770078] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.770126] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.770178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.770225] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.770269] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.770308] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.770886] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.771298] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.771343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.771389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.771432] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.771554] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.771599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.771643] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.771687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.771730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.771774] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.771816] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.771826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.771867] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.771874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.771917] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.771962] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.772005] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.772048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.772091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.772136] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.772178] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.772223] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.772267] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.772310] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.772353] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.772395] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.772481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.772534] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.772577] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.772752] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.772790] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.773080] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.773133] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.773175] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.773232] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.774555] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.774880] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.774924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.774967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.775010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.775053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.775096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.775139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.775181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.775224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.775267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.775315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.775359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.775434] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.775644] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.777766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.777812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.777856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.778637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.778680] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.779451] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.779612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.780916] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.782480] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.783488] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.783671] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.783724] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.783892] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.800634] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.800681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.800726] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.800770] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.800812] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.800855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.800898] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.800941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.800984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.801027] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.801068] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.801077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.801119] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.801125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.801168] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.801211] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.801254] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.801296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.801338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.801382] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.801425] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.801544] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.801590] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.801635] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.801679] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.801723] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.801787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.801837] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.801882] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.817067] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.834771] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.834884] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.834973] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.835300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.835345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.835388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.835431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.835523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.835572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.835618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.835665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.835712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.835756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.835804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.835850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.835911] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.835954] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.836008] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.836057] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.836104] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.836155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.836203] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.836247] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.836287] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.836873] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.837303] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.837349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.837395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.837484] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.837530] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.837577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.837622] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.837665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.837708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.837750] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.837793] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.837802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.837845] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.837852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.837895] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.837938] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.837982] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.838025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.838067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.838113] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.838155] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.838202] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.838245] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.838289] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.838334] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.838379] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.838507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.838562] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.838605] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.838764] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.838801] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.839092] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.839146] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.839186] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.839243] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.840018] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.840354] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.840400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.840740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.840784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.840827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.840870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.840912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.840955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.840998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.841040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.841091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.841136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.841212] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.841255] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.843052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.843097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.843142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.844602] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.844652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.845934] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.847517] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.848520] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.848720] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.848773] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.848942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.865675] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.865722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.865767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.865811] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.865852] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.865896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.865939] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.865982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.866026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.866068] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.866110] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.866118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.866160] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.866166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.866209] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.866252] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.866294] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.866337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.866379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.866424] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.866517] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.866564] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.866609] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.866655] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.866705] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.866750] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.866812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.866861] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.866907] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.882218] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.899703] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.899815] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.899904] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.900226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.900269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.900313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.900355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.900398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.900481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.900528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.900578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.900623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.900669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.900717] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.900763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.900825] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.900868] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.900922] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.900973] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.901021] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.901074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.901122] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.901166] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.901206] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.901820] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.902781] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.902828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.902873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.902917] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.902959] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.903004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.903047] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.903090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.903133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.903175] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.903217] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.903226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.903268] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.903273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.903316] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.903359] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.903402] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.903565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.903608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.903654] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.903697] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.903743] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.903786] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.903830] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.903873] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.903917] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.903984] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.904038] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.904082] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.905589] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.905629] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.905918] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.905972] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.906012] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.906067] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.906367] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.906702] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.906747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.906792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.906835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.906878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.906922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.906969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.907014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.907059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.907104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.907155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.907202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.907279] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.907323] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.908887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.908932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.908976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.909779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.909822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.910558] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.910604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.911649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.913740] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.914743] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.914959] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.915012] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.915181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.931866] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.931912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.931957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.932000] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.932043] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.932086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.932131] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.932174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.932217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.932259] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.932300] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.932310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.932352] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.932358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.932400] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.932505] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.932554] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.932600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.932643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.932690] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.932735] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.932780] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.932824] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.932868] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.932911] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.932954] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.933019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.933072] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.933116] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.948333] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.966695] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.966808] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.966895] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.967214] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.967258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.967301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.967344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.967387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.967430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.967538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.967586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.967630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.967675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.967723] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.967769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.967830] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.967873] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.967927] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.967978] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.968026] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.968079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.968126] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.968170] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 546.968209] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 546.968795] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.969223] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.969268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.969313] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.969357] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.969399] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.969488] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.969537] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.969581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.969625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.969671] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.969715] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.969724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.969767] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.969774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.969818] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.969862] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.969906] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.969949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.969992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.970037] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.970080] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.970125] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.970169] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.970213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.970256] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.970299] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.970362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.970416] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.970531] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.970687] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 546.970725] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 546.971025] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 546.971083] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.971126] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 546.971184] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 546.971874] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.972199] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.972243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 546.972287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.972330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.972373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.972415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 546.972796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 546.972840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 546.972884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 546.972929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 546.972979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 546.973027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.973105] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 546.973149] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.974848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.974895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 546.974940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 546.976523] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 546.976571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 546.977628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 546.979505] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 546.980540] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 546.980748] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 546.980801] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 546.980971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.997713] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 546.997760] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 546.997805] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 546.997849] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 546.997891] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 546.997935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.997978] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 546.998021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.998064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 546.998106] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.998148] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 546.998157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.998198] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 546.998204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.998247] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 546.998290] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 546.998333] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 546.998375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 546.998417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 546.998506] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 546.998549] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 546.998598] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 546.998642] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 546.998685] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.998729] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.998772] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 546.998839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 546.998893] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 546.998937] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.014179] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.031711] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.031824] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.031914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.032235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.032281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.032327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.032371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.032414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.032498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.032545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.032595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.032640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.032685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.032734] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.032779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.032841] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.032885] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.032940] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.032989] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.033038] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.033091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.033138] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.033184] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 547.033223] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 547.033806] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.034239] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.034284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.034329] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.034372] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.034414] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.034495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.034540] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.034587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.034633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.034677] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.034720] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.034733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.034776] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.034783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.034827] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.034870] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.034914] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.034958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.035001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.035046] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.035089] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.035134] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.035177] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.035221] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.035264] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.035307] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.035370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.035424] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.035518] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.035675] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.035714] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.036012] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 547.036068] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.036111] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.036167] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.036537] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.036863] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.036907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.036951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.036993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.037036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.037082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.037126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.037169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.037213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.037257] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.037304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.037348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.037422] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.037642] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.039078] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.039124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.039169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 547.039953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.039997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.040755] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 547.040802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 547.041879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 547.044113] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 547.045185] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.045399] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.045498] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.045672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.062328] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.062375] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.062420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.062506] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.062549] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.062598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.062642] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.062685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.062730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.062773] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.062815] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.062824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.062866] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.062873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.062917] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.062960] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.063004] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.063047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.063090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.063135] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.063178] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.063223] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.063267] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.063310] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.063354] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.063397] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.063520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.063574] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.063617] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.078773] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.096697] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.096809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.096899] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.097222] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.097266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.097309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.097352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.097395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.097507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.097551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.097596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.097642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.097686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.097733] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.097778] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.097838] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.097880] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.097933] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.097983] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.098029] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.098082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.098130] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.098174] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 547.098213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 547.098795] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.099228] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.099273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.099318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.099362] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.099404] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.099496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.099540] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.099585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.099628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.099670] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.099713] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.099722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.099764] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.099770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.099814] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.099857] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.099901] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.099943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.099986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.100031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.100074] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.100119] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.100163] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.100206] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.100249] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.100292] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.100357] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.100411] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.100499] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.100651] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.100689] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.100978] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 547.101032] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.101074] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.101131] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.101645] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.101975] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.102018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.102062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.102104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.102147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.102190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.102233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.102275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.102318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.102360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.102406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.102533] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.102611] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.102654] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.104288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.104333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.104377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 547.105212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.105256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.106013] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 547.106058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 547.107106] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 547.108505] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 547.109577] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.109776] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.109828] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.109997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.126764] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.126811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.126856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.126899] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.126941] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.126985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.127028] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.127071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.127114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.127156] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.127197] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.127206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.127248] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.127254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.127296] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.127339] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.127382] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.127424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.127507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.127553] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.127595] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.127640] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.127684] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.127728] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.127772] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.127814] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.127880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.127931] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.127974] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.143210] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.160746] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.160858] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.160946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.161262] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.161306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.161349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.161394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.161492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.161536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.161582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.161626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.161669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.161712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.161758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.161802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.161861] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.161903] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.161957] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.162007] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.162055] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.162107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.162155] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.162199] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 547.162239] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 547.162844] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.163804] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.163849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.163894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.163938] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.163980] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.164024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.164067] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.164110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.164153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.164195] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.164237] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.164246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.164287] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.164293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.164336] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.164379] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.164422] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.164503] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.164546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.164591] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.164633] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.164679] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.164723] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.164766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.164809] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.164853] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.164918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.164971] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.165014] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.165168] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.165205] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.165524] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 547.165579] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.165621] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.165678] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.166420] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.166922] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.166967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.167010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.167055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.167098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.167141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.167184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.167226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.167269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.167313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.167361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.167405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.167520] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.167564] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.169289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.169717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.169764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 547.170734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.170779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.171630] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 547.171675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 547.175213] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 547.176533] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 547.177619] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.177857] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.177930] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.178139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.194774] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.194821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.194866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.194910] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.194952] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.194996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.195039] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.195082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.195125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.195167] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.195209] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.195218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.195259] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.195265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.195308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.195351] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.195393] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.195500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.195543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.195590] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.195635] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.195682] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.195725] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.195768] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.195813] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.195857] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.195918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.195970] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.196013] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.211192] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.228793] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.228908] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.228998] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.229324] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.229369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.229412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.229840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.229884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.229927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.229969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.230012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.230055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.230098] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.230148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.230192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.230256] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.230299] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.230352] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.230402] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.231064] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.231120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.231170] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.231214] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 547.231253] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 547.232425] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.232885] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.232931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.232978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.233021] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.233064] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.233108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.233152] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.233195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.233238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.233281] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.233322] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.233332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.233374] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.233380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.233423] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.234155] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.234199] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.234242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.234284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.234330] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.234371] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.234416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.234858] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.234902] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.234945] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.234988] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.235059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.235114] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.235157] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.235324] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.235362] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.236099] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 547.236896] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.236941] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.236996] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.237301] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.237645] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.237690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.237734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.237777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.237820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.237863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.237906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.237963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.238006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.238049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.238098] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.238142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.238218] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.238261] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.239766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.239812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.239857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 547.240742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.240786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.241533] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 547.241580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 547.242635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 547.244735] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 547.245767] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.245960] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.246014] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.246183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.262939] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.262988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.263034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.263079] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.263122] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.263166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.263212] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.263255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.263303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.263352] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.263401] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.263469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.263520] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.263528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.263572] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.263615] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.263657] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.263700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.263743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.263789] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.263831] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.263877] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.263920] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.263964] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.264008] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.264051] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.264128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.264182] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.264226] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.279344] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.297854] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.297966] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.298055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.298374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.298418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.298499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.298545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.298590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.298634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.298680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.298723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.298766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.298812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.298858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.298904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.298964] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.299007] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.299061] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.299110] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.299157] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.299209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.299256] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.299299] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:01 BXT-2 kernel: [ 547.299338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:01 BXT-2 kernel: [ 547.299919] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.300352] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.300398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.300511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.300555] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.300597] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.300643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.300687] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.300731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.300774] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.300817] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.300859] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.300868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.300910] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.300917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.300961] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.301004] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.301047] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.301091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.301133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.301178] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.301221] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.301267] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.301310] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.301355] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.301398] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.301463] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.301529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.301583] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.301626] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.301780] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:01 BXT-2 kernel: [ 547.301817] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:01 BXT-2 kernel: [ 547.302106] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:01 BXT-2 kernel: [ 547.302161] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.302203] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:01 BXT-2 kernel: [ 547.302259] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:01 BXT-2 kernel: [ 547.302753] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.303083] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.303127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:01 BXT-2 kernel: [ 547.303170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.303213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.303256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.303298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:01 BXT-2 kernel: [ 547.303341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:01 BXT-2 kernel: [ 547.303384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:01 BXT-2 kernel: [ 547.303426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:01 BXT-2 kernel: [ 547.303534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:01 BXT-2 kernel: [ 547.303583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:01 BXT-2 kernel: [ 547.303628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.303704] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:01 BXT-2 kernel: [ 547.303748] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.305289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.305336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.305381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:01 BXT-2 kernel: [ 547.306279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.306325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:01 BXT-2 kernel: [ 547.307198] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:01 BXT-2 kernel: [ 547.307245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:01 BXT-2 kernel: [ 547.308587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:01 BXT-2 kernel: [ 547.310691] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:01 BXT-2 kernel: [ 547.311718] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.311916] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:01 BXT-2 kernel: [ 547.311969] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:01 BXT-2 kernel: [ 547.312138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.328850] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:01 BXT-2 kernel: [ 547.328898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:01 BXT-2 kernel: [ 547.328945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:01 BXT-2 kernel: [ 547.328991] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:01 BXT-2 kernel: [ 547.329033] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:01 BXT-2 kernel: [ 547.329078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.329123] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:01 BXT-2 kernel: [ 547.329167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.329211] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:01 BXT-2 kernel: [ 547.329253] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.329294] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:01 BXT-2 kernel: [ 547.329305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.329346] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:01 BXT-2 kernel: [ 547.329352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.329395] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:01 BXT-2 kernel: [ 547.329510] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:01 BXT-2 kernel: [ 547.329553] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:01 BXT-2 kernel: [ 547.329596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:01 BXT-2 kernel: [ 547.329640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:01 BXT-2 kernel: [ 547.329688] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:01 BXT-2 kernel: [ 547.329730] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:01 BXT-2 kernel: [ 547.329779] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:01 BXT-2 kernel: [ 547.329822] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:01 BXT-2 kernel: [ 547.329866] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.329909] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.329952] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:01 BXT-2 kernel: [ 547.330016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:01 BXT-2 kernel: [ 547.330066] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:01 BXT-2 kernel: [ 547.330109] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:01 BXT-2 kernel: [ 547.345381] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.363691] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.363804] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.363892] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.364212] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.364256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.364299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.364342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.364385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.364428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.364539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.364583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.364626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.364670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.364718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.364763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.364823] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.364866] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.364920] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.364970] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.365016] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.365068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.365115] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.365158] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.365197] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.365792] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.366210] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.366256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.366301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.366345] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.366387] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.366431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.366503] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.366546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.366590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.366632] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.366673] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.366682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.366723] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.366729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.366773] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.366816] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.366860] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.366902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.366944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.366989] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.367032] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.367077] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.367120] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.367165] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.367207] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.367251] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.367317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.367372] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.367415] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.367608] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.367646] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.367936] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.367991] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.368033] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.368089] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.368612] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.368941] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.368986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.369030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.369073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.369115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.369159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.369201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.369244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.369287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.369331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.369380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.369425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.369579] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.369623] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.371238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.371283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.371329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.372158] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.372204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.373487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.375580] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.376623] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.376812] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.376865] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.377034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.393795] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.393841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.393886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.393930] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.393972] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.394015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.394058] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.394101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.394144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.394186] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.394228] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.394236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.394278] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.394284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.394327] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.394370] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.394412] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.395166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.395209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.395255] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.395296] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.395341] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.395384] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.395428] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.395806] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.395850] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.395920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.395973] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.396016] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.418570] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.428703] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.428816] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.428905] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.429226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.429270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.429313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.429355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.429398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.429491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.429536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.429579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.429622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.429665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.429713] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.429758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.429825] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.429868] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.429922] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.429974] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.430023] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.430076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.430125] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.430169] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.430208] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.430789] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.431205] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.431249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.431294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.431338] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.431380] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.431424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.431532] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.431575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.431619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.431662] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.431705] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.431714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.431757] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.431763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.431807] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.431850] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.431893] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.431935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.431978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.432023] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.432066] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.432111] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.432155] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.432198] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.432241] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.432284] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.432349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.432402] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.432468] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.433270] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.433309] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.433839] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.434223] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.434264] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.434319] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.434842] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.435160] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.435204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.435249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.435291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.435336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.435379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.435422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.435763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.435807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.435851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.435899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.435944] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.436019] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.436063] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.437834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.437878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.437923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.438962] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.439008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.440142] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.442249] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.443235] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.443802] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.443857] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.444028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.460391] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.460465] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.460512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.460555] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.460598] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.460642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.460686] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.460729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.460772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.460814] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.460856] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.460865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.460907] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.460913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.460956] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.460999] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.461041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.461084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.461126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.461171] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.461213] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.461259] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.461302] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.461345] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.461388] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.461430] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.461553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.461610] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.461655] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.476887] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.495606] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.495747] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.495864] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.496198] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.496247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.496291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.496334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.496377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.496420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.496956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.496999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.497042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.497085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.497135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.497180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.497242] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.497284] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.497337] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.497387] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.497433] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.497970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.498019] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.498062] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.498101] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.499266] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.499844] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.499889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.499934] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.499978] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.500020] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.500064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.500107] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.500150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.500193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.500235] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.500277] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.500285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.500327] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.500333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.500375] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.500418] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.501120] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.501163] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.501205] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.501250] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.501292] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.501337] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.501380] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.501423] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.501825] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.501868] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.501937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.501992] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.502035] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.502186] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.502224] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.502891] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.503200] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.503241] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.503296] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.503706] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.504034] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.504078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.504121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.504164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.504206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.504249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.504292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.504334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.504377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.504420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.504930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.504975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.505050] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.505094] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.506724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.506768] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.506813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.507686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.507729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.508622] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.508666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.509828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.511496] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.512597] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.512795] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.512848] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.513010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.529762] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.529809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.529853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.529897] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.529939] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.529983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.530027] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.530072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.530115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.530157] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.530199] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.530207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.530249] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.530255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.530298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.530340] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.530383] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.530425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.530512] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.530558] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.530603] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.530650] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.530694] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.530739] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.530784] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.530829] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.530890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.530944] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.530990] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.546165] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.563738] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.563853] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.563942] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.564268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.564312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.564355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.564398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.564490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.564535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.564579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.564625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.564669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.564714] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.564761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.564806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.564868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.564911] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.564964] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.565013] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.565059] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.565111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.565157] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.565201] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.565241] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.565828] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.566257] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.566302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.566347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.566391] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.566481] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.566528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.566573] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.566616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.566659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.566702] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.566744] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.566755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.566796] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.566803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.566847] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.566891] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.566934] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.566978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.567021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.567067] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.567110] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.567159] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.567202] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.567247] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.567290] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.567333] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.567398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.567495] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.567539] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.567699] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.567736] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.568026] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.568080] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.568122] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.568179] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.568485] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.568810] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.568854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.568897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.568940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.568982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.569025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.569068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.569111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.569153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.569197] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.569246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.569290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.569365] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.569408] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.571413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.571484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.571530] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.572289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.572331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.573588] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.573635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.575030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.576499] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.577522] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.577718] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.577770] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.577940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.594681] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.594727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.594772] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.594816] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.594858] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.594902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.594945] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.594988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.595031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.595073] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.595114] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.595123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.595165] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.595171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.595214] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.595257] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.595299] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.595342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.595384] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.595429] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.596283] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.596329] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.596372] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.596416] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.596704] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.596747] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.596818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.596873] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.596919] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.611107] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.628718] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.628830] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.628920] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.629251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.629294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.629338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.629381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.629423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.629519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.629563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.629607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.629650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.629693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.629741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.629786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.629848] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.629891] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.629945] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.629995] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.630042] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.630094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.630141] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.630184] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.630227] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.630807] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.631246] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.631291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.631336] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.631380] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.631422] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.631537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.631582] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.631625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.631670] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.631712] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.631754] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.631764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.631806] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.631813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.631857] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.631902] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.631945] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.631988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.632031] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.632078] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.632120] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.632171] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.632215] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.632258] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.632302] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.632344] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.632412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.632489] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.632532] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.632704] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.632742] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.633032] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.633086] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.633128] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.633185] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.633431] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.633787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.633831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.633874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.633917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.633960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.634003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.634046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.634088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.634131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.634174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.634223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.634268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.634343] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.634387] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.636563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.636609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.636654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.637437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.637538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.638426] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.638551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.639872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.641977] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.643005] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.643208] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.643260] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.643430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.660148] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.660194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.660239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.660283] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.660325] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.660369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.660412] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.660889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.660933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.660975] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.661017] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.661026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.661068] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.661074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.661117] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.661161] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.661204] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.661247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.661289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.661333] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.661375] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.661420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.662051] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.662097] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.662139] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.662182] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.662253] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.662306] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.662349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.676574] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.694829] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.694943] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.695035] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.695364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.695408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.695506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.695551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.695596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.695640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.695683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.695728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.695771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.695814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.695862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.695907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.695968] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.696010] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.696064] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.696114] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.696160] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.696212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.696260] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.696303] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.696342] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.696942] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.697935] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.697981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.698027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.698071] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.698113] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.698157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.698201] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.698244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.698287] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.698329] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.698371] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.698380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.698421] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.698465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.698512] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.698555] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.698601] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.698643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.698685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.698730] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.698776] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.698822] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.698867] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.698912] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.698957] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.699001] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.699067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.699121] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.699167] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.700934] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.700977] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.701267] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.701323] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.701365] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.701421] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.701968] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.702293] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.702337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.702382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.702425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.702519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.702564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.702607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.702650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.702693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.702737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.702785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.702830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.702905] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.702949] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.704524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.704569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.704613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.705364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.705407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.706182] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.706227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.707499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.709594] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.710605] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.710804] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.710857] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.711027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.727930] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.727977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.728023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.728067] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.728109] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.728153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.728197] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.728240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.728284] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.728327] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.728369] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.728378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.728420] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.729195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.729253] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.729296] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.729339] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.729382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.729424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.729798] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.729840] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.729886] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.729929] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.729972] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.730015] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.730057] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.730126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.730180] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.730223] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.744196] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.762518] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.762630] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.762721] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.763039] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.763083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.763127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.763170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.763212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.763255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.763299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.763342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.763385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.763427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.763517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.763564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.763629] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.763671] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.763725] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.763776] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.763824] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.763876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.763923] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.763966] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.764013] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.764588] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.765030] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.765077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.765122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.765166] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.765209] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.765254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.765298] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.765341] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.765384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.765427] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.765512] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.765523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.765565] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.765571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.765614] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.765657] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.765701] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.765744] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.765786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.765832] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.765875] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.765920] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.765964] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.766007] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.766051] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.766094] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.766162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.766216] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.766259] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.766382] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.766420] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.766740] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.766794] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.766837] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.766893] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.767297] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.767667] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.767713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.767757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.767800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.767843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.767886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.767929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.767972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.768014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.768057] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.768105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.768150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.768224] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.768267] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.769927] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.769973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.770017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.770936] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.770981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.772184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.774365] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.775430] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.775642] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.775695] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.775867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.792619] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.792666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.792711] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.792754] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.792796] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.792840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.792883] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.792926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.792969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.793011] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.793052] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.793061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.793102] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.793108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.793151] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.793194] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.793236] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.793278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.793320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.793365] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.793407] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.794307] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.794351] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.794395] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.794621] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.794665] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.794733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.794787] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.794830] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.809020] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.826740] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.826852] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.826941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.827264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.827308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.827351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.827394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.827480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.827524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.827569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.827614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.827658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.827701] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.827748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.827793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.827852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.827894] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.827947] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.827997] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.828043] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.828097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.828143] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.828187] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.828226] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.828814] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.829241] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.829287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.829332] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.829376] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.829418] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.829540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.829585] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.829628] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.829673] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.829715] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.829757] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.829767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.829809] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.829816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.829860] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.829903] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.829947] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.829989] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.830032] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.830077] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.830120] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.830165] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.830209] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.830252] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.830295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.830338] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.830402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.830490] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.830533] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.830687] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.830725] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.831015] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.831070] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.831112] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.831168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.831595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.831925] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.831969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.832013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.832055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.832098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.832141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.832184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.832226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.832269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.832312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.832359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.832404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.832532] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.832576] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.834156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.834201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.834245] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.835207] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.835254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.836485] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.838497] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.839486] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.839708] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.839761] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.839930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.856666] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.856713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.856758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.856801] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.856843] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.856887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.856930] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.856973] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.857016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.857058] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.857100] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.857109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.857151] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.857156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.857199] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.857242] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.857284] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.857327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.857369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.857414] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.857494] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.857543] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.857590] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.857636] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.857681] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.857727] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.857792] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.857841] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.857886] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.873152] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.890862] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.890975] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.891064] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.891396] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.891739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.891783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.891825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.891868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.891911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.891954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.891996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.892039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.892082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.892129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.892173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.892235] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.892277] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.892330] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.892382] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.892428] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.893086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.893135] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.893178] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.893216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.894375] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.894877] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.894922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.894967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.895011] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.895053] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.895097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.895140] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.895183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.895226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.895269] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.895311] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.895319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.895361] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.895367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.895410] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.896105] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.896148] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.896190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.896232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.896277] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.896319] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.896364] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.896407] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.896769] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.896812] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.896855] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.896923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.896977] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.897020] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.897166] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.897203] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.897861] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.898176] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.898217] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.898273] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.898964] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.899300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.899343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.899387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.899429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.899852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.899895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.899938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.899981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.900023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.900066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.900117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.900161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.900237] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.900280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.905321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.905368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.905412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.906531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.906574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.907287] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.907330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.908383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.910512] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.911572] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.911769] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.911821] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.911990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.928746] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.928793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.928838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.928882] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.928923] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.928967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.929010] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.929053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.929096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.929138] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.929180] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.929189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.929231] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.929237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.929280] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.929323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.929365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.929407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.929506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.929553] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.929596] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.929642] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.929688] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.929733] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.929779] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.929822] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.929884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.929935] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.929980] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.945155] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.962873] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.962985] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.963073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.963391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.963488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.963533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.963577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.963619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.963662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.963706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.963749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.963792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.963835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.963882] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.963927] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.963989] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.964032] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.964085] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.964135] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.964181] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.964234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.964280] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.964324] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 547.964362] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 547.964958] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.965421] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.965510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.965555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.965599] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.965641] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.965686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.965730] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.965773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.965816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.965858] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.965900] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.965909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.965951] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.965957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.966000] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.966042] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.966085] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.966128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.966171] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.966216] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.966260] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.966306] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.966349] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.966393] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.966480] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.966523] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.966593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.966647] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.966690] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.966840] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 547.966878] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 547.967168] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 547.967222] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.967264] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 547.967321] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 547.967990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.968554] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.968601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 547.968646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.968689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.968732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.968779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 547.968822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 547.968866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 547.968909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 547.968952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 547.969001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 547.969047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.969123] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 547.969167] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.970741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.970786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.970831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 547.971616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.971659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 547.972387] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 547.972431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 547.973562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 547.975661] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 547.976709] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 547.976894] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 547.976946] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 547.977116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.995183] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 547.995230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 547.995276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 547.995319] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 547.995362] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 547.995405] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.995545] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 547.995588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.995632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 547.995676] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.995718] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 547.995727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.995770] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 547.995776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.995820] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 547.995863] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 547.995907] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 547.995950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 547.995993] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 547.996038] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 547.996080] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 547.996126] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 547.996169] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 547.996213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.996256] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.996299] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 547.996363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 547.996416] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 547.996489] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.010341] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.027709] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.027822] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.027910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.028227] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.028272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.028315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.028358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.028400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.028499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.028542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.028588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.028631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.028674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.028720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.028766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.028826] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.028869] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.028922] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.028972] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.029019] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.029071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.029118] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.029162] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 548.029200] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 548.029796] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.030757] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.030804] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.030849] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.030893] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.030935] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.030980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.031023] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.031066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.031109] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.031151] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.031193] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.031202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.031243] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.031249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.031292] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.031335] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.031377] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.031420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.031508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.031557] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.031601] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.031649] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.031693] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.031739] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.031784] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.031830] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.031898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.031952] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.031998] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.032154] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.032192] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.032525] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 548.032582] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.032624] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.032681] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.033250] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.033816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.033862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.033906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.033949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.033993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.034036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.034081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.034124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.034168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.034211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.034259] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.034303] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.034378] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.034421] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.036298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.036344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.036389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 548.037514] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 548.037562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 548.038970] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 548.041717] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 548.042830] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.043025] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.043077] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.043245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.059966] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.060013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.060058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.060101] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.060143] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.060187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.060230] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.060272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.060315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.060357] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.060399] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.060458] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.060502] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.060510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.060556] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.060601] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.060647] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.060690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.060733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.060778] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.060823] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.060868] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.060911] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.060954] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.060997] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.061039] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.061102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.061155] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.061198] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.076428] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.094749] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.094863] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.094953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.095282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.095326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.095370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.095413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.095840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.095884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.095927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.095969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.096012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.096056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.096106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.096150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.096213] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.096256] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.096309] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.096359] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.096405] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.096849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.096899] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.096943] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 548.096982] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 548.098154] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.098869] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.098916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.098962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.099006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.099048] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.099092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.099136] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.099179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.099222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.099265] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.099306] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.099315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.099357] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.099363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.099406] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.099856] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.099901] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.099945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.099987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.100034] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.100077] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.100123] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.100167] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.100210] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.100254] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.100297] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.100730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.101034] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.101079] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.101226] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.101265] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.101590] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 548.101649] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.101691] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.101750] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.102000] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.102321] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.102365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.102409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.102508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.102552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.102596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.102640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.102684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.102727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.102771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.102819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.102864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.102938] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.102982] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.104427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.104502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.104547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 548.105300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.105341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.106077] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 548.106122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 548.107166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 548.109257] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 548.110254] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.110487] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.110542] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.110712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.127727] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.127785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.127832] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.127876] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.127918] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.127963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.128009] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.128052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.128095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.128137] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.128179] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.128188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.128230] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.128236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.128279] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.128322] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.128365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.128408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.128672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.128718] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.128762] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.128809] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.128853] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.128897] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.128941] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.128984] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.129054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.129109] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.129153] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.143898] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.161762] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.161874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.161963] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.162278] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.162323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.162366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.162409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.162506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.162553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.162598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.162641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.162685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.162728] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.162775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.162821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.162884] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.162927] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.162982] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.163033] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.163081] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.163135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.163184] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.163228] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 548.163267] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 548.163859] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.164284] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.164329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.164374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.164418] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.164507] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.164555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.164599] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.164642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.164686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.164731] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.164773] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.164783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.164825] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.164831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.164875] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.164919] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.164962] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.165005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.165048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.165093] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.165136] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.165182] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.165226] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.165269] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.165314] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.165357] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.165423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.165510] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.165556] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.165706] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.165745] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.166041] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 548.166097] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.166139] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.166196] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.166795] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.167115] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.167159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.167202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.167245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.167288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.167331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.167373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.167416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.167830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.167873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.167923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.167967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.168042] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.168085] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.169829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.169875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.169921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 548.171072] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 548.171119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 548.172297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 548.174410] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 548.175481] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.175666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.175719] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.175887] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.192637] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.192683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.192729] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.192772] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.192814] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.192858] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.192901] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.192943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.192986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.193028] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.193070] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.193079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.193120] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.193126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.193169] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.193211] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.193254] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.193296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.193338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.193382] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.193424] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.193526] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.193571] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.193618] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.193662] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.193706] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.193768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.194091] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.194135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.209059] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.226726] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.226839] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.226927] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.227250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.227294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.227337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.227379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.227422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.227510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.227554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.227600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.227645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.227689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.227736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.227781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.227842] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.227884] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.227938] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.227987] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.228033] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.228084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.228132] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.228176] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 548.228215] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 548.228800] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.229209] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.229254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.229300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.229344] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.229386] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.229431] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.229556] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.229600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.229643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.229686] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.229728] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.229738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.229780] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.229786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.229830] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.229873] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.229917] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.229959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.230002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.230047] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.230090] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.230135] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.230179] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.230222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.230266] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.230308] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.230374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.230428] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.230508] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.230663] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.230701] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.230991] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 548.231045] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.231087] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.231143] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.231572] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.231903] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.231948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.231991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.232034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.232077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.232120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.232162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.232205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.232247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.232290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.232337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.232381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.232506] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.233243] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.235244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.235289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.235334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 548.236132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.236176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.236903] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 548.236946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 548.237976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 548.240067] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 548.241061] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.241249] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.241301] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.241505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.258176] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.258221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.258266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.258310] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.258352] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.258396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.258494] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.258544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.258590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.258635] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.258681] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.258691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.258734] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.258740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.258785] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.258830] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.258877] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.258921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.258964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.259009] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.259052] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.259097] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.259140] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.259184] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.259227] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.259270] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.259334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.259384] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.259427] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.274703] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.292745] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.292858] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.292947] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.293263] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.293307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.293350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.293393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.293496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.293541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.293584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.293627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.293670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.293714] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.293762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.293807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.293868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.293911] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.293965] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.294015] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.294061] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.294113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.294160] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.294203] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:02 BXT-2 kernel: [ 548.294242] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:02 BXT-2 kernel: [ 548.294829] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.295249] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.295293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.295338] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.295382] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.295424] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.295511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.295556] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.295599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.295643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.295686] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.295728] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.295738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.295780] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.295785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.295829] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.295872] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.295916] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.295959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.296002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.296047] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.296089] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.296136] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.296179] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.296222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.296266] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.296308] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.296371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.296425] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.296491] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.296646] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:02 BXT-2 kernel: [ 548.296684] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:02 BXT-2 kernel: [ 548.296974] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:02 BXT-2 kernel: [ 548.297029] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.297073] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:02 BXT-2 kernel: [ 548.297130] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:02 BXT-2 kernel: [ 548.297520] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.298100] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.298145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:02 BXT-2 kernel: [ 548.298189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.298231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.298274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.298317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:02 BXT-2 kernel: [ 548.298360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:02 BXT-2 kernel: [ 548.298402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:02 BXT-2 kernel: [ 548.298495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:02 BXT-2 kernel: [ 548.298542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:02 BXT-2 kernel: [ 548.298594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:02 BXT-2 kernel: [ 548.298640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.298715] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:02 BXT-2 kernel: [ 548.298758] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.300198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.300242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:02 BXT-2 kernel: [ 548.300287] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:02 BXT-2 kernel: [ 548.301206] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:02 BXT-2 kernel: [ 548.301253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:02 BXT-2 kernel: [ 548.302387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:02 BXT-2 kernel: [ 548.304540] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:02 BXT-2 kernel: [ 548.305622] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.305809] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:02 BXT-2 kernel: [ 548.305862] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:02 BXT-2 kernel: [ 548.306033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.322808] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:02 BXT-2 kernel: [ 548.322857] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:02 BXT-2 kernel: [ 548.322902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:02 BXT-2 kernel: [ 548.322946] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:02 BXT-2 kernel: [ 548.322988] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:02 BXT-2 kernel: [ 548.323032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.323076] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:02 BXT-2 kernel: [ 548.323119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.323162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:02 BXT-2 kernel: [ 548.323205] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.323246] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:02 BXT-2 kernel: [ 548.323255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.323297] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:02 BXT-2 kernel: [ 548.323303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.323346] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:02 BXT-2 kernel: [ 548.323389] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:02 BXT-2 kernel: [ 548.323431] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:02 BXT-2 kernel: [ 548.323519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:02 BXT-2 kernel: [ 548.323565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:02 BXT-2 kernel: [ 548.323614] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:02 BXT-2 kernel: [ 548.323661] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:02 BXT-2 kernel: [ 548.323708] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:02 BXT-2 kernel: [ 548.323754] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:02 BXT-2 kernel: [ 548.323800] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.323846] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.323893] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:02 BXT-2 kernel: [ 548.323961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:02 BXT-2 kernel: [ 548.324014] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:02 BXT-2 kernel: [ 548.324059] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:02 BXT-2 kernel: [ 548.339211] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.357719] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.357831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.357920] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.358244] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.358288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.358332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.358375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.358417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.358548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.358595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.358641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.358686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.358732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.358782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.358828] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.358887] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.358930] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.358984] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.359845] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.359895] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.359966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.360016] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.360060] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.360099] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.360702] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.362144] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.362191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.362237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.362280] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.362322] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.362367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.362411] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.362505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.362552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.362596] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.362638] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.362649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.362693] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.362699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.362742] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.362786] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.362828] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.362871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.362913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.362959] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.363000] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.363045] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.363088] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.363132] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.363175] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.363217] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.363286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.363341] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.363384] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.364677] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.364717] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.365010] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.365066] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.365107] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.365164] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.365850] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.366174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.366218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.366262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.366305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.366348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.366391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.366816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.367110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.367153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.367196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.367246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.367291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.367366] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.367409] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.368879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.368922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.368967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.369743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.369786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.370516] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.370560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.371607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.373687] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.374700] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.374909] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.374963] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.375131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.392025] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.392084] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.392142] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.392195] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.392245] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.392299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.392356] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.392403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.392574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.392618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.392662] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.392671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.392713] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.392719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.392763] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.392806] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.392850] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.392893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.392936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.392982] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.393024] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.393070] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.393113] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.393157] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.393201] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.393243] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.393312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.393366] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.393409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.408361] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.425702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.425815] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.425903] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.426225] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.426269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.426312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.426355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.426398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.426491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.426544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.426590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.426635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.426680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.426729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.426774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.426840] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.426884] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.426937] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.426987] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.427034] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.427086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.427132] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.427175] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.427214] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.427805] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.428227] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.428273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.428318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.428362] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.428404] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.428494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.428540] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.428587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.428630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.428673] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.428715] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.428725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.428766] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.428773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.428816] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.428859] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.428903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.428946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.428989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.429034] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.429076] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.429122] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.429165] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.429208] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.429251] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.429294] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.429361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.429414] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.429487] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.429644] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.429682] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.429972] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.430026] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.430068] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.430125] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.430428] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.430789] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.430834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.430877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.430920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.430962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.431005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.431048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.431090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.431133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.431175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.431222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.431266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.431340] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.431382] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.433396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.433472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.433517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.434301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.434346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.435117] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.435165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.436250] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.437622] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.438713] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.438933] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.438988] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.439161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.455850] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.455897] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.455942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.455986] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.456028] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.456071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.456115] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.456157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.456200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.456243] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.456284] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.456293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.456335] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.456341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.456384] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.456426] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.456535] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.456580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.456622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.456667] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.456710] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.456755] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.456799] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.456842] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.456886] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.456928] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.456996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.457048] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.457091] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.472333] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.490719] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.490832] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.490921] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.491246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.491290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.491333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.491376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.491419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.491513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.491558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.491604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.491648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.491691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.491740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.491785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.491845] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.491887] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.491942] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.491991] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.492037] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.492089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.492135] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.492178] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.492217] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.492845] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.493779] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.493825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.493871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.493915] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.493957] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.494001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.494045] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.494088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.494131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.494174] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.494215] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.494224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.494266] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.494272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.494314] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.494357] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.494400] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.494934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.494977] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.495022] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.495064] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.495109] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.495153] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.495195] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.495238] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.495281] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.495352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.495406] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.495508] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.495945] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.495985] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.496277] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.496332] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.496373] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.496846] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.497864] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.498191] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.498235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.498278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.498321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.498364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.498407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.498816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.498860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.498903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.498946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.498996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.499040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.499116] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.499159] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.501308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.501356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.501401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.502262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.502306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.503051] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.503095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.504146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.506237] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.507260] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.507500] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.507555] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.507724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.524386] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.524432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.524520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.524565] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.524610] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.524653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.524697] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.524742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.524785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.524827] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.524870] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.524879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.524922] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.524929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.524973] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.525016] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.525059] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.525102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.525145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.525191] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.525233] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.525278] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.525322] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.525365] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.525409] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.525513] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.525578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.525629] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.525672] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.540868] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.558903] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.559015] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.559107] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.559425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.559530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.559575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.559618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.559661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.559706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.559749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.559794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.559838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.559883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.559929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.559976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.560038] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.560080] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.560135] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.560184] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.560230] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.560282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.560330] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.560374] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.560412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.560991] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.561415] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.561510] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.561558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.561601] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.561645] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.561691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.561735] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.561779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.561822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.561865] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.561907] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.562049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.562099] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.562106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.562149] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.562192] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.562236] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.562279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.562322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.562367] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.562410] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.562476] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.562520] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.562564] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.562607] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.562649] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.562719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.562773] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.562816] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.562966] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.563003] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.563293] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.563347] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.563389] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.563467] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.563941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.564263] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.564306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.564350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.564392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.564486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.564530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.564573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.564616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.564660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.564703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.564751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.564796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.564870] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.564913] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.566538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.566583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.566627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.567406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.567521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.568686] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.568734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.569843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.571515] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.572637] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.572870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.572928] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.573099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.576856] perf: interrupt took too long (2514 > 2500), lowering kernel.perf_event_max_sample_rate to 79000 >May 24 03:31:03 BXT-2 kernel: [ 548.589784] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.589831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.589876] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.589920] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.589962] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.590006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.590049] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.590092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.590135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.590177] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.590219] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.590228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.590269] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.590275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.590318] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.590361] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.590403] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.590488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.590533] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.590580] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.590623] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.590669] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.590715] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.590760] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.590807] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.590852] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.590912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.590961] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.591008] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.606236] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.624709] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.624822] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.624910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.625235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.625279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.625322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.625365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.625408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.625492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.625537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.625582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.625627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.625672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.625720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.625765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.625826] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.625868] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.625923] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.625972] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.626018] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.626071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.626117] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.626161] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.626199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.626784] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.627207] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.627252] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.627298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.627342] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.627384] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.627429] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.627550] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.627593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.627637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.627679] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.627721] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.627730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.627772] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.627778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.627821] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.627864] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.627906] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.627948] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.627991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.628036] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.628077] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.628122] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.628165] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.628208] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.628251] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.628293] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.628358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.628412] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.628537] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.628690] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.628728] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.629020] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.629075] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.629115] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.629171] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.630878] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.631205] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.631250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.631293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.631336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.631379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.631422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.631951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.631995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.632038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.632081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.632130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.632175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.632251] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.632295] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.634241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.634288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.634332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.635324] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.635371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.636884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.639087] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.640099] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.640293] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.640346] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.640588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.657208] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.657254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.657300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.657343] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.657853] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.657900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.657945] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.657988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.658031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.658074] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.658115] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.658125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.658167] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.658172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.658216] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.658258] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.658301] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.658343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.658385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.658430] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.658527] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.658572] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.658615] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.658658] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.658701] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.658743] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.658813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.658867] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.658910] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.673694] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.691941] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.692054] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.692142] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.692496] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.692541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.692587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.692630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.692673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.692718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.692761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.692804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.692847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.692891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.692938] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.692983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.693043] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.693086] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.693139] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.693189] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.693235] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.693287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.693333] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.693376] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.693415] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.694001] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.694410] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.694495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.694541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.694585] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.694627] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.694672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.694716] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.694759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.694803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.694846] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.694888] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.694897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.694939] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.694945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.694989] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.695032] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.695075] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.695119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.695162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.695207] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.695250] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.695295] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.695338] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.695382] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.695425] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.695486] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.695549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.695602] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.695645] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.695794] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.695832] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.696121] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.696175] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.696216] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.696272] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.696806] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.697126] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.697170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.697213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.697255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.697298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.697341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.697383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.697426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.697515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.697559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.697606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.697651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.697725] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.697768] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.699350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.699394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.699480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.700246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.700289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.701204] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.701251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.702607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.704729] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.705786] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.705980] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.706033] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.706203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.722915] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.722961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.723006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.723049] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.723091] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.723135] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.723178] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.723221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.723264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.723306] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.723348] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.723357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.723420] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.724159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.724218] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.724262] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.724305] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.724347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.724389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.724504] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.724547] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.724593] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.724637] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.724680] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.724724] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.724767] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.724836] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.724891] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.724934] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.739377] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.757721] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.757834] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.757923] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.758252] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.758296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.758339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.758382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.758425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.758958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.759001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.759044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.759087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.759130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.759180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.759225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.759288] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.759331] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.759384] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.759919] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.759970] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.760025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.760075] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.760119] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.760157] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.761327] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.761900] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.761946] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.761992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.762036] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.762078] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.762123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.762167] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.762210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.762253] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.762295] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.762337] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.762346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.762388] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.762394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.763091] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.763135] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.763178] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.763220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.763262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.763309] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.763351] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.763396] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.763849] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.763894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.763936] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.763979] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.764052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.764107] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.764150] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.764322] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.764360] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.765107] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.765425] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.765656] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.765714] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.765974] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.766305] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.766348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.766391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.766849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.766893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.766937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.766980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.767022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.767065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.767108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.767158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.767203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.767278] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.767322] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.769628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.769674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.769718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.770713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.770756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.771590] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.771636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.772746] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.774842] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.775885] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.776073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.776125] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.776295] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.793056] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.793103] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.793149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.793192] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.793235] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.793279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.793323] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.793367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.793411] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.794029] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.794081] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.794092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.794145] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.794152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.794205] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.794256] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.794306] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.794355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.794403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.795024] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.795067] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.795113] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.795157] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.795201] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.795244] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.795288] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.795362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.795418] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.796100] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.809605] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.827835] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.827947] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.828035] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.828357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.828401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.828500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.828543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.828589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.828633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.828677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.828720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.828762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.828805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.828853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.828898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.828958] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.829001] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.829055] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.829105] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.829151] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.829203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.829250] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.829294] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.829333] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.829921] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.830350] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.830397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.830496] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.830542] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.830584] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.830629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.830675] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.830718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.830761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.830804] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.830847] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.830857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.830899] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.830906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.830949] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.830992] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.831036] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.831078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.831121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.831166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.831209] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.831255] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.831299] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.831342] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.831385] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.831428] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.831521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.831576] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.831619] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.831776] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.831814] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.832103] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.832157] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.832199] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.832256] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.832995] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.833323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.833366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.833409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.833519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.833562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.833606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.833649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.833692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.833736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.833779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.833827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.833872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.833947] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.833990] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.835562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.835607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.835652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.836426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.836618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.838365] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.838412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.839598] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.842136] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.843191] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.843381] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.843433] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.843643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.860287] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.860333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.860378] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.860422] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.860515] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.860563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.860609] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.860653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.860696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.860742] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.860783] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.860792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.860834] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.860840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.860883] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.860925] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.860968] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.861011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.861053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.861098] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.861140] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.861187] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.861231] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.861274] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.861318] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.861361] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.861428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.861546] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.861590] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.876779] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.894705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.894817] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.894906] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.895226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.895270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.895313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.895356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.895398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.895491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.895534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.895579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.895622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.895665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.895711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.895756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.895818] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.895861] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.895914] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.895964] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.896010] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.896062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.896108] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.896151] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.896190] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.896773] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.897195] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.897241] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.897286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.897330] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.897372] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.897416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.897502] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.897547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.897590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.897633] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.897676] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.897685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.897728] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.897734] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.897778] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.897821] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.897865] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.897907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.897949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.897995] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.898037] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.898083] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.898126] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.898170] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.898213] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.898256] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.898320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.898373] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.898416] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.898618] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.898656] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.898945] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.898999] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.899041] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.899097] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.899546] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.899877] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.899922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.899965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.900008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.900050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.900093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.900136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.900178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.900221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.900264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.900311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.900356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.900430] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.900519] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.902647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.902692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.902737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.903525] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.903567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.904416] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.904501] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.905590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.907683] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.908698] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.908893] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.908945] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.909114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.925892] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.925955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.926012] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.926067] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.926118] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.926173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.926229] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.926280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.926331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.926382] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.926426] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.926506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.926582] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.926589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.926634] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.926678] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.926721] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.926764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.926807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.926852] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.926894] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.926940] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.926983] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.927027] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.927070] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.927113] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.927193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.927248] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.927292] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.942269] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.959870] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.959982] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.960070] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.960395] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.960503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.960550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.960595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.960641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.960687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.960732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.960777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.960821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.960865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.960914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.960960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.961022] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.961066] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.961121] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.961172] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.961220] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.961273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.961320] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.961364] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 548.961403] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 548.961997] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.962413] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.962500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.962547] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.962591] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.962634] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.962678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.962727] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.962772] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.962818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.962861] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.962904] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.962914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.962957] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.962963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.963007] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.963054] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.963099] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.963144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.963189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.963235] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.963278] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.963324] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.963368] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.963411] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.963508] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.963551] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.963622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.963678] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.963721] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.963876] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 548.963915] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 548.964213] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 548.964268] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.964310] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 548.964368] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 548.964911] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.965235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.965279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 548.965322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.965366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.965409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.965792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 548.965835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 548.965878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 548.965921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 548.965964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 548.966013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 548.966058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.966132] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 548.966175] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.967810] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.967855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.967900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 548.968895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.968940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 548.970030] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 548.970093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 548.971255] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 548.973362] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 548.974368] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 548.974593] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 548.974647] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 548.974822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.991509] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 548.991556] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 548.991601] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 548.991644] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 548.991686] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 548.991729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.991772] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 548.991815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.991858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 548.991900] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.991942] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 548.991951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.991993] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 548.991999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.992042] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 548.992084] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 548.992127] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 548.992169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 548.992212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 548.992256] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 548.992298] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 548.992343] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 548.992385] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 548.992428] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.993507] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.993550] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 548.993621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 548.993676] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 548.993719] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 549.007954] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 549.024713] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 549.024825] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.024914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.025237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.025281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.025324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.025367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.025409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.025886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.025930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.025973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.026015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.026058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.026106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.026150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.026211] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.026254] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.026307] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.026356] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.026402] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 549.026969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.027019] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.027062] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 549.027101] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 549.028266] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.028857] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.028902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.028948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.028992] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.029034] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.029078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.029121] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.029164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.029207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.029249] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.029291] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.029300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.029341] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.029347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.029390] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.030049] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.030094] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.030137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.030179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.030224] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.030266] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.030311] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 549.030353] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 549.030396] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.030841] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.030884] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.030951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.031005] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.031048] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 549.031198] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.031236] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.031881] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 549.032202] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.032244] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.032300] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.032647] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.032987] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.033032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.033075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.033118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.033160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.033205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.033248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.033290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.033332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.033375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.033422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.033535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.033610] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 549.033654] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.035089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.035134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.035179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 549.035960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.036004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.036866] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 549.036911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 549.037976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 549.040073] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 549.041078] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 549.041271] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.041323] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 549.041538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.058380] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.058436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.058981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.059026] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.059068] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.059112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.059158] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.059201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.059244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.059286] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.059328] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.059337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.059378] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.059384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.059427] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.060373] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.060418] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.060865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.060908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.060954] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.060996] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.061042] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:80, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 549.061085] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 549.061128] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.061172] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.061214] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.061290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.061345] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.061389] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:03 BXT-2 kernel: [ 549.074662] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:03 BXT-2 kernel: [ 549.092719] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:03 BXT-2 kernel: [ 549.092832] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.092921] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.093242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.093286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.093329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.093372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.093414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.093506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.093551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.093596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.093640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.093684] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.093730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.093777] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.093835] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.093877] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.093930] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.093979] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.094025] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 549.094077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.094124] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.094167] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 549.094206] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 549.094790] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.095198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.095301] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.095339] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.095701] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 549.096269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.096314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.096357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.096399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.096486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.096535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.096578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.096621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.096665] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.096710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.096757] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.096803] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.096866] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 549.096918] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.096962] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 549.097001] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 549.097597] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.098604] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:03 BXT-2 kernel: [ 549.098670] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:03 BXT-2 kernel: [ 549.159215] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:03 BXT-2 kernel: [ 549.159703] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.160273] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:03 BXT-2 kernel: [ 549.160906] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.160953] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.161069] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.161115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.161161] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.161205] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.161248] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.161293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.161337] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.161380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.161425] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.161495] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.161538] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.161546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.161588] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.161595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.161639] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.161682] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.161726] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.161769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.161812] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.161858] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.161900] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.161944] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.161988] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.162031] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.162075] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.162138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.162191] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.162236] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.162839] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.162879] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.163169] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 549.163222] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.163267] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.163326] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.163626] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.163948] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.163992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.164036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.164083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.164126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.164169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.164213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.164257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.164301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.164345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.164392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.164475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.164550] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:03 BXT-2 kernel: [ 549.164595] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.166055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.166098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.166143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 549.166922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.166966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.167749] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 549.167794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 549.168863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 549.170952] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 549.171995] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.188886] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.188944] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.189115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.222439] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.222546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.222591] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.222635] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.222677] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.222720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.222764] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.222807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.222850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.222892] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.222934] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.222943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.222985] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.222990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.223033] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.223076] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.223119] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.223161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.223203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.223248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.223290] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.223334] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 549.223377] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 549.223420] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.223500] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.223546] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.223608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.223660] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.223705] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.238904] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.257556] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:03 BXT-2 kernel: [ 549.257702] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.257811] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.258136] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.258182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.258225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.258269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.258312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.258356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.258400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.258546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.258589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.258633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.258683] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.258728] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.258798] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.258842] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.258896] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.258946] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.258992] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.259039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.259085] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.259127] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 549.259167] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 549.259752] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.260186] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.260233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.260278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.260322] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.260364] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.260408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.260516] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.260599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.260644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.260686] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.260729] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.260739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.260780] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.260787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.260830] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.260873] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.260917] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.260960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.261002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.261047] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.261090] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.261135] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 549.261179] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 549.261222] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.261265] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.261308] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.261379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.261467] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.261511] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.261658] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.261696] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.261986] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 549.262039] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.262082] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.262139] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.263127] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.263509] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.263555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.263600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.263643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.263686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.263729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.263773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.263816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.263859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.263902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.263951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.263996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.264071] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:03 BXT-2 kernel: [ 549.264115] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.265940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.265987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.266032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 549.267043] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 549.267091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 549.268262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 549.270388] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 549.271447] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.271693] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.271746] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.271916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.288669] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.288716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.288761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.288805] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.288847] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.288891] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.288936] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.288979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.289022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.289064] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.289105] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.289114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.289156] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.289162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.289205] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.289247] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.289290] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.289332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.289374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.289419] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.289501] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.289546] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 549.289591] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 549.289637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.289682] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.289727] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.289789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.289841] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.289884] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.305261] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.323732] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:03 BXT-2 kernel: [ 549.323846] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.323934] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.324257] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.324301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.324344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.324387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.324430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.325072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.325115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.325157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.325200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.325243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.325292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.325337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.325398] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.325806] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.325860] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.325911] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.325958] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.326004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.326051] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.326094] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:03 BXT-2 kernel: [ 549.326133] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:03 BXT-2 kernel: [ 549.327300] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.327873] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:03 BXT-2 kernel: [ 549.327919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:03 BXT-2 kernel: [ 549.327964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:03 BXT-2 kernel: [ 549.328008] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:03 BXT-2 kernel: [ 549.328050] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:03 BXT-2 kernel: [ 549.328093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.328138] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:03 BXT-2 kernel: [ 549.328181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.328224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:03 BXT-2 kernel: [ 549.328266] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.328308] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:03 BXT-2 kernel: [ 549.328317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.328358] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:03 BXT-2 kernel: [ 549.328364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.328407] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:03 BXT-2 kernel: [ 549.329070] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:03 BXT-2 kernel: [ 549.329113] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:03 BXT-2 kernel: [ 549.329155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:03 BXT-2 kernel: [ 549.329197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:03 BXT-2 kernel: [ 549.329244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:03 BXT-2 kernel: [ 549.329286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:03 BXT-2 kernel: [ 549.329331] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:03 BXT-2 kernel: [ 549.329374] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:03 BXT-2 kernel: [ 549.329417] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.329847] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.329891] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:03 BXT-2 kernel: [ 549.329958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.330011] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.330054] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.330207] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:03 BXT-2 kernel: [ 549.330244] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:03 BXT-2 kernel: [ 549.330845] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:03 BXT-2 kernel: [ 549.331155] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.331195] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:03 BXT-2 kernel: [ 549.331252] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:03 BXT-2 kernel: [ 549.331701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.332036] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:03 BXT-2 kernel: [ 549.332080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:03 BXT-2 kernel: [ 549.332124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.332166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.332209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.332252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:03 BXT-2 kernel: [ 549.332295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:03 BXT-2 kernel: [ 549.332337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:03 BXT-2 kernel: [ 549.332380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:03 BXT-2 kernel: [ 549.332423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:03 BXT-2 kernel: [ 549.332954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:03 BXT-2 kernel: [ 549.332999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.333074] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:03 BXT-2 kernel: [ 549.333117] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:03 BXT-2 kernel: [ 549.334907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.334951] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:03 BXT-2 kernel: [ 549.334996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:03 BXT-2 kernel: [ 549.335898] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:03 BXT-2 kernel: [ 549.335944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:03 BXT-2 kernel: [ 549.336992] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:03 BXT-2 kernel: [ 549.338493] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:03 BXT-2 kernel: [ 549.339481] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:03 BXT-2 kernel: [ 549.339686] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:03 BXT-2 kernel: [ 549.339739] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:03 BXT-2 kernel: [ 549.339909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.356691] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.356738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.356783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.356827] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.356869] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.356913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.356956] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.356999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.357042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.357084] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.357126] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.357135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.357177] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.357183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.357226] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.357268] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.357311] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.357353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.357396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.357492] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.357534] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.357581] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.357624] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.357667] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.357710] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.357753] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.357820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.357874] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.357917] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.373110] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.390689] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.390802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.390889] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.391210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.391254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.391297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.391339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.391382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.391425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.391564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.391607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.391652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.391696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.391742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.391787] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.391848] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.391891] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.391944] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.391994] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.392040] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.392088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.392134] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.392178] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.392216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.392825] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.393780] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.393826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.393872] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.393915] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.393957] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.394001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.394044] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.394087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.394130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.394172] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.394214] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.394223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.394264] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.394270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.394313] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.394356] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.394399] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.394475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.394518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.394565] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.394607] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.394652] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.394696] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.394739] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.394782] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.394827] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.394893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.394947] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.394990] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.395139] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.395177] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.395512] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.395567] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.395609] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.395667] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.396437] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.396928] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.396973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.397017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.397059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.397104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.397147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.397190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.397232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.397275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.397318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.397365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.397409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.397529] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.397572] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.399262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.399308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.399357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.400306] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.400354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.401419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.403506] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.409957] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.410162] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.410215] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.410385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.427093] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.427140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.427185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.427229] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.427271] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.427315] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.427358] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.427401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.427506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.427550] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.427592] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.427601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.427644] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.427650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.427693] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.427737] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.427780] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.427823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.427866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.427912] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.427954] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.428000] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.428043] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.428087] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.428130] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.428173] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.428239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.428290] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.428334] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.443662] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.461823] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.461935] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.462024] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.462355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.462400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.462821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.462864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.462907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.462950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.462993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.463036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.463079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.463122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.463172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.463217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.463282] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.463325] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.463379] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.463428] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.463826] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.463874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.463925] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.463968] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.464007] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.465180] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.465914] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.465961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.466006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.466050] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.466093] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.466137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.466181] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.466224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.466267] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.466310] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.466351] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.466360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.466402] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.466820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.466880] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.466924] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.466967] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.467010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.467053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.467098] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.467141] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.467187] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.467230] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.467274] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.467318] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.467364] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.467431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.467782] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.467826] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.467982] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.468020] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.468318] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.468373] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.468413] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.468822] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.469083] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.469409] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.469823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.469868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.469911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.469954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.469997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.470040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.470082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.470126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.470169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.470219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.470264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.470340] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.470383] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.472214] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.472261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.472306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.473299] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.473347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.475061] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.476540] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.477569] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.477752] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.477805] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.477975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.494707] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.494754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.494799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.494843] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.494885] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.494929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.494972] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.495015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.495058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.495101] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.495142] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.495151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.495193] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.495199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.495243] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.495285] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.495328] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.495370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.495412] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.495507] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.495551] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.495598] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.495643] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.495689] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.495734] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.495780] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.495844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.495898] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.495944] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.511178] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.528762] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.528874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.528962] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.529287] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.529331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.529374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.529417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.529517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.529563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.529609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.529654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.529697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.529741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.529788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.529833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.529895] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.529937] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.529991] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.530041] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.530086] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.530133] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.530177] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.530221] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.530260] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.531430] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.532376] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.532421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.532512] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.532558] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.532600] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.532645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.532689] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.532732] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.532775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.532819] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.532861] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.532871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.532912] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.532919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.532963] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.533006] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.533049] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.533092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.533134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.533179] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.533222] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.533267] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.533311] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.533354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.533397] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.533464] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.533528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.533581] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.533624] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.533771] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.533809] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.534100] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.534153] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.534195] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.534252] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.534746] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.535078] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.535122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.535165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.535207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.535250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.535293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.535336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.535378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.535421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.535551] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.535600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.535645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.535722] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.535766] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.537296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.537342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.537386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.538223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.538266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.539015] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.539059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.540109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.542205] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.543204] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.543408] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.543502] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.543672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.560417] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.560527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.560574] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.560618] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.560660] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.560704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.560748] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.560791] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.560834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.560877] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.560918] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.560927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.560969] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.560975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.561018] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.561061] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.561103] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.561146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.561188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.561234] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.561277] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.561321] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.561365] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.561409] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.561505] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.561548] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.561617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.561673] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.561718] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.576807] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.594619] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.594732] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.594821] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.595144] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.595188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.595231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.595273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.595316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.595359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.595401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.595489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.595534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.595577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.595624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.595669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.595734] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.595776] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.595830] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.595879] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.595925] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.595971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.596016] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.596059] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.596098] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.596715] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.597683] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.597730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.597775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.597819] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.597861] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.597905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.597948] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.597991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.598034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.598077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.598118] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.598128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.598169] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.598175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.598218] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.598261] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.598304] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.598346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.598388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.598433] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.598519] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.598564] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.598608] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.598651] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.598694] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.598737] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.598799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.598853] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.598896] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.599043] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.599081] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.599371] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.599425] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.599486] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.599543] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.599979] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.600311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.600356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.600399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.600569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.600613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.600656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.600700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.600743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.600786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.600830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.600878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.600923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.600999] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.601042] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.603013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.603058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.603102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.603980] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.604026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.605161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.607255] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.608293] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.608704] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.608760] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.609544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.625438] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.625531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.625578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.625624] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.625666] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.625711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.625756] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.625802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.625845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.625887] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.625929] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.625939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.625980] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.625986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.626030] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.626074] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.626117] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.626159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.626201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.626247] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.626289] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.626335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.626377] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.626420] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.627038] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.627083] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.627153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.627208] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.627252] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.641908] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.659689] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.659802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.659890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.660220] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.660266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.660311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.660355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.660399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.660784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.660828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.660873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.660916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.660959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.661008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.661053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.661116] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.661158] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.661212] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.661266] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.661313] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.661359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.661405] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.661488] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.661527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.662074] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.662554] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.662602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.662649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.662693] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.662737] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.662781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.662825] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.662868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.662912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.662955] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.662997] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.663006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.663049] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.663056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.663099] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.663142] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.663185] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.663228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.663271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.663316] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.663358] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.663404] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.663471] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.663515] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.663558] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.663601] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.663665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.663719] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.663762] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.663909] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.663947] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.664237] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.664290] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.664332] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.664390] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.664899] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.665231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.665275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.665318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.665361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.665404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.665605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.665648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.665691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.665736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.665780] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.665829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.665875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.665950] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.665993] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.667595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.667641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.667687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.668495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.668540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.669282] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.669326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.670492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.672534] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.673587] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.673792] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.673845] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.676319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.690775] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.690821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.690866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.690909] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.690951] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.690995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.691038] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.691081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.691124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.691166] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.691207] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.691216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.691258] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.691263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.691306] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.691349] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.691391] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.691471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.691513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.691560] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.691602] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.691647] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.691691] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.691734] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.691777] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.691820] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.691882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.691932] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.691975] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.707176] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.725821] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.725934] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.726025] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.726393] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.726834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.726880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.726923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.726966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.727008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.727051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.727094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.727136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.727179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.727231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.727276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.727353] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.727397] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.727873] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.727925] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.727973] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.728021] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.728071] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.728114] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.728153] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.729324] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.730013] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.730060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.730106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.730149] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.730191] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.730236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.730279] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.730322] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.730365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.730408] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.730850] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.730860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.730902] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.730909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.730952] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.730996] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.731039] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.731082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.731124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.731170] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.731213] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.731259] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.731303] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.731346] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.731390] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.731751] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.731820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.731875] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.731918] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.732070] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.732108] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.732400] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.733039] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.733081] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.733138] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.733747] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.734077] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.734121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.734165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.734208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.734251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.734293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.734336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.734379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.734422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.734843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.734895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.734940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.735016] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.735059] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.737106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.737153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.737197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.737979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.738023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.738755] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.738799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.739969] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.742061] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.743072] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.743265] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.743318] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.743518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.760164] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.760211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.760256] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.760300] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.760342] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.760386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.760429] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.760538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.760582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.760626] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.760668] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.760677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.760719] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.760725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.760768] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.760811] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.760854] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.760897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.760941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.760987] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.761029] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.761075] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.761118] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.761163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.761206] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.761249] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.761319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.761372] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.761415] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.776656] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.794710] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.794825] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.794913] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.795240] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.795284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.795328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.795371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.795413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.795832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.795875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.795919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.795962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.796006] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.796056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.796101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.796164] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.796207] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.796262] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.796311] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.796357] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.796403] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.796859] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.796903] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.796941] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.798112] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.798829] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.798876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.798921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.798965] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.799007] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.799051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.799095] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.799138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.799181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.799224] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.799265] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.799274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.799317] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.799323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.799367] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.799410] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.799903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.799946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.799989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.800036] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.800078] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.800124] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.800168] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.800213] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.800257] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.800300] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.800367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.800421] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.800801] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.800960] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.800997] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.801291] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.801346] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.801386] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.801802] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.802073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.802397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.802763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.802808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.802850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.802894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.802938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.802980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.803023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.803066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.803109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.803160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.803205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.803280] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.803323] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.805140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.805187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.805232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.806289] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.806338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.807581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.809713] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.810776] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.810993] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.811048] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.811219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.827931] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.827980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.828026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.828070] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.828112] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.828156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.828200] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.828243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.828286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.828329] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.828371] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.828381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.828422] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.828520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.828574] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.828618] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.828661] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.828704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.828746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.828791] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.828834] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.828879] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.828922] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.828965] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.829007] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.829051] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.829118] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.829171] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.829215] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.844398] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.862781] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.862894] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.862982] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.863307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.863351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.863394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.863496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.863539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.863584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.863627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.863670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.863712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.863755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.863802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.863847] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.863910] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.863952] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.864006] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.864057] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.864104] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.864150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.864196] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.864240] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.864280] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.864868] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.865395] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.865475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.865521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.865564] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.865606] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.865650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.865695] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.865738] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.865781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.865823] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.865865] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.865874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.865916] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.865922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.865964] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.866007] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.866049] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.866092] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.866134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.866179] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.866220] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.866265] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.866308] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.866350] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.866393] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.866469] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.866536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.866590] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.866634] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.866784] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.866822] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.867112] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.867165] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.867207] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.867264] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.868074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.868398] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.868505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.868550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.868594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.868639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.868684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.868729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.868772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.868817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.868863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.868910] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.868958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.869033] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.869077] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.870878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.870923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.870967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.871910] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.871956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.873045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.875150] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.876230] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.876652] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.876707] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.876878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.893442] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.893529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.893575] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.893619] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.893661] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.893705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.893750] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.893793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.893836] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.893879] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.893921] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.893930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.893971] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.893977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.894020] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.894063] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.894105] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.894148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.894190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.894235] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.894277] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.894322] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.894365] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.894408] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.895513] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.895558] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.895630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.895685] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.895728] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.909816] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.927789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.927905] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.927993] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.928316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.928361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.928404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.928503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.928546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.928592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.928635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.928679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.928722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.928766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.928813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.928858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.928919] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.928962] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.929015] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.929065] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.929110] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.929156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.929202] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.929245] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.929284] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.929860] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.930279] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.930325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.930371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.930415] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.930504] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.930550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.930594] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.930637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.930681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.930724] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.930767] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.930776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.930818] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.930824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.930868] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.930911] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.930955] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.930997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.931040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.931086] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.931128] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.931173] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.931217] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.931260] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.931304] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.931347] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.931412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.931529] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.931572] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.931725] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.931763] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.932054] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.932107] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.932148] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.932205] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.933012] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.933341] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.933385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.933428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.933537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.933581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.933624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.933667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.933711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.933754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.933798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.933846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.933890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.933965] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.934009] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.935814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.935859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.935903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 549.936710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.936753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 549.937602] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 549.937646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 549.938839] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 549.940932] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 549.941929] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.942112] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.942165] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.942334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.959029] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.959076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.959120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.959164] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.959206] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.959250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.959292] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.959335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.959378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.959420] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.959988] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.959998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.960040] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.960046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.960089] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.960131] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.960174] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.960217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.960258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.960304] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.960346] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.960391] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.960922] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.960966] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.961009] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.961052] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.961121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.961176] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.961219] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.975668] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.993701] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 549.993813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.993901] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.994224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.994268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.994312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.994354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.994397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.994497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 549.994900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.994944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.994988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 549.995031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 549.995081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 549.995126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.995189] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.995232] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.995286] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.995335] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 549.995381] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 549.995428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.995558] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.995601] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 549.995640] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 549.996206] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.996675] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 549.996721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 549.996766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 549.996812] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 549.996857] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 549.996902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.996945] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 549.996990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.997034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 549.997076] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.997118] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 549.997127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.997168] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 549.997298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.997353] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 549.997397] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 549.997475] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 549.997518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 549.997560] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 549.997606] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 549.997649] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 549.997694] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 549.997738] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 549.997782] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.997825] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.997868] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 549.997936] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.997991] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 549.998034] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 549.998179] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 549.998216] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 549.998526] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 549.998581] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.998623] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 549.998680] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 549.999380] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.999795] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 549.999841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 549.999885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 549.999928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 549.999970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.000013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.000056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.000099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.000141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.000185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.000232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.000277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.000353] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.000396] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.002163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.002208] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.002254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 550.003154] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 550.003199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 550.004509] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 550.006609] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 550.007689] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.007885] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.007939] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.008109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.024841] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.024888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.024933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.024977] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.025019] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.025062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.025106] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.025148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.025191] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.025233] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.025275] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.025284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.025326] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.025331] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.025374] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.025417] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.026169] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.026212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.026254] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.026299] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.026341] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.026387] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.026430] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.026785] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.026828] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.026871] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.026937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.026990] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.027033] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.041253] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.059842] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.059954] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.060042] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.060364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.060409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.060766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.060809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.060852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.060895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.060938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.060980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.061023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.061066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.061114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.061158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.061221] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.061263] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.061316] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.061365] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.061410] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.062086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.062136] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.062179] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 550.062217] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 550.063387] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.064340] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.064386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.064431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.064697] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.064739] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.064784] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.064829] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.064872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.064914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.064956] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.064998] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.065007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.065049] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.065055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.065098] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.065141] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.065183] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.065225] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.065267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.065312] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.065354] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.065399] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.066145] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.066188] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.066231] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.066274] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.066345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.066400] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.066763] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.066920] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.066957] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.067245] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 550.067299] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.067339] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.067396] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.067997] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.068315] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.068359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.068402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.068699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.068743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.068785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.068828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.068871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.068914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.068957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.069005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.069049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.069123] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.069166] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.070937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.070982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.071027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 550.071904] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 550.071949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 550.072998] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 550.075105] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 550.076135] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.076322] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.076375] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.076592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.093265] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.093312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.093357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.093400] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.093503] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.093550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.093594] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.093637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.093681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.093723] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.093766] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.093775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.093817] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.093824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.093867] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.093910] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.093953] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.093996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.094039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.094084] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.094126] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.094171] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.094215] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.094258] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.094302] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.094345] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.094409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.094483] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.094527] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.109777] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.127795] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.127909] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.127996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.128411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.128516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.128560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.128603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.128647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.128690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.128734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.128779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.128822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.128865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.128913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.128958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.129024] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.129066] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.129120] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.129172] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.129220] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.129266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.129314] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.129357] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 550.129398] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 550.129977] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.130401] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.130500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.130546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.130590] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.130632] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.130677] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.130722] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.130766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.130810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.130853] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.130895] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.130904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.130946] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.130952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.130996] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.131039] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.131083] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.131125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.131168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.131213] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.131256] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.131301] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.131345] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.131388] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.131432] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.131503] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.131568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.131622] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.131665] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.131816] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.131854] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.132144] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 550.132197] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.132239] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.132296] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.132782] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.133112] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.133155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.133200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.133243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.133287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.133333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.133376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.133418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.133526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.133570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.133616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.133661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.133738] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.133783] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.135232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.135277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.135322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 550.136251] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 550.136297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 550.137438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 550.139585] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 550.140673] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.140887] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.140941] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.141113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.157835] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.157881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.157926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.157970] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.158012] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.158055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.158098] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.158141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.158184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.158226] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.158268] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.158276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.158318] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.158324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.158367] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.158409] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.159186] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.159229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.159271] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.159317] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.159358] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.159403] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.159786] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.159829] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.159872] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.159915] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.159983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.160037] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.160079] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.174270] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.192776] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.192889] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.192979] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.193309] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.193353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.193396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.193800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.193843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.193887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.193929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.193972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.194015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.194058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.194109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.194153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.194218] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.194261] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.194315] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.194366] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.194412] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.195120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.195172] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.195216] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 550.195255] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 550.196425] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.196878] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.196923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.196969] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.197013] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.197055] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.197099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.197142] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.197185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.197228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.197271] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.197312] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.197321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.197363] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.197369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.197412] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.198143] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.198187] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.198230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.198272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.198318] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.198360] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.198405] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.198827] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.198871] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.198914] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.198957] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.199027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.199082] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.199125] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.199287] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.199325] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.200079] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 550.200395] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.200634] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.200693] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.201006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.201328] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.201372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.201415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.201823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.201867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.201910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.201953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.201996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.202039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.202082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.202132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.202177] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.202253] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.202296] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.204627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.204674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.204719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 550.205980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.206025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.207187] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 550.207234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 550.208750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 550.210561] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 550.211687] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.211964] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.212039] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.212231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.228904] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.228952] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.228998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.229041] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.229084] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.229128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.229172] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.229215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.229258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.229300] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.229342] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.229351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.229393] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.230076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.230135] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.230179] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.230223] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.230266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.230309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.230355] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.230398] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.230494] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.230538] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.230582] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.230625] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.230669] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.230740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.230794] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.230837] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.245294] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.263740] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.263854] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.263943] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.264269] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.264313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.264357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.264400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.264830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.264875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.264918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.264962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.265005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.265048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.265099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.265147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.265211] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.265254] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.265308] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.265358] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.265403] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.265839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.265890] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.265933] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 550.265972] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 550.267216] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.267939] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.267985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.268031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.268075] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.268117] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.268161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.268205] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.268248] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.268291] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.268333] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.268375] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.268384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.268426] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.268762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.268822] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.268865] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.268909] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.268951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.268994] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.269040] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.269083] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.269128] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.269172] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.269216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.269259] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.269302] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.269368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.269422] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.269833] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.269990] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.270028] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.270321] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 550.270374] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.270415] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.270808] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.271074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.271400] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.271759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.271804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.271847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.271890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.271933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.271976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.272019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.272062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.272104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.272154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.272199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.272274] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.272317] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.274076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.274123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.274168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 550.275194] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 550.275242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 550.276634] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 550.278562] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 550.279603] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.279786] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.279840] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.280009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.296737] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.296783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.296829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.296873] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.296915] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.296959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.297002] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.297045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.297088] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.297129] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.297171] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.297180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.297222] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.297228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.297270] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.297313] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.297355] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.297398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.297488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.297536] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.297579] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.297627] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.297673] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.297717] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.297763] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.297807] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.297867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.297918] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.297961] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.313162] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.331868] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.332004] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.332096] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.332420] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.332816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.332864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.332908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.332951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.332994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.333036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.333079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.333122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.333165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.333216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.333261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.333326] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.333369] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.333424] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.334100] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.334150] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.334196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.334246] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.334289] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:04 BXT-2 kernel: [ 550.334328] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:04 BXT-2 kernel: [ 550.335524] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.335959] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:04 BXT-2 kernel: [ 550.336004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:04 BXT-2 kernel: [ 550.336050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:04 BXT-2 kernel: [ 550.336094] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:04 BXT-2 kernel: [ 550.336136] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:04 BXT-2 kernel: [ 550.336181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.336224] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:04 BXT-2 kernel: [ 550.336267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.336310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:04 BXT-2 kernel: [ 550.336352] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.336394] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:04 BXT-2 kernel: [ 550.336986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.337043] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:04 BXT-2 kernel: [ 550.337049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.337093] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:04 BXT-2 kernel: [ 550.337136] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:04 BXT-2 kernel: [ 550.337179] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:04 BXT-2 kernel: [ 550.337221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:04 BXT-2 kernel: [ 550.337264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:04 BXT-2 kernel: [ 550.337309] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:04 BXT-2 kernel: [ 550.337351] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:04 BXT-2 kernel: [ 550.337397] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:04 BXT-2 kernel: [ 550.337952] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:04 BXT-2 kernel: [ 550.337997] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.338040] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.338083] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:04 BXT-2 kernel: [ 550.338153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.338208] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.338251] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.338417] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:04 BXT-2 kernel: [ 550.338845] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:04 BXT-2 kernel: [ 550.339141] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:04 BXT-2 kernel: [ 550.339200] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.339240] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:04 BXT-2 kernel: [ 550.339297] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:04 BXT-2 kernel: [ 550.339918] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.340244] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:04 BXT-2 kernel: [ 550.340288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:04 BXT-2 kernel: [ 550.340331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.340374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.340417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.340770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:04 BXT-2 kernel: [ 550.340813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:04 BXT-2 kernel: [ 550.340856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:04 BXT-2 kernel: [ 550.340899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:04 BXT-2 kernel: [ 550.340942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:04 BXT-2 kernel: [ 550.340991] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:04 BXT-2 kernel: [ 550.341035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.341110] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:04 BXT-2 kernel: [ 550.341153] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:04 BXT-2 kernel: [ 550.342911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.342955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:04 BXT-2 kernel: [ 550.343000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:04 BXT-2 kernel: [ 550.343877] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:04 BXT-2 kernel: [ 550.343921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:04 BXT-2 kernel: [ 550.345012] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:04 BXT-2 kernel: [ 550.347108] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:04 BXT-2 kernel: [ 550.348129] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:04 BXT-2 kernel: [ 550.348320] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:04 BXT-2 kernel: [ 550.348374] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:04 BXT-2 kernel: [ 550.348822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.365248] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.365295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.365340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.365384] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.365426] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.365803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.365848] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.365891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.365934] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.365976] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.366018] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.366027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.366069] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.366074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.366117] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.366160] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.366202] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.366244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.366287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.366332] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.366373] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.366418] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.367112] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.367156] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.367199] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.367242] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.367313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.367366] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.367409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.381752] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.399692] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.399805] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.399893] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.400212] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.400256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.400299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.400342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.400386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.400429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.400575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.400619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.400661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.400704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.400751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.400796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.400857] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.400900] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.400953] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.401002] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.401048] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.401095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.401140] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.401184] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.401223] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.401818] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.402224] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.402269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.402314] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.402358] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.402400] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.402515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.402559] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.402602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.402645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.402688] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.402731] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.402740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.402782] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.402788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.402832] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.402876] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.402919] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.402962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.403004] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.403052] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.403095] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.403141] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.403184] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.403227] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.403271] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.403314] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.403380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.403470] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.403514] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.403670] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.403708] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.403997] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.404050] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.404093] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.404150] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.404853] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.405173] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.405216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.405261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.405303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.405346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.405391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.405482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.405528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.405573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.405618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.405666] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.405930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.406006] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.406049] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.407523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.407567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.407611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.408371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.408413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.409195] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.409239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.410493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.412602] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.413635] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.413816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.413870] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.414040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.430790] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.430837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.430882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.430926] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.430968] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.431011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.431055] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.431097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.431140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.431183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.431224] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.431233] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.431274] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.431280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.431323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.431366] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.431409] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.432171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.432214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.432259] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.432301] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.432346] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.432390] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.432734] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.432778] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.432821] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.432889] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.432944] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.432986] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.447221] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.464876] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.464988] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.465077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.465400] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.465520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.465565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.465608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.465651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.465695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.465738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.465781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.465824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.465868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.465916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.465962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.466031] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.466074] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.466128] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.466177] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.466223] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.466270] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.466316] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.466359] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.466398] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.466979] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.467408] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.467504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.467556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.467601] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.467643] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.467688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.467733] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.467776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.467820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.467863] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.467905] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.467915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.467957] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.467963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.468007] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.468050] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.468093] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.468136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.468179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.468224] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.468267] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.468313] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.468356] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.468400] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.468471] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.468514] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.468586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.468642] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.468687] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.468859] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.468897] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.469186] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.469240] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.469282] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.469339] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.469894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.470215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.470259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.470302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.470345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.470387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.470430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.470530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.470825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.470869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.470914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.470964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.471010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.471085] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.471129] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.473072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.473118] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.473163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.473948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.473992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.474802] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.474847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.475881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.477977] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.478979] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.479183] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.479237] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.479406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.496193] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.496240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.496286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.496330] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.496373] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.496416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.496970] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.497020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.497070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.497119] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.497168] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.497178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.497227] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.497233] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.497283] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.497333] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.497382] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.497431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.498077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.498130] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.498179] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.498232] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.498282] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.498332] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.498382] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.498432] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.498941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.499005] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.499055] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.512624] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.529716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.529829] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.529918] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.530245] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.530290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.530333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.530376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.530419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.531207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.531251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.531294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.531337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.531380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.531430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.531870] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.531936] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.531979] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.532033] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.532083] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.532129] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.532175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.532221] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.532264] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.532303] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.533646] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.534079] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.534124] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.534169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.534213] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.534256] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.534300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.534343] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.534386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.534429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.534628] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.534671] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.534680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.534722] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.534729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.534773] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.534817] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.534860] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.534904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.534947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.534993] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.535036] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.535081] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.535125] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.535169] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.535213] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.535257] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.535321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.535375] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.535419] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.535701] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.535739] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.536030] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.536084] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.536126] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.536185] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.537105] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.537431] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.537770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.537815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.537858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.537901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.537944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.537987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.538030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.538073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.538116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.538165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.538210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.538285] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.538328] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.541026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.541288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.541334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.542364] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.542411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.543611] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.545523] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.546620] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.546827] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.546881] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.547051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.563840] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.563887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.563933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.563977] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.564019] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.564063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.564107] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.564150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.564193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.564235] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.564278] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.564286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.564328] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.564334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.564377] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.564420] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.564640] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.564684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.564728] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.564773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.564817] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.564862] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.564906] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.564950] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.564994] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.565037] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.565101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.565154] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.565198] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.580297] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.598881] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.598994] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.599083] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.599402] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.599838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.599883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.599926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.599969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.600012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.600055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.600098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.600141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.600184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.600233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.600278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.600341] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.600384] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.600801] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.600857] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.600905] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.600953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.601001] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.601045] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.601085] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.602254] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.602897] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.603020] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.603066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.603110] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.603153] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.603197] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.603242] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.603284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.603328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.603370] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.603412] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.603768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.603827] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.603835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.603878] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.603922] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.603965] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.604008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.604051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.604098] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.604141] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.604187] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.604231] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.604275] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.604318] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.604362] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.604429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.604840] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.604884] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.605042] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.605079] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.605369] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.605423] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.605744] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.605803] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.606106] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.606432] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.606787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.606831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.606874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.606917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.606960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.607003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.607045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.607088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.607132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.607180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.607225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.607300] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.607343] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.609113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.609158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.609203] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.610268] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.610313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.611536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.613637] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.614675] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.614869] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.614923] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.615092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.631907] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.631954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.631999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.632042] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.632085] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.632129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.632172] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.632215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.632259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.632301] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.632343] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.632352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.632394] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.632775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.632834] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.632879] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.632923] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.632967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.633010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.633055] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.633098] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.633144] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.633188] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.633231] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.633276] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.633319] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.633387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.633849] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.633895] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.648319] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.666904] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.667017] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.667106] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.667424] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.667871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.667916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.667959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.668002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.668045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.668088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.668131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.668174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.668217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.668265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.668310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.668374] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.668416] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.668786] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.668839] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.668887] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.668935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.668984] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.669028] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.669068] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.670241] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.670782] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.670828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.670873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.670917] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.670959] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.671003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.671047] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.671089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.671133] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.671175] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.671217] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.671225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.671267] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.671273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.671316] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.671359] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.671402] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.671629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.671672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.671718] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.671761] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.671806] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.671850] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.671894] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.671937] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.671981] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.672047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.672102] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.672145] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.672294] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.672332] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.672853] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.673245] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.673286] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.673343] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.673758] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.674080] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.674123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.674167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.674210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.674253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.674296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.674338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.674381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.674424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.674610] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.674659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.674707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.674782] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.674826] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.676276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.676319] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.676364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.677149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.677192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.677944] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.677989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.679040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.681136] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.682166] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.682374] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.682428] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.682637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.699403] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.699503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.699549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.699593] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.699635] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.699679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.699723] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.699766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.699809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.699852] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.699894] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.699903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.699945] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.699951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.699994] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.700036] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.700079] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.700122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.700164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.700209] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.700251] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.700295] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.700338] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.700381] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.700424] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.700507] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.700575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.700631] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.700677] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.715817] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.733873] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.733986] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.734074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.734397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.734507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.734555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.734598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.734641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.734685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.734729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.734772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.734816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.734859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.734907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.734952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.735015] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.735058] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.735112] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.735162] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.735208] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.735254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.735300] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.735344] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.735383] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.735969] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.736389] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.736468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.736514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.736562] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.736604] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.736649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.736694] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.736737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.736781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.736824] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.736867] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.736876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.736919] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.736925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.736969] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.737012] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.737055] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.737098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.737141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.737187] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.737229] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.737275] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.737319] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.737362] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.737406] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.737468] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.737530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.737584] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.737627] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.737779] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.737817] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.738107] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.738161] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.738203] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.738260] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.738569] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.738886] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.738930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.738973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.739016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.739059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.739102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.739145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.739188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.739231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.739274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.739320] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.739365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.739469] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.739513] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.741591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.741637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.741682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.742434] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.742652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.743377] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.743422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.744600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.745970] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.747042] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.747238] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.747292] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.747605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.764234] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.764281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.764327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.764371] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.764413] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.764635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.764681] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.764725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.764768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.764812] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.764854] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.764865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.764906] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.764913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.764957] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.765001] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.765044] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.765088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.765130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.765176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.765219] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.765264] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.765308] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.765351] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.765395] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.765622] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.765688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.765743] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.765787] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.780701] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.799205] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.799317] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.799405] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.799896] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.799941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.799985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.800028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.800071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.800114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.800157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.800200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.800243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.800286] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.800332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.800377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.800564] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.800608] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.800663] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.800714] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.800761] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.800808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.800854] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.800898] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.800937] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.802101] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.802615] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.802660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.802706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.802751] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.802794] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.802839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.802883] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.802927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.802972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.803015] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.803057] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.803067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.803110] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.803116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.803160] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.803203] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.803248] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.803291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.803334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.803380] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.803423] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.803607] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.803652] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.803695] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.803739] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.803783] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.803846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.803901] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.803945] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.804092] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.804130] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.804419] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.805050] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.805090] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.805147] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.806408] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.806765] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.806810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.806853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.806896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.806939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.806982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.807025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.807068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.807111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.807154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.807202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.807247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.807321] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.807364] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.808824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.808868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.808912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.809678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.809722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.810435] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.810524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.811568] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.813664] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.814698] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.814900] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.814953] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.815123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.831921] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.831969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.832015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.832060] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.832103] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.832147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.832191] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.832235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.832279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.832322] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.832365] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.832374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.832416] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.832488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.832536] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.832589] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.832635] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.832681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.832726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.832773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.832818] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.832865] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.832912] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.832957] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.833001] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.833046] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.833114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.833167] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.833212] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.848350] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.866769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.866881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.866969] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.867291] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.867335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.867379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.867421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.867520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.867565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.867608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.867651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.867694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.867738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.867784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.867831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.867895] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.867937] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.867991] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.868043] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.868089] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.868136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.868181] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.868238] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.868277] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.868857] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.869269] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.869315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.869360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.869406] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.869483] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.869528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.869572] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.869615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.869659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.869701] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.869744] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.869753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.869795] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.869802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.869845] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.869888] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.869932] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.869974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.870017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.870062] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.870104] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.870149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.870193] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.870236] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.870279] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.870322] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.870386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.870457] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.870500] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.870782] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.870820] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.871110] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.871163] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.871205] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.871264] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.871775] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.872370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.872415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.872524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.872567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.872613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.872656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.872698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.872741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.872785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.872829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.872879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.872924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.873002] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.873045] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.874557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.874602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.874647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.875413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.875491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.876213] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.876256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.877298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.879392] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.880394] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.880638] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.880692] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.880864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.897711] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.897758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.897803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.897847] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.897890] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.897934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.897978] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.898021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.898064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.898106] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.898148] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.898158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.898200] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.898206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.898249] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.898291] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.898334] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.898377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.898419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.898502] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.898549] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.898599] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.898645] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.898691] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.898738] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.898785] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.898851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.898903] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.898949] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.914088] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.932619] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.932733] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.932822] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.933150] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.933194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.933237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.933280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.933325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.933368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.933410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.933506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.933552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.933597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.933645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.933692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.933757] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.933801] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.933857] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.933907] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.933953] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.933999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.934045] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.934089] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.934128] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.934708] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.935139] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.935185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.935230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.935274] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.935316] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.935360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.935403] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.935485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.935529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.935577] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.935621] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.935634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.935679] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.935687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.935731] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.935776] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.935821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.935865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.935908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.935953] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.935995] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.936040] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.936084] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.936127] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.936171] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.936214] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.936276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.936330] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.936373] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.936555] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 550.936593] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.936888] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 550.936942] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.936984] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.937042] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.937340] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.937665] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.937709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.937752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.937795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.937838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.937880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.937923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.937966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.938008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.938051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.938097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.938142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.938216] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.938259] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.939738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.939782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.939826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 550.940585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.940628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 550.941362] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 550.941405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 550.942512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 550.944605] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 550.945607] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.945814] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.945868] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.946038] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.962880] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 550.962927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 550.962972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 550.963016] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 550.963058] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 550.963102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.963146] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 550.963189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.963232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 550.963274] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.963316] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 550.963325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.963366] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 550.963372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.963415] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 550.963494] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 550.963537] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 550.963584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 550.963630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 550.963679] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 550.963724] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 550.963770] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 550.963816] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 550.963862] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.963908] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.963953] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 550.964016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.964069] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.964113] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.979279] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 550.997819] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 550.997931] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.998019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.998337] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 550.998381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 550.998425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.998521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.998568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.998611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 550.998654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 550.998698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 550.998742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 550.998785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 550.998833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 550.998880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.998942] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 550.998985] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.999039] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 550.999089] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 550.999135] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 550.999181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 550.999226] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 550.999270] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 550.999309] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 550.999896] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.000323] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.000368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.000413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.000493] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.000536] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.000582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.000625] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.000669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.000713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.000756] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.000798] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.000807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.000850] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.000856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.000901] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.000945] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.000988] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.001031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.001075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.001120] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.001163] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.001208] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.001252] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.001295] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.001339] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.001382] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.001468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.001523] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.001566] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.001718] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.001756] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.002046] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 551.002100] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.002141] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.002199] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.002517] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.002836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.002880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.002923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.002966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.003009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.003051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.003094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.003137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.003179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.003223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.003269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.003313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.003386] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.003429] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.004896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.004944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.004989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 551.005809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.005853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.006574] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 551.006618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 551.007683] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 551.009773] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 551.010787] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.010991] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.011044] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.011212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.027999] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.028046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.028091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.028135] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.028177] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.028221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.028265] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.028308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.028351] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.028393] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.028508] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.028519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.028560] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.028570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.028614] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.028657] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.028700] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.028743] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.028786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.028832] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.028874] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.028919] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.028962] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.029006] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.029049] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.029093] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.029159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.029213] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.029256] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.044450] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.063032] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.063145] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.063232] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.063561] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.063606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.063650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.063694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.063738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.063781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.063825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.063869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.063913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.063956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.064003] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.064048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.064117] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.064160] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.064215] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.064265] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.064313] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.064361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.064407] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.064475] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 551.064514] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 551.065062] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.065516] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.065561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.065607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.065652] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.065695] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.065739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.065784] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.065827] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.065871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.065914] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.065957] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.065966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.066009] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.066015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.066059] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.066102] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.066146] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.066190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.066234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.066279] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.066322] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.066370] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.066413] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.066482] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.066529] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.066574] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.066638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.066693] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.066739] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.066899] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.066938] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.067228] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 551.067282] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.067324] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.067382] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.067709] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.068038] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.068082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.068126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.068168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.068211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.068254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.068297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.068340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.068383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.068426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.068518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.068564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.068642] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.068686] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.070128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.070171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.070215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 551.071014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.071057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.071787] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 551.071830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 551.072877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 551.074968] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 551.075999] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.076209] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.076262] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.076431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.093226] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.093273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.093318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.093361] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.093404] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.093515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.093564] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.093610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.093656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.093699] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.093742] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.093753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.093796] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.093802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.093845] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.093888] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.093931] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.093973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.094015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.094060] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.094102] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.094147] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.094193] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.094236] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.094280] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.094324] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.094388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.094475] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.094520] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.109680] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.128190] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.128303] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.128390] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.128772] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.128816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.128861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.128908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.128951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.128994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.129038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.129081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.129124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.129168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.129214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.129260] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.129322] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.129365] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.129419] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.129498] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.129544] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.129591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.129637] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.129681] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 551.129720] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 551.130267] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.130725] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.130772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.130819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.130864] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.130906] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.130951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.130996] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.131040] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.131084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.131127] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.131170] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.131180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.131222] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.131229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.131273] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.131316] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.131359] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.131402] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.131491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.131537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.131580] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.131626] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.131670] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.131714] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.131757] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.131801] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.131870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.131925] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.131969] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.132132] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.132170] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.132484] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 551.132539] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.132581] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.132639] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.132926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.133252] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.133296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.133340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.133383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.133426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.133517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.133564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.133608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.133651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.133695] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.133745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.133790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.133864] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.133908] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.135350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.135394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.135478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 551.136237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.136280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.137013] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 551.137057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 551.138097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 551.140187] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 551.141246] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.141432] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.141524] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.141698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.158508] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.158556] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.158602] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.158646] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.158688] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.158732] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.158777] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.158820] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.158864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.158906] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.158948] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.158957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.158999] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.159005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.159048] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.159091] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.159134] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.159176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.159218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.159263] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.159305] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.159349] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.159392] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.159486] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.159534] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.159580] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.159647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.159703] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.159746] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.174868] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.193400] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.193563] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.193652] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.193975] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.194019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.194062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.194105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.194148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.194191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.194234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.194277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.194320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.194363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.194409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.194487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.194558] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.194601] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.194657] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.194707] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.194752] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.194798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.194843] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.194887] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 551.194927] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 551.195499] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.195923] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.195969] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.196015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.196059] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.196102] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.196146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.196190] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.196234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.196277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.196321] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.196363] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.196373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.196414] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.196451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.196496] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.196541] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.196587] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.196634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.196679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.196726] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.196772] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.197557] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.197605] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.197649] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.197693] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.197736] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.197809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.197865] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.197908] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.198038] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.198076] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.198369] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 551.198423] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.198774] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.198834] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.199540] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.199876] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.199920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.199963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.200006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.200049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.200092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.200135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.200177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.200220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.200263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.200311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.200355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.200429] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.200510] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.201975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.202022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.202066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 551.202999] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 551.203044] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 551.204107] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 551.205503] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 551.206614] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.206806] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.206859] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.207030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.223898] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.223945] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.223991] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.224035] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.224078] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.224122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.224165] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.224208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.224251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.224293] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.224335] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.224344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.224386] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.224392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.224478] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.224526] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.224572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.224618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.224661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.224709] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.224753] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.224800] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.224847] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.224891] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.225341] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.225387] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.225749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.225805] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.225849] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.240273] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.258789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.258903] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.258991] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.259317] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.259361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.259404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.259506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.259945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.259989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.260031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.260074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.260117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.260160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.260209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.260254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.260319] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.260361] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.260415] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.260512] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.260562] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.260613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.260660] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.260951] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 551.260992] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 551.261575] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.262142] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.262187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.262233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.262277] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.262319] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.262364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.262407] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.262486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.262532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.262577] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.262622] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.262635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.262679] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.262886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.262940] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.262984] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.263028] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.263071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.263114] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.263160] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.263204] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.263249] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.263293] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.263337] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.263381] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.263424] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.263517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.263573] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.263887] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.264045] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.264083] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.264372] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 551.264425] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.264497] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.264557] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.265027] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.265351] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.265395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.265486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.265534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.265579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.265809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.265852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.265895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.265938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.265981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.266029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.266074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.266148] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.266191] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.267743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.267788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.267832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 551.268773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.268817] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.269672] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 551.269718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 551.270914] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 551.273015] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 551.274039] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.274249] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.274303] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.274532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.291279] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.291326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.291371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.291415] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.291529] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.291573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.291840] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.291884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.291928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.291972] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.292014] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.292024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.292066] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.292073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.292117] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.292160] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.292204] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.292247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.292290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.292336] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.292379] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.292424] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.292509] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.292552] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.292596] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.292640] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.292707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.292760] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.292804] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.307713] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.326228] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.326341] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.326428] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.326933] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.326978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.327022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.327065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.327108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.327151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.327194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.327237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.327279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.327322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.327369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.327414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.327543] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.327827] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.327883] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.327934] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.327983] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.328031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.328078] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.328123] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:05 BXT-2 kernel: [ 551.328162] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:05 BXT-2 kernel: [ 551.328752] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.329343] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:05 BXT-2 kernel: [ 551.329387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:05 BXT-2 kernel: [ 551.329433] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:05 BXT-2 kernel: [ 551.329512] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:05 BXT-2 kernel: [ 551.329555] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:05 BXT-2 kernel: [ 551.329605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.329652] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:05 BXT-2 kernel: [ 551.329698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.329743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:05 BXT-2 kernel: [ 551.330139] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.330183] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:05 BXT-2 kernel: [ 551.330194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.330236] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:05 BXT-2 kernel: [ 551.330243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.330288] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:05 BXT-2 kernel: [ 551.330332] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:05 BXT-2 kernel: [ 551.330376] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:05 BXT-2 kernel: [ 551.330419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:05 BXT-2 kernel: [ 551.330492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:05 BXT-2 kernel: [ 551.330537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:05 BXT-2 kernel: [ 551.330580] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:05 BXT-2 kernel: [ 551.330631] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:05 BXT-2 kernel: [ 551.330677] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:05 BXT-2 kernel: [ 551.330723] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.330769] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.330816] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:05 BXT-2 kernel: [ 551.330884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.331211] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.331255] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.331412] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:05 BXT-2 kernel: [ 551.331483] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:05 BXT-2 kernel: [ 551.331937] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:05 BXT-2 kernel: [ 551.332398] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.332472] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:05 BXT-2 kernel: [ 551.332533] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:05 BXT-2 kernel: [ 551.333027] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.333347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:05 BXT-2 kernel: [ 551.333391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:05 BXT-2 kernel: [ 551.333484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.333533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.333579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.333624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:05 BXT-2 kernel: [ 551.333962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:05 BXT-2 kernel: [ 551.334006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:05 BXT-2 kernel: [ 551.334049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:05 BXT-2 kernel: [ 551.334093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:05 BXT-2 kernel: [ 551.334142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:05 BXT-2 kernel: [ 551.334187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.334263] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:05 BXT-2 kernel: [ 551.334306] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:05 BXT-2 kernel: [ 551.335875] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.335920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.335964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:05 BXT-2 kernel: [ 551.336755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.336798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:05 BXT-2 kernel: [ 551.337520] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:05 BXT-2 kernel: [ 551.337566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:05 BXT-2 kernel: [ 551.338820] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:05 BXT-2 kernel: [ 551.340924] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:05 BXT-2 kernel: [ 551.341961] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:05 BXT-2 kernel: [ 551.342154] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:05 BXT-2 kernel: [ 551.342208] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:05 BXT-2 kernel: [ 551.342377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.359170] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.359220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.359265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.359309] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.359351] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.359395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.359511] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.359929] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.359973] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.360017] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.360060] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.360069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.360111] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.360118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.360161] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.360205] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.360249] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.360292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.360335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.360381] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.360424] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.360504] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.360552] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.360599] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.360644] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.360691] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.360760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.360830] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.360874] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.375634] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.393798] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.393913] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.394002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.394331] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.394375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.394419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.394547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.394590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.394634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.394676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.394719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.394762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.394805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.394853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.394897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.394960] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.395003] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.395057] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.395107] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.395153] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.395200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.395246] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.395288] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.395327] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.395923] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.396890] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.396937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.396983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.397027] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.397069] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.397114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.397159] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.397202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.397245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.397288] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.397330] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.397338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.397380] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.397386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.397429] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.397501] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.397544] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.397587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.397629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.397675] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.397717] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.397763] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.397806] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.397848] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.397891] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.397934] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.398000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.398056] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.398099] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.400661] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.400701] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.400992] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.401047] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.401087] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.401144] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.401406] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.402351] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.402396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.402851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.402895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.402938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.402981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.403024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.403066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.403109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.403152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.403203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.403248] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.403324] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.403367] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.405646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.405692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.405737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.407177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.407239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.408550] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.408598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.409684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.411780] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.412815] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.413010] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.413064] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.413232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.429969] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.430016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.430062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.430106] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.430148] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.430192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.430236] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.430279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.430322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.430365] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.430407] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.430463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.430509] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.430519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.430565] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.430611] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.430657] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.430703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.430747] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.430792] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.430838] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.430885] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.430929] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.430972] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.431016] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.431059] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.431124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.431177] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.431221] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.446437] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.464993] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.465106] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.465194] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.465519] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.465565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.465610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.465654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.465699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.465743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.465787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.465830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.465873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.465916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.465963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.466010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.466077] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.466121] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.466176] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.466227] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.466276] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.466323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.466369] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.466414] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.466485] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.467032] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.467439] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.467529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.467577] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.467621] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.467663] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.467707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.467752] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.467796] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.467840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.467882] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.467925] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.467935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.467978] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.467984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.468028] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.468071] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.468115] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.468158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.468201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.468248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.468290] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.468336] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.468379] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.468423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.468500] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.468543] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.468607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.468660] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.468704] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.468861] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.468899] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.469189] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.469243] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.469285] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.469343] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.469669] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.469988] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.470032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.470075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.470118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.470160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.470203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.470246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.470289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.470331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.470374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.470420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.470517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.470594] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.470637] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.472073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.472117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.472161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.472924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.472966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.473752] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.473796] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.474863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.476955] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.477976] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.478171] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.478225] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.478396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.495145] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.495192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.495237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.495281] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.495323] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.495367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.495409] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.495520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.495563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.495608] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.495651] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.495660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.495703] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.495708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.495752] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.495795] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.495837] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.495880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.495923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.495970] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.496012] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.496056] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.496100] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.496144] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.496187] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.496231] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.496295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.496347] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.496390] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.511627] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.530137] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.530251] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.530339] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.530664] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.530709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.530753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.530797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.530841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.530885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.530930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.530974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.531018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.531062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.531109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.531156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.531219] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.531262] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.531317] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.531367] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.531413] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.531490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.531538] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.531583] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.531623] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.532173] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.532617] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.532661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.532706] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.532750] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.532792] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.532836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.532882] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.532925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.532969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.533013] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.533055] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.533065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.533107] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.533113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.533158] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.533201] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.533244] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.533287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.533331] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.533377] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.533420] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.533508] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.533552] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.533596] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.533640] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.533684] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.533751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.533806] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.533850] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.534012] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.534050] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.534340] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.534394] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.534462] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.534520] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.534769] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.535094] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.535138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.535181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.535224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.535267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.535310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.535353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.535396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.535492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.535536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.535587] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.535632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.535708] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.535752] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.537362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.537407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.537706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.538783] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.538828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.539727] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.539772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.540958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.543066] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.544137] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.544333] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.544387] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.544932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.561282] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.561329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.561374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.561418] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.561595] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.561640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.561686] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.561729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.561772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.561814] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.561857] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.561867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.561909] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.561915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.561959] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.562003] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.562047] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.562090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.562133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.562178] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.562221] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.562266] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.562310] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.562354] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.562397] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.562570] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.562689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.562743] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.562787] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.577768] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.596266] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.596379] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.596634] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.596958] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.597002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.597045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.597088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.597131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.597174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.597219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.597262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.597305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.597348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.597394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.597556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.597617] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.597661] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.597716] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.597767] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.597813] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.597860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.597906] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.597950] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.597989] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.599154] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.599670] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.599716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.599761] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.599805] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.599848] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.599892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.599935] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.599978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.600022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.600064] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.600106] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.600115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.600157] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.600163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.600206] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.600249] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.600292] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.600334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.600376] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.600421] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.600611] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.600657] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.600701] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.600745] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.600788] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.600832] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.600895] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.600949] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.600992] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.601141] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.601179] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.601588] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.602088] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.602129] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.602185] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.602820] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.603145] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.603189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.603232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.603275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.603318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.603361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.603404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.603770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.603814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.603857] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.603907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.603952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.604028] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.604072] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.605535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.605579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.605624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.606375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.606418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.607178] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.607222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.608297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.610389] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.611407] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.611631] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.611685] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.611855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.628613] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.628659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.628704] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.628748] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.628790] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.628834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.628878] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.628921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.628964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.629007] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.629049] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.629058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.629099] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.629105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.629148] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.629191] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.629234] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.629277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.629319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.629363] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.629406] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.629552] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.629596] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.629640] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.629684] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.629727] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.629797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.629850] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.629894] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.645045] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.663582] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.663696] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.663784] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.664105] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.664149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.664192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.664235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.664278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.664321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.664364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.664407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.664487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.664536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.664584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.664631] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.664699] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.664741] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.664797] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.664846] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.664892] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.664937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.664982] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.665025] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.665064] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.665642] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.666049] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.666094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.666140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.666184] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.666227] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.666271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.666316] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.666359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.666403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.666476] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.666565] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.666574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.666617] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.666622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.666666] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.666708] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.666751] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.666795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.666838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.666883] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.666926] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.666972] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.667016] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.667060] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.667103] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.667146] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.667210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.667263] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.667307] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.667513] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.667551] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.667842] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.667895] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.667935] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.667991] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.668298] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.668629] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.668674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.668718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.668761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.668805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.668849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.668893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.668936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.668980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.669023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.669071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.669116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.669191] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.669235] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.670714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.670757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.670801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.671586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.671630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.672343] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.672387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.673480] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.675528] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.676542] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.676751] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.676804] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.676974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.693777] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.693823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.693868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.693912] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.693954] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.693998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.694041] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.694084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.694127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.694169] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.694210] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.694219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.694261] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.694267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.694310] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.694352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.694395] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.694478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.694525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.694575] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.694620] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.694667] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.694712] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.694758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.694804] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.694850] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.694916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.694968] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.695013] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.710195] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.727812] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.727924] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.728012] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.728333] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.728376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.728420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.728555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.728599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.728646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.728689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.728733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.728777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.728820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.728869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.728914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.728983] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.729028] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.729082] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.729133] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.729178] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.729225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.729271] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.729315] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.729354] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.729976] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.730897] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.730942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.730988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.731032] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.731074] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.731118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.731161] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.731204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.731248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.731290] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.731332] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.731341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.731383] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.731389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.731433] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.731548] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.731592] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.731635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.731678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.731724] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.731767] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.731812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.731856] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.731899] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.731943] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.731986] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.732050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.732104] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.732148] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.732289] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.732327] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.732644] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.732699] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.732742] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.732800] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.733778] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.734101] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.734145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.734190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.734233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.734276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.734320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.734364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.734407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.735221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.735265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.735316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.735361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.735902] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.735948] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.737406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.737527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.737573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.738339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.738382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.739723] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.739771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.740949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.743052] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.744101] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.744288] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.744342] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.744931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.761273] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.761321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.761366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.761410] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.761540] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.761585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.761633] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.761675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.761719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.761761] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.761804] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.761814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.761857] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.761863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.761907] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.761950] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.761994] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.762036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.762080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.762125] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.762168] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.762213] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.762257] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.762300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.762343] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.762387] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.762479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.762531] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.762575] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.777705] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.796225] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.796339] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.796428] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.796820] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.796865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.796908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.796951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.796994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.797037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.797080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.797122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.797165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.797208] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.797254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.797298] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.797359] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.797401] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.797488] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.797541] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.797586] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.797633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.797680] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.797724] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.797763] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.798311] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.798753] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.798798] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.798843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.798886] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.798929] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.798973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.799015] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.799058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.799101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.799144] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.799185] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.799194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.799236] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.799241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.799285] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.799327] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.799370] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.799413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.799491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.799536] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.799582] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.799626] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.799669] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.799713] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.799757] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.799800] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.799861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.799915] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.799959] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.800113] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.800151] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.800501] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.801062] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.801103] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.801160] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.801488] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.801813] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.801857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.801901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.801944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.801986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.802029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.802072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.802115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.802158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.802202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.802247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.802292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.802365] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.802408] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.803879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.803923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.803967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.804765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.804809] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.805549] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.805594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.806633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.808723] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.809788] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.809998] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.810051] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.810222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.826975] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.827021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.827066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.827110] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.827152] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.827196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.827239] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.827282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.827325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.827367] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.827409] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.827479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.827525] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.827535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.827579] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.827622] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.827665] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.827709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.827752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.827798] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.827840] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.827886] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.827929] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.827973] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.828016] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.828060] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.828121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.828172] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.828216] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.843429] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.861773] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.861886] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.861975] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.862300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.862344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.862387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.862430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.862528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.862574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.862617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.862660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.862703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.862747] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.862793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.862838] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.862902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.862945] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.862999] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.863049] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.863096] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.863142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.863188] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.863232] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.863272] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.863895] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.864816] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.864860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.864905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.864951] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.864993] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.865036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.865080] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.865123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.865166] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.865208] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.865249] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.865258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.865300] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.865305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.865348] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.865391] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.865464] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.865509] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.865555] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.865602] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.865649] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.865696] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.865741] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.865787] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.865833] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.865878] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.865942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.865996] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.866039] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.866186] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.866224] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.866537] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.866594] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.866636] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.866693] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.866976] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.867300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.867344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.867387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.867430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.867544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.867588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.867632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.867676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.867720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.867764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.867813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.867859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.867934] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.867978] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.869405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.869481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.869525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.870288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.870331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.871062] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.871106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.872156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.874250] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.875268] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.875516] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.875574] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.875744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.892395] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.892535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.892581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.892625] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.892667] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.892711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.892755] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.892798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.892841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.892883] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.892925] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.892934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.892976] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.892982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.893025] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.893067] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.893110] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.893153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.893194] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.893239] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.893281] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.893326] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.893368] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.893411] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.894332] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.894375] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.894582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.894638] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.894681] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.908879] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.926896] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.927008] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.927097] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.927419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.927764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.927809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.927852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.927895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.927938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.927981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.928023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.928066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.928109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.928156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.928202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.928264] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.928307] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.928360] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.928412] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.929021] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.929067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.929116] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.929159] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.929197] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.930361] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.930906] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.930951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.930997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.931040] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.931082] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.931126] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.931170] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.931213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.931256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.931299] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.931341] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.931350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.931393] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.931901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.931956] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.931999] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.932042] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.932084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.932127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.932172] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.932214] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.932259] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.932302] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.932345] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.932388] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.932431] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.932972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.933026] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.933069] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.933221] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.933258] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.933786] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 551.934167] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.934207] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.934264] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.934802] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.935122] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.935165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.935209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.935251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.935294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.935337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.935380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.935423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.935828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.935871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.935920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.935965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.936040] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.936083] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.937794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.937839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.937883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 551.938711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.938754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 551.939623] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 551.939667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 551.940845] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 551.942946] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 551.944010] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.944214] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.944267] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.944702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.961181] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.961229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.961274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.961318] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.961360] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.961404] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.961531] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.961576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.961622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.961665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.961708] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.961717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.961760] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.961766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.961810] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.961853] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.961897] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.961940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.961983] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.962028] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.962071] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.962116] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.962160] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.962203] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.962247] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.962290] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.962352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.962404] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.962478] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.977673] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 551.996176] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 551.996289] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.996376] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.996712] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.996757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 551.996801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.996844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.996887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.996930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 551.996973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 551.997016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 551.997059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 551.997103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 551.997149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 551.997194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.997260] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 551.997302] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.997356] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 551.997405] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 551.997487] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 551.997534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.997583] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 551.997627] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 551.997666] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 551.998213] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 551.998668] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 551.998713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 551.998758] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 551.998806] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 551.998851] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 551.998895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.998938] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 551.998981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.999025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 551.999067] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.999110] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 551.999119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.999162] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 551.999167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.999211] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 551.999254] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 551.999298] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 551.999341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 551.999384] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 551.999429] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 551.999501] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 551.999547] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 551.999591] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 551.999634] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.999678] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.999722] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 551.999788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 551.999842] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 551.999886] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.000040] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.000079] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.000369] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 552.000424] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.000486] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.000544] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.001332] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.001854] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.001901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.001945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.001988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.002031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.002074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.002117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.002160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.002203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.002246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.002294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.002339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.002413] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.002830] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.004283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.004329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.004373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 552.005230] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 552.005276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 552.006531] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 552.008639] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 552.009657] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.009866] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.009920] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.010090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.026845] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.026892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.026937] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.026981] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.027023] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.027067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.027110] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.027153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.027196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.027238] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.027280] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.027288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.027330] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.027336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.027379] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.027421] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.027967] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.028012] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.028055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.028100] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.028143] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.028188] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.028232] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.028276] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.028320] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.028363] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.028431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.028851] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.028894] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.043307] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.060795] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.060908] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.061000] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.061323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.061368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.061411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.061504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.061551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.061596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.061644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.061690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.061734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.061778] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.061828] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.061874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.061938] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.061981] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.062035] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.062084] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.062132] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.062178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.062224] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.062267] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 552.062306] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 552.062927] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.063875] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.063922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.063967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.064011] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.064054] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.064098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.064142] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.064185] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.064228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.064270] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.064312] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.064321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.064364] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.064370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.064413] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.064547] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.064590] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.064634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.064677] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.064722] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.064765] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.064810] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.064854] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.064897] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.064941] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.064984] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.065053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.065108] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.065151] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.065303] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.065340] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.065658] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 552.065714] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.065758] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.065817] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.066644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.066973] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.067017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.067060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.067103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.067145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.067188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.067231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.067274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.067316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.067359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.067408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.067518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.067595] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.067638] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.069925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.069971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.070015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 552.070821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.070865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.071594] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 552.071638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 552.072745] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 552.074492] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 552.075515] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.075705] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.075758] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.075928] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.092765] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.092811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.092856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.092900] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.092942] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.092986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.093029] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.093071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.093115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.093157] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.093199] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.093208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.093249] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.093255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.093298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.093341] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.093383] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.093426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.093664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.093710] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.093753] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.093799] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.093843] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.093886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.093930] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.093973] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.094040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.094092] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.094135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.109170] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.126813] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.126926] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.127015] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.127336] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.127380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.127424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.127504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.127554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.127601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.127647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.127692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.127738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.127782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.128113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.128159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.128222] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.128265] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.128319] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.128370] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.128418] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.128506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.128553] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.128758] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 552.128797] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 552.129357] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.130063] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.130110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.130156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.130201] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.130243] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.130288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.130332] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.130376] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.130419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.130543] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.130587] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.130821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.130873] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.130879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.130924] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.130967] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.131011] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.131055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.131098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.131144] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.131187] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.131232] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.131277] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.131321] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.131365] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.131409] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.131515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.131570] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.131613] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.131764] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.131803] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.132093] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 552.132147] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.132190] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.132247] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.132519] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.133139] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.133185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.133229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.133271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.133314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.133357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.133400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.133480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.133525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.133571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.133620] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.133667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.134042] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.134087] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.135537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.135582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.135627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 552.136385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.136427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.137281] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 552.137327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 552.138513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 552.140613] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 552.141704] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.141915] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.141971] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.142141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.158871] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.158918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.158963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.159007] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.159049] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.159093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.159137] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.159180] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.159223] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.159265] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.159307] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.159316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.159358] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.159364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.159406] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.159523] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.159569] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.159614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.159659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.159705] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.160138] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.160186] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.160229] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.160274] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.160318] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.160361] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.160429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.160518] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.160566] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.175351] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.193875] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.193988] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.194076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.194397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.194507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.194818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.194861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.194904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.194947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.194990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.195033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.195078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.195122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.195170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.195215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.195277] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.195320] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.195375] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.195424] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.195859] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.195909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.195961] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.196005] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 552.196046] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 552.196632] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.197273] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.197319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.197365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.197409] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.197501] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.197547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.197594] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.197832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.197876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.197918] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.197960] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.197969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.198011] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.198017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.198060] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.198103] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.198146] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.198188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.198230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.198276] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.198317] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.198363] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.198406] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.198494] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.198539] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.198587] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.198654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.198965] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.199009] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.199165] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.199203] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.199530] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 552.199586] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.199851] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.199909] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.200207] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.200685] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.200731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.200775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.200817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.200860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.200904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.200946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.200989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.201032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.201075] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.201123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.201168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.201242] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.201287] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.202929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.202973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.203095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 552.203952] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 552.203999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 552.205047] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 552.207142] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 552.208149] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.208350] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.208404] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.208606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.225314] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.225361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.225406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.225663] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.225705] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.225750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.225795] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.225841] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.225884] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.225927] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.225970] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.225981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.226024] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.226031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.226075] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.226119] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.226162] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.226206] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.226249] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.226294] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.226337] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.226383] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.226427] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.226501] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.226545] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.226589] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.226659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.226713] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.226757] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.241763] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.260304] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.260417] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.260604] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.260922] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.260966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.261011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.261054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.261098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.261141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.261185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.261228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.261272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.261315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.261362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.261407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.261493] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.261564] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.261619] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.261669] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.261715] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.261761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.261806] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.261850] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 552.261889] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 552.262479] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.262903] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.262948] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.262993] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.263037] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.263079] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.263123] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.263166] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.263209] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.263252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.263294] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.263336] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.263345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.263387] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.263393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.263470] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.263555] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.263598] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.263644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.263686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.263732] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.263774] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.263819] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.263862] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.263904] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.263947] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.263993] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.264053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.264107] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.264150] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.264299] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.264337] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.264656] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 552.264712] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.264754] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.264811] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.265099] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.265422] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.265501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.265547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.265591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.265635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.265681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.265724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.265767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.265809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.265853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.265902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.265948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.266024] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.266068] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.267558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.267604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.267648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 552.268404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.268478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.269195] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 552.269238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 552.270275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 552.272369] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 552.273932] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.274132] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.274186] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.274356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.291077] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.291125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.291170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.291214] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.291256] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.291300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.291344] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.291386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.291430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.291504] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.291550] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.291562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.291605] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.291613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.291658] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.291702] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.291748] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.291794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.291837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.291885] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.291927] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.291972] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.292015] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.292059] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.292102] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.292147] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.292211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.292262] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.292306] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.307589] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.326106] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.326219] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.326306] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.326641] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.326687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.326732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.326775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.326819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.326863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.326906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.326950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.326994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.327037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.327084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.327129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.327198] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.327241] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.327296] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.327346] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.327394] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.327475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.327526] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.327571] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:06 BXT-2 kernel: [ 552.327614] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:06 BXT-2 kernel: [ 552.328164] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.328621] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:06 BXT-2 kernel: [ 552.328666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:06 BXT-2 kernel: [ 552.328711] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:06 BXT-2 kernel: [ 552.328755] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:06 BXT-2 kernel: [ 552.328797] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:06 BXT-2 kernel: [ 552.328841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.328884] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:06 BXT-2 kernel: [ 552.328926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.328969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:06 BXT-2 kernel: [ 552.329012] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.329054] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:06 BXT-2 kernel: [ 552.329062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.329104] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:06 BXT-2 kernel: [ 552.329110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.329154] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:06 BXT-2 kernel: [ 552.329197] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:06 BXT-2 kernel: [ 552.329239] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:06 BXT-2 kernel: [ 552.329282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:06 BXT-2 kernel: [ 552.329324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:06 BXT-2 kernel: [ 552.329369] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:06 BXT-2 kernel: [ 552.329411] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:06 BXT-2 kernel: [ 552.329487] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:06 BXT-2 kernel: [ 552.329533] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:06 BXT-2 kernel: [ 552.329580] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.329625] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.329670] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:06 BXT-2 kernel: [ 552.329736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.329790] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.329834] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.329990] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:06 BXT-2 kernel: [ 552.330029] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:06 BXT-2 kernel: [ 552.330319] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:06 BXT-2 kernel: [ 552.330374] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.330416] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:06 BXT-2 kernel: [ 552.330551] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:06 BXT-2 kernel: [ 552.330792] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.331113] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:06 BXT-2 kernel: [ 552.331157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:06 BXT-2 kernel: [ 552.331201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.331244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.331286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.331329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:06 BXT-2 kernel: [ 552.331372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:06 BXT-2 kernel: [ 552.331415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:06 BXT-2 kernel: [ 552.331503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:06 BXT-2 kernel: [ 552.331548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:06 BXT-2 kernel: [ 552.331597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:06 BXT-2 kernel: [ 552.331644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.331718] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:06 BXT-2 kernel: [ 552.331762] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:06 BXT-2 kernel: [ 552.333205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.333249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.333294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:06 BXT-2 kernel: [ 552.334071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.334115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:06 BXT-2 kernel: [ 552.334851] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:06 BXT-2 kernel: [ 552.334896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:06 BXT-2 kernel: [ 552.335931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:06 BXT-2 kernel: [ 552.338025] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:06 BXT-2 kernel: [ 552.339039] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:06 BXT-2 kernel: [ 552.339231] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:06 BXT-2 kernel: [ 552.339285] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:06 BXT-2 kernel: [ 552.339486] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.356210] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.356257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.356302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.356346] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.356388] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.356432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.356547] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.356592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.356636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.356681] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.356724] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.356733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.356775] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.356781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.356825] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.356867] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.356910] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.356953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.356996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.357043] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.357086] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.357131] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.357175] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.357219] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.357262] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.357306] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.357369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.357421] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.357495] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.372673] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.391188] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.391301] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.391388] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.391773] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.391818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.391862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.391905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.391948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.391991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.392034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.392077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.392120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.392163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.392209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.392253] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.392321] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.392363] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.392416] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.392499] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.392547] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.392596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.392643] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.392688] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.392730] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.393279] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.393728] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.393774] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.393819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.393863] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.393905] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.393949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.393992] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.394035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.394078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.394121] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.394163] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.394171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.394213] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.394219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.394262] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.394305] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.394347] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.394390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.394432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.394508] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.394555] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.394601] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.394648] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.394694] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.394741] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.394786] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.394852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.394907] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.394951] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.395104] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.395143] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.395461] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.395518] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.395560] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.395618] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.395905] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.396228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.396273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.396316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.396359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.396401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.396493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.396539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.396584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.396629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.396673] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.396721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.396767] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.396842] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.396886] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.398339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.398383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.398427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.399231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.399274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.400018] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.400062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.401111] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.403204] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.404222] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.404415] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.404507] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.404685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.421407] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.421511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.421557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.421601] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.421643] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.421687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.421731] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.421774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.421817] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.421859] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.421901] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.421911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.421952] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.421958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.422001] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.422044] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.422087] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.422129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.422172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.422217] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.422259] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.422304] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.422347] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.422390] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.422433] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.422517] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.422589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.422644] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.422689] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.437861] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.455721] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.455835] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.455925] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.456246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.456291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.456335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.456378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.456421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.456528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.456572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.456620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.456663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.456706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.456755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.456800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.456868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.456912] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.456966] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.457016] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.457065] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.457115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.457164] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.457209] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.457250] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.457851] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.458802] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.458847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.458893] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.458937] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.458979] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.459024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.459067] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.459110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.459153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.459196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.459238] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.459247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.459288] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.459294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.459338] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.459380] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.459423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.459493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.459535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.459580] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.459623] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.459667] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.459711] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.459754] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.459796] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.459839] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.459899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.459951] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.459994] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.460147] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.460185] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.460496] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.460550] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.460591] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.460647] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.460937] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.461259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.461303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.461346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.461389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.461432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.461510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.461554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.461601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.461648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.461693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.461744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.461791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.461869] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.461915] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.463354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.463398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.463478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.464237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.464281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.465009] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.465053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.466090] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.468187] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.469221] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.469424] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.469515] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.469689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.486384] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.486431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.486572] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.486617] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.486660] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.486705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.486750] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.486793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.486838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.486880] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.486923] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.486932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.486975] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.486981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.487025] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.487069] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.487112] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.487155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.487198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.487244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.487286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.487332] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.487376] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.487419] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.487482] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.487555] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.487620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.487672] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.487716] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.502847] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.521367] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.521512] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.521603] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.521923] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.521967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.522011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.522054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.522096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.522139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.522182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.522225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.522268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.522311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.522357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.522402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.522495] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.522538] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.522593] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.522642] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.522690] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.522738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.522784] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.522828] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.522867] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.523415] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.524380] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.524426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.524511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.524556] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.524598] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.524643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.524687] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.524731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.524775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.524818] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.524861] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.524870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.524913] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.524919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.524963] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.525006] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.525050] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.525093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.525136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.525181] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.525225] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.525270] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.525314] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.525357] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.525401] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.525467] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.525533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.525588] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.525634] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.525788] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.525826] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.526116] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.526170] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.526213] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.526270] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.526594] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.526914] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.526958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.527001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.527044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.527087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.527130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.527173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.527216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.527258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.527301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.527348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.527392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.527557] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.527601] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.529045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.529089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.529135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.529905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.529948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.530700] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.530744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.531801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.533894] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.534911] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.535104] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.535158] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.535328] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.552065] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.552112] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.552158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.552201] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.552244] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.552287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.552331] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.552373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.552417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.552503] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.552549] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.552564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.552609] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.552617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.552663] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.552708] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.552755] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.552799] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.552842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.552888] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.552931] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.552976] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.553020] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.553063] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.553107] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.553150] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.553215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.553268] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.553312] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.568541] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.586760] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.586872] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.586960] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.587281] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.587325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.587368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.587411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.587545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.587589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.587632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.587677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.587720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.587765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.587814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.587859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.587928] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.587972] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.588027] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.588078] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.588125] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.588171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.588217] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.588261] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.588300] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.588878] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.589300] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.589344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.589389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.589433] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.589505] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.589550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.589596] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.589639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.589683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.589726] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.589769] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.589779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.589820] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.589827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.589871] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.589915] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.589958] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.590002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.590045] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.590090] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.590133] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.590179] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.590223] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.590266] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.590310] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.590354] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.590415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.590488] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.590573] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.590722] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.590760] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.591050] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.591104] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.591146] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.591204] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.591517] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.591843] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.591887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.591930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.591973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.592016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.592059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.592102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.592145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.592188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.592231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.592278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.592323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.592395] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.592483] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.593921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.593965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.594010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.594781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.594824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.595549] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.595593] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.596630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.598725] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.599744] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.599932] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.599985] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.600155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.616904] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.616951] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.616997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.617041] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.617083] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.617127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.617170] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.617213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.617257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.617299] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.617341] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.617350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.617391] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.617464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.617516] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.617562] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.617608] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.617651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.617697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.617744] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.617787] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.617833] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.617876] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.617920] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.617963] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.618007] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.618071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.618123] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.618167] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.633360] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.651872] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.651985] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.652074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.652395] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.652473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.652517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.652564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.652607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.652651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.652694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.652738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.652782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.652826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.652873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.652918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.652987] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.653030] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.653085] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.653135] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.653183] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.653230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.653276] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.653321] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.653360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.653945] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.654371] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.654415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.654566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.654610] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.654654] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.654698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.654743] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.654787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.654831] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.654874] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.654917] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.654926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.654968] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.654975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.655018] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.655062] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.655105] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.655148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.655191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.655236] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.655279] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.655325] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.655369] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.655412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.655475] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.655546] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.655614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.655669] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.655712] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.655857] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.655896] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.656187] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.656241] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.656283] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.656340] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.656657] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.656983] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.657027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.657070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.657113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.657156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.657199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.657241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.657286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.657329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.657371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.657418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.657509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.657584] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.657629] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.659060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.659103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.659148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.659934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.659977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.660731] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.660775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.661824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.663495] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.664539] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.664733] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.664787] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.664957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.681719] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.681766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.681811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.681855] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.681898] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.681942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.681985] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.682028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.682071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.682114] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.682156] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.682165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.682207] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.682213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.682256] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.682298] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.682341] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.682383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.682426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.682573] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.682617] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.682668] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.682711] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.682755] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.682799] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.682842] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.682911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.682963] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.683006] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.698168] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.716719] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.716831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.716918] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.717239] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.717283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.717326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.717369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.717412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.717512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.717560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.717606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.717652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.717698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.717746] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.717792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.717862] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.717906] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.717959] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.718009] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.718055] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.718102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.718148] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.718193] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.718233] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.718809] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.719216] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.719261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.719306] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.719350] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.719392] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.719474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.719518] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.719561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.719605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.719651] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.719693] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.719701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.719743] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.719750] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.719794] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.719837] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.719881] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.719925] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.719968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.720014] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.720057] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.720102] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.720145] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.720189] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.720233] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.720277] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.720340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.720395] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.720465] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.720624] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.720663] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.720953] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.721007] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.721049] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.721107] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.721402] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.721753] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.721798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.721841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.721884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.721927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.721971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.722017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.722063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.722109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.722153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.722200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.722245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.722318] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.722362] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.723801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.723845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.723890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.724654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.724697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.725410] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.725602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.726648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.728741] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.729804] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.730011] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.730064] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.730235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.746966] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.747013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.747058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.747102] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.747144] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.747188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.747231] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.747274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.747318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.747360] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.747402] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.747448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.747492] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.747501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.747544] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.747587] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.747630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.747673] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.747717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.747762] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.747805] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.747850] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.747894] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.747938] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.747981] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.748025] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.748089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.748140] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.748184] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.763451] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.781979] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.782092] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.782181] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.782505] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.782552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.782596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.782640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.782684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.782728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.782771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.782815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.782859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.782902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.782949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.782995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.783063] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.783107] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.783161] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.783211] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.783257] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.783304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.783350] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.783394] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.783466] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.784014] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.784434] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.784514] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.784564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.784609] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.784652] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.784696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.784741] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.784784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.784828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.784871] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.784913] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.784923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.784964] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.784971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.785014] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.785058] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.785101] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.785144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.785187] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.785232] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.785275] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.785323] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.785367] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.785410] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.785480] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.785526] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.785593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.785650] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.785693] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.785850] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.785888] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.786178] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.786232] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.786274] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.786332] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.786663] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.786988] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.787032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.787075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.787118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.787160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.787203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.787246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.787289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.787332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.787375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.787421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.787511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.787587] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.787631] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.789070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.789114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.789159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.789932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.789975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.790724] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.790768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.791811] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.793913] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.794982] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.795176] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.795230] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.795401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.812139] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.812186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.812231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.812274] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.812317] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.812361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.812405] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.812487] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.812535] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.812580] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.812626] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.812638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.812683] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.812691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.812735] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.812778] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.812821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.812868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.812913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.812960] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.813003] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.813048] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.813093] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.813136] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.813180] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.813225] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.813290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.813342] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.813386] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.828627] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.847128] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.847241] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.847329] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.847659] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.847706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.847752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.847797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.847840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.847886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.847930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.847973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.848016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.848059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.848105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.848150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.848216] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.848259] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.848312] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.848360] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.848406] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.848485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.848530] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.848573] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.848613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.849162] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.849623] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.849669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.849714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.849758] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.849800] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.849844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.849888] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.849930] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.849974] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.850016] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.850058] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.850188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.850238] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.850244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.850287] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.850330] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.850373] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.850416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.850487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.850537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.850581] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.850629] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.850675] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.850721] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.850766] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.850812] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.850883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.850937] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.850983] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.851134] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.851172] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.851489] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.851542] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.851584] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.851641] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.851926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.852253] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.852297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.852342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.852385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.852429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.852504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.852548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.852592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.852636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.852680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.852727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.852773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.852847] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.852891] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.854446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.854530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.854575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.855333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.855376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.856114] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.856159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.857211] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.859309] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.860302] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.860646] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.860701] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.860871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.877445] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.877559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.877605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.877649] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.877691] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.877735] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.877778] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.877821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.877864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.877906] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.877947] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.877956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.877998] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.878004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.878047] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.878090] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.878132] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.878175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.878217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.878261] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.878303] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.878348] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.878391] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.878607] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.878730] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.878773] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.878837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.878890] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.878934] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.893916] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.912437] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.912598] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.912687] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.913007] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.913051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.913094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.913138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.913181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.913223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.913266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.913310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.913352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.913395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.913616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.913661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.913723] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.913767] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.913821] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.913871] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.913918] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.913964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.914011] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.914055] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.914094] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.915261] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.915773] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.915819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.915864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.915908] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.915950] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.915994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.916038] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.916081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.916124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.916166] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.916208] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.916217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.916259] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.916265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.916308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.916351] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.916393] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.916601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.916644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.916690] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.916733] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.916778] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.916822] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.916866] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.916910] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.916954] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.917019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.917073] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.917117] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.917266] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.917305] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.917727] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.918219] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.918260] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.918317] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.918723] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.919053] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.919097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.919140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.919183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.919226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.919269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.919312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.919355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.919398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.919585] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.919633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.919680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.919755] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.919799] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.921312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.921359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.921403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.922252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.922299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.923086] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.923132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.924187] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.926283] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.927316] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.927674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.927729] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.927899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.944530] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.944577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.944622] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.944665] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.944708] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.944752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.944795] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.944838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.944881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.944923] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.944965] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.944975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.945016] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.945022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.945066] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.945108] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.945151] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.945194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.945236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.945281] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.945323] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.945368] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.945411] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.945646] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.945748] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.945791] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.945855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.945908] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.945951] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.960949] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.979512] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.979626] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.979714] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.980043] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.980087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.980130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.980173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.980216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.980260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.980303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.980346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.980389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.980432] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.980650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.980695] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.980755] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.980798] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.980851] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.980901] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.980947] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.980995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.981040] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.981085] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 552.981123] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 552.982287] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.982802] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 552.982847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 552.982892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 552.982936] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 552.982979] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 552.983023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.983066] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 552.983109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.983152] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 552.983194] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.983236] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 552.983244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.983286] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 552.983292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.983335] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 552.983378] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 552.983421] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 552.983616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 552.983714] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 552.983759] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 552.983802] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 552.983847] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 552.983891] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 552.983934] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.983978] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.984022] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 552.984086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.984140] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.984184] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.984331] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 552.984369] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 552.984791] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 552.985285] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.985327] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 552.985385] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 552.985769] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.986091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 552.986136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 552.986179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.986222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.986265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.986307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 552.986350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 552.986393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 552.986586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 552.986630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 552.986677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 552.986722] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.986797] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 552.986841] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 552.988262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.988306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.988351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 552.989134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.989177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 552.989954] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 552.989999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 552.991051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 552.993155] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 552.994192] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 552.994385] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 552.994565] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 552.994740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.011376] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.011423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.011630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.011674] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.011716] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.011761] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.011806] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.011850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.011894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.011937] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.011980] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.011990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.012032] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.012038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.012082] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.012125] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.012169] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.012212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.012255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.012301] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.012344] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.012390] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.012563] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.012660] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.012704] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.012747] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.012811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.012864] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.012907] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.027823] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.046319] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.046432] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.046686] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.047008] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.047052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.047096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.047138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.047181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.047224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.047267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.047310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.047353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.047397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.047563] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.047608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.047669] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.047712] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.047766] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.047816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.047862] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.047909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.047955] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.047999] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 553.048038] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 553.049201] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.049713] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.049758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.049804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.049848] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.049890] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.049934] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.049977] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.050020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.050063] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.050106] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.050147] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.050156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.050198] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.050204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.050247] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.050290] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.050333] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.050375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.050417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.050739] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.050781] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.050827] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.050871] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.050915] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.050960] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.051003] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.051073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.051128] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.051172] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.051323] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.051361] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.051792] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 553.052273] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.052314] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.052371] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.052691] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.053014] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.053059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.053102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.053145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.053188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.053231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.053273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.053316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.053359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.053402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.053588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.053633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.053708] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.053751] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.055173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.055217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.055262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 553.056076] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 553.056122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 553.057174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 553.059281] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 553.060273] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.060629] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.060685] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.060855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.077523] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.077570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.077615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.077659] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.077701] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.077745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.077788] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.077831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.077875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.077917] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.077959] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.077968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.078010] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.078016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.078059] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.078101] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.078144] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.078187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.078229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.078274] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.078316] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.078361] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.078404] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.078667] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.078711] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.078754] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.078819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.078870] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.078913] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.093922] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.112417] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.112579] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.112669] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.112995] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.113039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.113082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.113125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.113168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.113211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.113254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.113296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.113339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.113382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.113428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.113638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.113700] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.113743] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.113797] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.113848] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.113895] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.113941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.113987] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.114031] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 553.114070] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 553.114727] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.115684] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.115728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.115775] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.115819] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.115862] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.115907] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.115951] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.115995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.116039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.116081] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.116124] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.116133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.116176] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.116182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.116226] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.116269] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.116313] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.116356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.116398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.116590] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.116632] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.116677] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.116721] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.116763] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.116806] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.116850] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.116914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.116969] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.117012] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.117164] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.117202] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.117624] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 553.118113] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.118154] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.118211] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.118590] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.118911] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.118955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.118998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.119040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.119083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.119126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.119168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.119211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.119253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.119296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.119342] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.119387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.119601] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.119646] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.121082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.121127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.121171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 553.122000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.122043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.122804] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 553.122849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 553.123946] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 553.126050] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 553.127081] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.127279] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.127333] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.127632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.144953] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.145001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.145046] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.145090] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.145133] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.145176] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.145220] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.145263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.145306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.145348] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.145390] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.145399] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.145613] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.145619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.145663] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.145706] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.145748] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.145791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.145833] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.145879] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.145922] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.145967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.146011] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.146055] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.146099] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.146142] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.146208] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.146261] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.146305] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.160711] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.179212] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.179325] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.179414] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.179901] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.179946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.179989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.180033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.180076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.180119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.180162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.180205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.180248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.180291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.180337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.180382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.180561] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.180605] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.180658] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.180708] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.180753] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.180799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.180846] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.180889] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 553.180929] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 553.181580] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.182548] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.182594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.182639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.182683] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.182727] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.182772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.182817] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.182860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.182905] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.182947] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.182990] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.182999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.183042] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.183048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.183092] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.183135] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.183179] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.183222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.183265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.183310] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.183353] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.183399] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.183645] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.183688] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.183731] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.183774] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.183838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.183891] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.183935] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.184086] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.184125] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.184415] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 553.185047] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.185089] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.185145] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.185437] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.185886] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.185931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.185974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.186017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.186060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.186103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.186146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.186189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.186231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.186274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.186321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.186366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.186551] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.186595] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.188025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.188070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.188114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 553.188953] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 553.188998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 553.190050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 553.192145] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 553.193171] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.193359] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.193413] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.193716] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.210341] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.210388] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.210597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.210642] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.210684] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.210729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.210775] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.210818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.210862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.210905] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.210948] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.210958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.211000] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.211007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.211051] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.211094] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.211138] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.211181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.211224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.211269] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.211312] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.211357] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.211401] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.211594] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.211637] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.211680] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.211743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.211796] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.211839] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.226787] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.245288] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.245401] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.245661] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.245985] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.246029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.246072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.246115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.246158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.246201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.246244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.246287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.246330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.246373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.246419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.246611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.246672] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.246714] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.246768] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.246818] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.246865] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.246912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.246957] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.247001] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 553.247040] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 553.248205] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.248717] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.248762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.248807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.248851] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.248893] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.248938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.248981] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.249024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.249067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.249109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.249151] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.249160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.249201] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.249207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.249250] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.249293] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.249335] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.249378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.249420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.249652] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.249695] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.249740] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.249783] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.249826] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.249869] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.249913] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.249978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.250032] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.250076] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.250223] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.250261] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.250681] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 553.251294] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.251335] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.251392] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.251799] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.252123] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.252167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.252211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.252254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.252296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.252339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.252383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.252425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.252613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.252657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.252705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.252749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.252825] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.252869] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.254288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.254332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.254377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 553.255276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.255320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.256070] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 553.256115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 553.257169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 553.259273] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 553.260269] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.260627] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.260682] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.260853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.277521] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.277568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.277614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.277658] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.277700] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.277744] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.277787] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.277830] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.277873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.277916] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.277957] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.277966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.278008] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.278014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.278057] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.278100] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.278143] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.278185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.278228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.278273] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.278315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.278360] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.278403] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.278669] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.278713] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.278756] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.278820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.278872] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.278915] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.293916] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.312412] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.312569] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.312659] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.312976] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.313020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.313064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.313107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.313150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.313193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.313236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.313279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.313321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.313364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.313410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.313647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.313707] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.313750] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.313803] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.313853] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.313899] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.313945] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.313991] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.314035] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:07 BXT-2 kernel: [ 553.314074] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:07 BXT-2 kernel: [ 553.315237] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.315745] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.315791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.315836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.315879] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.315922] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.315966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.316009] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.316052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.316095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.316138] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.316180] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.316188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.316230] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.316235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.316278] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.316321] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.316364] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.316407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.316608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.316654] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.316696] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.316741] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.316784] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.316827] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.316871] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.316915] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.316980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.317034] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.317078] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.317227] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:07 BXT-2 kernel: [ 553.317265] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:07 BXT-2 kernel: [ 553.317683] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:07 BXT-2 kernel: [ 553.318181] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.318223] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:07 BXT-2 kernel: [ 553.318281] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:07 BXT-2 kernel: [ 553.318685] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.319005] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.319048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:07 BXT-2 kernel: [ 553.319092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.319135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.319178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.319222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:07 BXT-2 kernel: [ 553.319265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:07 BXT-2 kernel: [ 553.319308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:07 BXT-2 kernel: [ 553.319351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:07 BXT-2 kernel: [ 553.319394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:07 BXT-2 kernel: [ 553.319600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:07 BXT-2 kernel: [ 553.319645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.319720] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:07 BXT-2 kernel: [ 553.319764] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.321183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.321228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.321273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:07 BXT-2 kernel: [ 553.322104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.322148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:07 BXT-2 kernel: [ 553.322948] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:07 BXT-2 kernel: [ 553.322992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:07 BXT-2 kernel: [ 553.324042] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:07 BXT-2 kernel: [ 553.326145] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:07 BXT-2 kernel: [ 553.327186] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:07 BXT-2 kernel: [ 553.327377] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:07 BXT-2 kernel: [ 553.327431] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:07 BXT-2 kernel: [ 553.327732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.344372] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:07 BXT-2 kernel: [ 553.344419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:07 BXT-2 kernel: [ 553.344624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:07 BXT-2 kernel: [ 553.344668] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:07 BXT-2 kernel: [ 553.344711] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:07 BXT-2 kernel: [ 553.344756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.344802] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:07 BXT-2 kernel: [ 553.344845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.344890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:07 BXT-2 kernel: [ 553.344933] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.344975] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:07 BXT-2 kernel: [ 553.344985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.345028] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:07 BXT-2 kernel: [ 553.345034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.345078] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:07 BXT-2 kernel: [ 553.345122] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:07 BXT-2 kernel: [ 553.345165] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:07 BXT-2 kernel: [ 553.345208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:07 BXT-2 kernel: [ 553.345251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:07 BXT-2 kernel: [ 553.345297] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:07 BXT-2 kernel: [ 553.345340] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:07 BXT-2 kernel: [ 553.345385] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:07 BXT-2 kernel: [ 553.345428] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:07 BXT-2 kernel: [ 553.345602] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.345703] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.345746] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:07 BXT-2 kernel: [ 553.345808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:07 BXT-2 kernel: [ 553.345861] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:07 BXT-2 kernel: [ 553.345905] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.360813] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.379317] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.379430] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.379654] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.379978] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.380022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.380065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.380109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.380151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.380194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.380237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.380280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.380323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.380366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.380412] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.380613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.380674] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.380717] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.380772] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.380822] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.380871] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.380919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.380965] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.381009] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.381048] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.382211] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.382720] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.382765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.382811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.382855] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.382897] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.382941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.382985] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.383028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.383071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.383113] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.383155] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.383163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.383205] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.383211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.383254] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.383297] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.383340] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.383382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.383424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.383631] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.383674] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.383720] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.383763] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.383806] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.383849] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.383892] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.383957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.384012] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.384055] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.384205] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.384243] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.384662] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.385156] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.385198] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.385256] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.385640] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.385958] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.386001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.386045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.386088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.386131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.386173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.386216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.386259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.386302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.386345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.386392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.386477] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.386554] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.386597] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.388034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.388079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.388124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.388896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.388940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.389702] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.389746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.390792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.392889] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.393881] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.394065] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.394119] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.394288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.411053] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.411100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.411145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.411189] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.411231] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.411275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.411318] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.411362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.411405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.411511] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.411553] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.411565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.411607] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.411616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.411660] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.411705] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.411748] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.411791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.411833] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.411878] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.411920] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.411965] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.412009] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.412052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.412096] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.412139] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.412204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.412256] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.412300] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.427549] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.446086] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.446199] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.446287] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.446640] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.446686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.446731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.446774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.446818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.446862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.446906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.446950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.446993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.447037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.447084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.447129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.447196] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.447240] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.447294] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.447344] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.447391] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.447463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.447512] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.447558] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.447599] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.448147] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.448609] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.448654] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.448700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.448744] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.448787] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.448832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.448876] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.448919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.448964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.449006] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.449049] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.449059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.449101] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.449108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.449152] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.449195] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.449239] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.449282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.449325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.449371] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.449414] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.449484] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.449531] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.449576] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.449622] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.449667] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.449732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.449786] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.449831] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.449983] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.450020] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.450309] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.450363] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.450405] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.450489] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.450779] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.451103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.451148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.451192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.451235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.451279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.451322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.451366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.451409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.451494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.451540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.451588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.451752] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.451827] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.451871] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.453288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.453331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.453376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.454184] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.454227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.454986] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.455030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.456071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.458165] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.459190] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.459376] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.459430] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.459635] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.476394] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.476511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.476557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.476601] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.476643] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.476687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.476732] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.476775] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.476818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.476860] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.476902] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.476911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.476953] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.476959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.477002] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.477044] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.477087] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.477130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.477172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.477217] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.477259] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.477305] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.477349] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.477392] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.477490] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.477537] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.477614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.477671] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.477715] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.492831] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.509564] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.509682] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.509772] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.510107] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.510153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.510197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.510240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.510283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.510326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.510369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.510411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.510537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.510583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.510634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.510679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.510752] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.510796] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.510851] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.510902] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.510951] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.510999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.511049] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.511094] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.511133] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.511745] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.512746] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.512794] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.512839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.512883] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.512925] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.512971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.513015] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.513058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.513101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.513144] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.513186] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.513195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.513237] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.513243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.513286] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.513328] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.513371] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.513414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.513517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.513566] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.513610] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.513658] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.513704] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.513750] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.513795] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.513840] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.513919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.513976] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.514019] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.514205] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.514244] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.514587] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.514651] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.514692] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.514748] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.515086] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.515435] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.515556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.515600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.515643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.515686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.515729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.515773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.515817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.515860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.515904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.515957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.516003] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.516081] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.516125] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.517652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.517699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.517744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.518574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.518621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.519386] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.519477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.520596] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.522722] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.523807] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.524048] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.524103] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.524282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.541041] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.541089] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.541135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.541180] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.541222] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.541267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.541312] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.541354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.541398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.541528] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.541571] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.541580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.541622] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.541628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.541671] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.541714] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.541758] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.541802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.541844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.541890] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.541934] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.541980] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.542024] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.542068] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.542112] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.542155] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.542236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.542294] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.542338] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.557540] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.574213] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.574331] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.574421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.574830] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.574877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.574922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.574966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.575009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.575053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.575097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.575140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.575184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.575228] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.575279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.575325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.575401] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.575488] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.575544] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.575597] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.575644] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.575690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.575739] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.575783] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.575822] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.576388] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.577372] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.577418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.577504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.577551] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.577595] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.577641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.577686] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.577729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.577772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.577815] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.577858] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.577868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.577911] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.577918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.577962] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.578006] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.578050] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.578093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.578136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.578181] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.578225] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.578271] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.578316] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.578359] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.578403] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.578491] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.578568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.578625] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.578668] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.578849] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.578888] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.579194] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.579253] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.579294] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.579354] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.579735] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.580073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.580120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.580165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.580208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.580252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.580295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.580339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.580382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.580426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.580544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.580596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.580641] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.580718] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.580761] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.582265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.582312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.582356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.583173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.583220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.584056] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.584110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.585247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.587391] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.588549] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.588762] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.588818] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.588997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.605814] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.605863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.605908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.605952] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.605995] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.606039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.606084] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.606127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.606170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.606212] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.606253] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.606263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.606305] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.606311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.606354] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.606396] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.606496] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.606540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.606584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.606632] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.606677] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.606726] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.606774] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.606820] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.606866] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.606910] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.606990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.607046] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.607090] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.622198] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.638930] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.639054] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.639148] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.639548] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.639597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.639641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.639685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.639729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.639773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.639817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.639861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.639905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.639949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.640001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.640048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.640127] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.640173] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.640229] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.640281] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.640330] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.640379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.640477] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.640523] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.640565] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.641135] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.641664] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.641713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.641759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.641804] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.641847] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.641893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.641938] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.641982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.642027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.642070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.642113] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.642123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.642166] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.642173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.642216] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.642260] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.642304] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.642347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.642390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.642540] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.642584] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.642630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.642674] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.642717] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.642760] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.642802] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.642884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.642943] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.642987] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.643190] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.643231] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.643581] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.644171] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.644217] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.644276] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.644672] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.645023] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.645070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.645114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.645157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.645200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.645243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.645286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.645328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.645371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.645414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.645552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.645598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.645677] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.645721] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.647222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.647270] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.647315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.648121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.648168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.648930] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.648980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.650066] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.652253] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.653276] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.653552] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.653607] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.653785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.670538] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.670584] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.670629] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.670673] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.670715] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.670760] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.670804] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.670846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.670889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.670932] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.670973] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.670982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.671025] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.671031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.671074] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.671116] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.671159] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.671202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.671244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.671290] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.671332] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.671377] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.671421] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.671516] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.671562] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.671608] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.671685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.671739] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.671785] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.686917] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.703771] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.703933] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.704059] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.704421] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.704645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.704707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.704755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.704803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.704849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.704896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.704942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.704989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.705036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.705097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.705148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.705253] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.705311] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.705375] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.705434] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.705551] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.705614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.705683] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.705732] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.705772] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.706382] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.707418] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.707536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.707594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.707641] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.707685] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.707734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.707786] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.707832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.707879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.707924] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.707968] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.707978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.708027] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.708033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.708080] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.708126] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.708172] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.708216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.708259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.708306] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.708351] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.708401] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.708520] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.708573] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.708625] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.708674] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.708771] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.708849] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.708897] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.709146] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.709206] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.709605] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.710185] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.710252] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.710333] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.710784] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.711173] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.711244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.711294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.711342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.711389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.711547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.711606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.711652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.711698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.711745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.711805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.711858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.711956] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.712008] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.713718] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.713788] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.713838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.714750] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.714808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.715996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.718183] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.719303] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.719608] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.719680] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.719873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.736704] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.736770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.736821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.736871] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.736917] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.736966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.737013] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.737059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.737112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.737159] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.737203] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.737212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.737263] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.737270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.737323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.737370] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.737414] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.737517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.737565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.737615] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.737666] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.737719] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.737767] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.737817] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.737867] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.737918] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.738023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.738100] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.738149] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.752982] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.769730] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.769857] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.769953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.770311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.770361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.770405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.770536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.770580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.770623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.770666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.770709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.770752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.770798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.770851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.770897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.770975] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.771020] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.771075] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.771127] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.771176] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.771225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.771275] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.771321] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.771361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.772006] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.772970] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.773021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.773066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.773111] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.773153] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.773198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.773244] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.773288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.773331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.773373] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.773415] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.773519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.773568] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.773577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.773621] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.773667] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.773710] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.773753] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.773796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.773841] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.773883] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.773931] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.773976] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.774020] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.774064] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.774108] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.774193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.774253] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.774298] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.774524] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.774567] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.774885] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.774949] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.774992] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.775052] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.775413] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.775819] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.775871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.775916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.775960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.776003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.776048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.776092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.776135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.776179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.776224] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.776277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.776325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.776406] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.776496] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.778022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.778070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.778116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.778987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.779037] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.779867] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.779919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.781067] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.783219] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.784273] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.784580] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.784642] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.784829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.801540] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.801587] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.801633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.801677] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.801719] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.801764] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.801807] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.801850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.801893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.801935] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.801977] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.801986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.802028] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.802034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.802077] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.802120] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.802163] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.802205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.802248] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.802294] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.802336] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.802381] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.802425] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.802527] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.802573] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.802621] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.802699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.802755] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.802799] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.818009] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.834687] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.834800] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.834887] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.835212] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.835256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.835299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.835343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.835385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.835428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.835522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.835569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.835615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.835660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.835707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.835754] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.835821] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.835863] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.835917] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.835966] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.836013] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.836059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.836104] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.836149] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.836188] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.836760] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.837185] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.837230] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.837276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.837321] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.837364] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.837408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.837482] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.837529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.837575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.837620] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.837663] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.837672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.837714] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.837720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.837763] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.837806] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.837850] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.837893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.837936] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.837981] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.838024] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.838070] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.838114] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.838157] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.838201] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.838244] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.838305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.838360] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.838403] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.838588] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.838626] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.838915] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.838969] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.839011] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.839069] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.839353] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.839683] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.839728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.839772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.839815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.839859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.839902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.839946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.839989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.840032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.840076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.840124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.840170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.840244] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.840288] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.841717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.841760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.841805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.842566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.842609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.843321] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.843365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.844407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.846508] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.847519] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.847724] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.847777] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.847947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.864747] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.864793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.864838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.864882] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.864924] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.864967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.865010] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.865053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.865096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.865138] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.865180] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.865189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.865231] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.865237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.865279] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.865322] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.865364] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.865407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.865483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.865530] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.865575] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.865621] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.865667] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.865712] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.865757] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.865802] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.865867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.865917] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.865962] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.881156] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.899701] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.899813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.899902] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.900224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.900268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.900311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.900354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.900397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.900501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.900547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.900591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.900635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.900681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.900727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.900772] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.900833] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.900875] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.900930] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.900978] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.901024] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.901071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.901117] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.901161] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.901200] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.901773] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.902194] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.902238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.902283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.902327] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.902369] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.902413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.902489] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.902534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.902580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.902627] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.902670] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.902680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.902721] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.902727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.902770] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.902813] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.902855] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.902898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.902941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.902986] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.903029] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.903074] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.903118] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.903161] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.903205] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.903248] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.903308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.903362] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.903405] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.903586] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.903623] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.903912] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.903966] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.904008] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.904064] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.904348] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.904674] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.904719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.904763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.904807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.904850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.904894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.904937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.904980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.905023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.905067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.905115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.905160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.905234] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.905278] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.906751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.906794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.906838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.907628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.907673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.908387] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.908431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.909488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.911583] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.912612] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.912822] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.912876] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.913045] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.929842] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.929890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.929936] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.929979] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.930021] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.930065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.930109] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.930152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.930195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.930237] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.930279] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.930288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.930329] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.930335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.930378] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.930421] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.930504] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.930551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.930596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.930643] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.930690] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.930736] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.930781] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.930827] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.930872] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.930915] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.930987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.931039] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.931083] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.946260] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.964797] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.964911] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.964999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.965320] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.965365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.965409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.965509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.965553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.965596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.965639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.965683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.965727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.965771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.965818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.965863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.965932] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.965975] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.966029] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.966079] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.966125] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.966171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.966217] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.966261] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 553.966301] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 553.966881] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.967312] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.967357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.967403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.967476] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.967523] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.967568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.967612] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.967655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.967698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.967741] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.967784] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.967794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.967835] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.967842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.967885] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.967929] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.967972] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.968015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.968058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.968103] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.968146] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.968192] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.968235] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.968279] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.968323] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.968366] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.968428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.968506] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.968552] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.968706] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 553.968744] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 553.969033] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 553.969087] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.969129] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 553.969187] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 553.969509] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.969835] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.969880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 553.969923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.969967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.970011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.970054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 553.970097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 553.970141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 553.970184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 553.970228] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 553.970276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 553.970323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.970397] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 553.970465] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.971880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.971923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.971968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 553.972746] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.972789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 553.973510] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 553.973553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 553.974587] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 553.976673] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 553.977692] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 553.977889] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 553.977943] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 553.978114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.994861] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 553.994908] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 553.994953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 553.994997] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 553.995039] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 553.995083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.995126] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 553.995169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.995212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 553.995254] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.995296] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 553.995305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.995347] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 553.995353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.995396] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 553.995509] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 553.995557] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 553.995600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 553.995643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 553.995691] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 553.995733] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 553.995777] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 553.995820] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 553.995863] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.995906] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.995950] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 553.996015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 553.996067] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 553.996111] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.011335] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.029830] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.029942] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.030030] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.030355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.030399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.030501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.030545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.030588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.030631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.030673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.030716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.030760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.030804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.030851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.030896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.030964] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.031008] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.031062] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.031113] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.031159] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.031205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.031251] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.031295] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 554.031334] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 554.031919] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.032347] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.032392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.032473] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.032520] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.032564] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.032608] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.032652] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.032695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.032738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.032782] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.032824] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.032835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.032877] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.032883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.032927] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.032970] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.033014] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.033057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.033100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.033145] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.033188] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.033233] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.033277] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.033320] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.033364] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.033407] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.033493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.033550] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.033595] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.033747] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.033784] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.034073] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 554.034127] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.034169] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.034227] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.034517] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.034837] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.034882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.034926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.034969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.035013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.035056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.035100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.035143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.035187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.035231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.035277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.035322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.035397] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.035465] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.036905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.036949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.036993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 554.037769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.037812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.038530] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 554.038574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 554.039608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 554.041696] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 554.042756] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.042942] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.042996] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.043166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.059901] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.059947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.059992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.060036] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.060078] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.060122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.060165] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.060208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.060251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.060293] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.060334] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.060343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.060385] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.060390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.060501] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.060547] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.060592] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.060635] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.060680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.060725] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.060767] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.060812] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.060854] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.060897] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.060940] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.060984] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.061045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.061097] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.061140] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.076389] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.094926] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.095039] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.095127] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.095496] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.095541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.095585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.095628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.095671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.095714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.095759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.095801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.095845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.095889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.095937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.095983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.096050] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.096093] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.096148] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.096198] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.096246] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.096294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.096340] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.096384] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 554.096423] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 554.096998] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.097425] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.097511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.097558] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.097603] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.097646] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.097690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.097734] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.097778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.097822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.097864] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.097907] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.097916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.097959] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.097965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.098009] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.098052] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.098096] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.098139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.098182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.098227] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.098270] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.098315] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.098359] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.098402] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.098468] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.098514] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.098578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.098633] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.098677] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.098830] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.098868] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.099157] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 554.099210] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.099253] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.099310] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.099637] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.099965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.100010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.100054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.100097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.100141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.100184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.100228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.100271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.100315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.100359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.100406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.100490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.100566] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.100610] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.102046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.102090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.102134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 554.102904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.102946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.103698] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 554.103742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 554.104784] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 554.106871] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 554.107861] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.108055] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.108109] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.108280] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.125044] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.125092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.125137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.125180] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.125223] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.125266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.125310] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.125353] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.125397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.125505] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.125548] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.125559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.125601] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.125610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.125653] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.125699] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.125743] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.125786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.125828] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.125873] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.125916] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.125961] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.126004] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.126047] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.126091] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.126134] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.126198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.126250] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.126293] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.141536] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.159683] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.159797] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.159886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.160210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.160254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.160297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.160340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.160383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.160427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.160517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.160563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.160609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.160654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.160705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.160751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.160813] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.160855] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.160908] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.160958] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.161005] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.161051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.161096] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.161141] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 554.161180] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 554.161756] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.162176] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.162221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.162265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.162309] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.162351] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.162395] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.162470] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.162515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.162561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.162606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.162650] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.162659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.162701] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.162707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.162750] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.162792] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.162835] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.162878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.162921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.162966] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.163008] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.163054] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.163097] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.163141] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.163184] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.163227] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.163289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.163343] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.163387] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.163563] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.163601] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.163889] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 554.163942] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.163984] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.164042] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.164327] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.164652] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.164697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.164741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.164785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.164828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.164872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.164915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.164958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.165002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.165046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.165093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.165138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.165212] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.165256] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.166695] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.166739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.166783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 554.167555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.167597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.168307] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 554.168351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 554.169389] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 554.171499] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 554.172526] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.172712] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.172765] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.172935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.189708] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.189755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.189800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.189844] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.189886] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.189929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.189972] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.190015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.190058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.190101] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.190142] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.190151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.190193] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.190199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.190242] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.190284] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.190327] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.190369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.190411] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.190490] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.190534] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.190581] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.190627] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.190672] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.190718] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.190763] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.190826] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.190877] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.190923] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.206157] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.224698] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.224811] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.224899] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.225226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.225270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.225313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.225356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.225399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.225600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.225643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.225686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.225729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.225774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.225820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.225865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.225928] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.225971] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.226025] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.226075] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.226121] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.226167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.226213] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.226256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 554.226296] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 554.226881] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.227295] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.227339] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.227385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.227429] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.227499] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.227544] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.227590] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.227635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.227678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.227721] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.227763] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.227771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.227813] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.227819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.227864] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.227907] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.227951] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.227994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.228037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.228082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.228125] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.228170] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.228213] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.228257] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.228300] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.228344] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.228407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.228485] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.228531] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.228684] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.228722] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.229011] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 554.229064] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.229106] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.229164] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.229490] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.229814] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.229858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.229902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.229946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.229989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.230032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.230075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.230119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.230162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.230206] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.230252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.230297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.230372] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.230415] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.231876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.231919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.231963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 554.232744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.232787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.233526] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 554.233573] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 554.234619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 554.236705] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 554.237764] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.237957] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.238011] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.238181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.254911] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.254958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.255003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.255046] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.255089] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.255133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.255176] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.255219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.255262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.255304] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.255346] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.255355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.255396] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.255470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.255519] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.255562] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.255608] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.255651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.255694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.255739] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.255781] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.255825] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.255869] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.255914] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.255957] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.256000] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.256065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.256119] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.256163] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.271402] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.289959] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.290073] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.290160] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.290504] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.290549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.290593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.290636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.290679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.290722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.290767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.290809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.290853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.290897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.290944] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.290990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.291051] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.291094] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.291148] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.291198] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.291244] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.291290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.291336] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.291380] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:08 BXT-2 kernel: [ 554.291419] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:08 BXT-2 kernel: [ 554.291993] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.292405] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.292483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.292530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.292575] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.292617] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.292661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.292704] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.292748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.292792] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.292834] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.292877] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.292887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.292928] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.292935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.292978] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.293021] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.293065] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.293108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.293151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.293196] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.293239] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.293284] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.293328] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.293371] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.293415] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.293479] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.293541] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.293594] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.293640] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.293789] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:08 BXT-2 kernel: [ 554.293827] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:08 BXT-2 kernel: [ 554.294124] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:08 BXT-2 kernel: [ 554.294177] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.294219] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:08 BXT-2 kernel: [ 554.294277] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:08 BXT-2 kernel: [ 554.294620] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.294938] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.294983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:08 BXT-2 kernel: [ 554.295026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.295070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.295113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.295157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:08 BXT-2 kernel: [ 554.295201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:08 BXT-2 kernel: [ 554.295244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:08 BXT-2 kernel: [ 554.295288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:08 BXT-2 kernel: [ 554.295331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:08 BXT-2 kernel: [ 554.295378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:08 BXT-2 kernel: [ 554.295423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.295543] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:08 BXT-2 kernel: [ 554.295587] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.297019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.297062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.297106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:08 BXT-2 kernel: [ 554.297895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.297937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:08 BXT-2 kernel: [ 554.298693] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:08 BXT-2 kernel: [ 554.298737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:08 BXT-2 kernel: [ 554.299802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:08 BXT-2 kernel: [ 554.301889] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:08 BXT-2 kernel: [ 554.302910] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.303106] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:08 BXT-2 kernel: [ 554.303160] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:08 BXT-2 kernel: [ 554.303331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.320088] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:08 BXT-2 kernel: [ 554.320134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:08 BXT-2 kernel: [ 554.320179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:08 BXT-2 kernel: [ 554.320223] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:08 BXT-2 kernel: [ 554.320266] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:08 BXT-2 kernel: [ 554.320310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.320353] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:08 BXT-2 kernel: [ 554.320396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.320509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:08 BXT-2 kernel: [ 554.320552] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.320594] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:08 BXT-2 kernel: [ 554.320603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.320645] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:08 BXT-2 kernel: [ 554.320651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.320694] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:08 BXT-2 kernel: [ 554.320737] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:08 BXT-2 kernel: [ 554.320781] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:08 BXT-2 kernel: [ 554.320824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:08 BXT-2 kernel: [ 554.320867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:08 BXT-2 kernel: [ 554.320913] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:08 BXT-2 kernel: [ 554.320955] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:08 BXT-2 kernel: [ 554.321001] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:08 BXT-2 kernel: [ 554.321045] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:08 BXT-2 kernel: [ 554.321088] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.321132] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.321176] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:08 BXT-2 kernel: [ 554.321240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:08 BXT-2 kernel: [ 554.321292] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:08 BXT-2 kernel: [ 554.321335] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:08 BXT-2 kernel: [ 554.336581] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.355086] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.355198] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.355286] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.355637] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.355682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.355727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.355770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.355814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.355857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.355901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.355945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.355988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.356032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.356079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.356125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.356194] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.356238] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.356292] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.356342] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.356388] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.356458] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.356507] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.356552] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.356592] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.357141] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.357612] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.357658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.357703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.357749] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.357791] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.357836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.357881] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.357924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.357968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.358012] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.358054] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.358064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.358105] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.358112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.358156] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.358199] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.358242] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.358285] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.358328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.358373] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.358416] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.358488] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.358535] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.358581] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.358626] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.358672] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.358735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.358788] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.358834] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.358987] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.359025] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.359315] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.359369] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.359411] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.359492] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.359782] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.360106] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.360150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.360195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.360238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.360282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.360326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.360369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.360413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.360493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.360540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.360590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.360636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.360711] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.360755] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.362194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.362238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.362282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.363054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.363097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.363845] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.363888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.364921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.367009] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.368046] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.368252] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.368305] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.368508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.385244] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.385290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.385335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.385379] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.385421] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.385527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.385572] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.385615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.385658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.385701] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.385743] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.385752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.385794] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.385801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.385844] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.385887] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.385931] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.385974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.386017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.386063] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.386106] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.386151] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.386195] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.386239] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.386282] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.386326] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.386391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.386467] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.386514] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.401686] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.420183] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.420296] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.420383] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.420715] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.420760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.420804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.420848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.420892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.420935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.420979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.421022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.421066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.421110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.421156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.421202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.421271] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.421314] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.421368] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.421419] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.421491] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.421540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.421587] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.421633] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.421672] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.422221] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.422693] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.422738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.422783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.422827] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.422869] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.422913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.422956] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.422999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.423042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.423085] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.423126] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.423135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.423177] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.423183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.423226] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.423269] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.423312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.423354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.423396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.423475] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.423519] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.423566] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.423612] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.423659] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.423704] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.423750] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.423814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.423867] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.423910] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.424063] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.424101] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.424391] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.424468] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.424512] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.424570] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.424860] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.425183] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.425227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.425272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.425315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.425359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.425402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.425484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.425529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.425574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.425621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.425669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.425715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.425788] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.425831] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.427271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.427315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.427360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.428131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.428174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.428898] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.428942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.429977] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.432066] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.433116] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.433309] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.433362] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.433568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.450294] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.450341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.450386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.450430] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.450535] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.450579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.450623] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.450666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.450710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.450753] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.450795] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.450804] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.450847] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.450853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.450897] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.450940] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.450984] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.451027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.451071] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.451116] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.451159] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.451205] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.451249] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.451292] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.451336] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.451379] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.451472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.451525] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.451570] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.466750] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.485251] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.485365] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.485510] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.485833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.485878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.485921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.485964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.486006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.486050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.486093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.486135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.486178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.486221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.486268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.486312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.486375] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.486417] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.486501] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.486553] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.486601] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.486649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.486695] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.486740] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.486779] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.487328] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.487775] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.487820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.487866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.487910] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.487953] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.487997] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.488041] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.488084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.488128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.488171] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.488213] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.488222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.488265] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.488271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.488315] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.488358] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.488402] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.488471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.488516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.488562] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.488607] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.488654] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.488698] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.488744] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.488789] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.488834] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.488897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.488949] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.488992] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.489140] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.489177] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.489489] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.489545] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.489585] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.489641] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.489933] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.490254] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.490298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.490342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.490385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.490429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.490519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.490564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.490607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.490650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.490694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.490742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.490788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.490865] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.490910] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.492341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.492385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.492429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.493224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.493266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.493991] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.494035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.495068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.497153] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.498095] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.498267] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.498320] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.498515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.515260] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.515307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.515352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.515396] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.515503] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.515547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.515594] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.515637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.515681] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.515723] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.515765] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.515774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.515815] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.515822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.515865] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.515909] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.515952] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.515995] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.516038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.516084] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.516126] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.516171] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.516215] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.516259] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.516303] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.516346] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.516409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.516490] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.516536] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.531717] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.550240] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.550354] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.550503] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.550823] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.550867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.550912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.550955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.550999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.551042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.551086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.551129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.551172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.551216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.551263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.551308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.551370] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.551413] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.551494] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.551545] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.551592] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.551639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.551684] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.551730] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.551769] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.552317] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.552769] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.552815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.552861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.552905] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.552948] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.552993] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.553037] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.553080] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.553124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.553167] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.553210] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.553219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.553262] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.553268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.553312] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.553355] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.553399] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.553476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.553519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.553566] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.553611] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.553657] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.553703] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.553748] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.553793] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.553840] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.553904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.553958] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.554004] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.554287] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.554326] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.554645] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.554701] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.554742] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.554798] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.555081] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.555402] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.555486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.555532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.555576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.555621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.555666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.555710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.555753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.555798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.555842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.555889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.555934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.556008] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.556051] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.557534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.557578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.557622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.558377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.558419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.559223] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.559267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.560327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.562424] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.563504] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.563694] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.563747] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.563916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.580684] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.580731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.580776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.580819] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.580861] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.580905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.580948] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.580991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.581034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.581077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.581118] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.581128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.581170] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.581176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.581219] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.581262] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.581304] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.581347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.581389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.581434] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.581509] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.581559] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.581605] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.581651] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.581696] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.581741] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.581806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.581857] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.581903] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.597131] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.614797] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.614911] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.615000] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.615323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.615367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.615410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.615808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.615852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.615896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.615940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.615983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.616028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.616072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.616120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.616166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.616230] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.616273] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.616328] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.616378] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.616424] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.616861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.616912] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.616956] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.616996] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.617631] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.618560] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.618605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.618651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.618697] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.618740] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.618786] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.618829] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.618874] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.618918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.618961] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.619003] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.619013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.619054] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.619061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.619105] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.619148] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.619191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.619235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.619278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.619323] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.619367] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.619412] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.619480] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.619524] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.619569] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.619615] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.619678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.619734] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.619777] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.619930] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.619968] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.620257] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.620312] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.620352] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.620408] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.620855] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.621172] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.621217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.621261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.621305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.621348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.621392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.621561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.621604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.621647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.621691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.621739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.621786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.621861] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.621905] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.623356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.623401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.623564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.624326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.624368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.625257] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.625303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.626552] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.628658] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.629752] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.629947] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.630000] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.630169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.646907] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.646954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.647000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.647043] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.647086] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.647130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.647173] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.647216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.647259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.647302] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.647344] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.647352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.647394] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.647793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.647853] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.647897] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.647941] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.647985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.648028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.648074] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.648117] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.648163] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.648207] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.648251] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.648295] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.648339] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.648406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.648803] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.648848] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.663390] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.681948] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.682062] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.682150] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.682773] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.682819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.682862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.682905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.682948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.682991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.683034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.683077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.683119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.683163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.683210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.683254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.683316] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.683358] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.683412] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.683841] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.683891] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.683939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.683989] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.684034] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.684074] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.685248] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.685920] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.685966] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.686012] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.686056] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.686098] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.686142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.686186] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.686228] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.686272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.686314] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.686356] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.686364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.686406] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.686776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.686835] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.686879] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.686923] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.686966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.687009] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.687054] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.687097] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.687142] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.687186] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.687230] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.687273] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.687317] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.687385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.687789] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.687835] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.687991] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.688029] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.688320] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.688373] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.688413] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.688802] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.689054] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.689376] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.689420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.689754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.689797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.689839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.689882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.689925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.689968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.690011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.690054] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.690104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.690148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.690223] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.690266] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.692058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.692104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.692148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.693185] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.693230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.694550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.696657] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.697754] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.697947] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.698001] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.698171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.714928] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.714974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.715020] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.715063] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.715105] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.715150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.715193] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.715236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.715279] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.715321] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.715363] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.715371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.715413] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.715782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.715841] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.715884] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.715928] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.715971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.716015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.716060] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.716104] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.716149] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.716193] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.716237] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.716281] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.716324] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.716394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.716884] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.716929] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.731383] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.748171] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.748285] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.748373] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.748952] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.748999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.749042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.749085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.749128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.749171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.749214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.749257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.749300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.749343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.749390] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.749729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.749795] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.749839] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.749894] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.749945] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.749993] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.750041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.750087] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.750131] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.750171] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.751343] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.751988] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.752033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.752079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.752123] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.752165] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.752209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.752253] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.752296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.752339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.752381] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.752423] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.752790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.752851] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.752858] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.752902] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.752945] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.752989] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.753032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.753075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.753121] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.753164] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.753210] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.753254] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.753298] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.753342] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.753386] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.753749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.753807] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.753851] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.754005] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.754043] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.754332] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.754385] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.754425] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.754884] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.755138] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.755765] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.755812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.755855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.755898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.755941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.755984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.756027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.756070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.756113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.756156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.756204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.756249] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.756323] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.756367] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.758096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.758141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.758185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.759132] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.759177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.760239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.762342] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.763333] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.763843] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.763899] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.764069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.780574] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.780621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.780667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.780711] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.780753] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.780797] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.780841] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.780884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.780928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.780970] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.781012] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.781021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.781062] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.781068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.781111] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.781154] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.781197] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.781240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.781282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.781327] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.781369] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.781414] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.781950] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.781995] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.782039] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.782083] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.782156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.782212] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.782256] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.797003] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.814872] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.814985] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.815073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.815395] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.815823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.815867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.815910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.815953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.815996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.816039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.816082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.816125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.816168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.816217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.816262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.816325] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.816368] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.816422] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.816837] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.816886] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.816934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.816983] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.817027] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.817066] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.818234] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.818876] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.818921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.818967] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.819010] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.819053] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.819097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.819140] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.819183] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.819226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.819268] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.819310] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.819319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.819360] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.819366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.819409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.819851] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.819895] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.819938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.819981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.820027] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.820069] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.820115] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.820158] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.820202] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.820245] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.820289] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.820355] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.820410] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.820779] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.820935] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.820973] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.821262] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.821315] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.821355] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.821411] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.821968] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.822289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.822334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.822377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.822420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.822742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.822786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.822829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.822871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.822914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.822957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.823005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.823050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.823124] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.823167] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.824823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.824868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.824913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.825818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.825865] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.826769] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.826816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.828176] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.829552] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.830676] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.830875] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.830928] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.831098] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.847838] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.847885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.847930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.847973] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.848015] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.848059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.848102] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.848145] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.848188] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.848231] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.848272] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.848281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.848323] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.848329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.848372] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.848414] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.848859] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.848902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.848946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.848991] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.849034] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.849079] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.849123] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.849167] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.849211] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.849254] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.849322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.849375] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.849419] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.864307] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.882833] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.882947] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.883035] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.883353] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.883398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.883792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.883835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.883878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.883921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.883964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.884007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.884050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.884093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.884141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.884186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.884248] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.884291] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.884344] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.884393] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.884737] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.884785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.884834] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.884878] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.884917] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.886090] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.886633] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.886679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.886724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.886768] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.886810] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.886854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.886898] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.886941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.886984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.887026] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.887068] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.887076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.887118] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.887124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.887167] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.887210] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.887253] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.887295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.887337] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.887382] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.887424] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.887669] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.887714] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.887758] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.887801] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.887845] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.887910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.887965] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.888008] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.888159] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.888197] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.888606] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.889109] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.889149] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.889206] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.889596] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.889916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.889960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.890003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.890046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.890091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.890133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.890176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.890220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.890263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.890306] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.890353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.890398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.890599] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.890643] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.892060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.892103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.892148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.892980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.893024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.893785] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.893829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.894942] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.897044] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.898074] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.898274] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.898328] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.898619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.915259] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.915306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.915352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.915395] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.915607] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.915652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.915698] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.915741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.915785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.915828] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.915871] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.915880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.915923] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.915929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.915974] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.916017] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.916061] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.916104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.916147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.916192] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.916235] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.916280] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.916324] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.916368] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.916411] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.916623] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.916691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.916743] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.916787] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.931698] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.950202] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.950315] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.950402] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.950891] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.950936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.950979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.951023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.951066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.951109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.951152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.951195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.951238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.951281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.951327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.951372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.951542] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.951587] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.951641] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.951692] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.951740] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.951786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.951832] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.951876] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 554.951915] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 554.952552] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.953434] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.953533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.953579] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.953622] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.953664] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.953711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.953755] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.953799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.953842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.953886] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.953928] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.953938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.953980] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.953988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.954031] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.954074] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.954118] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.954161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.954204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.954249] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.954292] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.954336] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.954380] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.954423] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.954493] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.954540] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.954608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.954664] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.954708] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.954847] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 554.954885] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 554.955185] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 554.955241] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.955284] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 554.955342] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 554.955595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.955920] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.955964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 554.956008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.956051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.956096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.956139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 554.956182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 554.956225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 554.956269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 554.956313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 554.956360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 554.956405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.956535] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 554.956578] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.958040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.958085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.958130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 554.958909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.958952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 554.959712] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 554.959755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 554.960807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 554.962905] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 554.963908] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.964112] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 554.964165] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 554.964336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.981093] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 554.981140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 554.981185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 554.981229] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 554.981271] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 554.981315] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.981358] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 554.981401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.981512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 554.981555] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.981597] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 554.981606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.981647] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 554.981653] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.981696] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 554.981740] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 554.981784] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 554.981827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 554.981870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 554.981916] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 554.981959] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 554.982004] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 554.982048] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 554.982091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.982135] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.982178] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 554.982243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 554.982295] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 554.982338] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 554.997585] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.016328] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.016483] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.016573] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.016900] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.016944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.016987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.017030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.017073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.017116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.017158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.017201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.017244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.017287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.017332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.017376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.017464] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.017510] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.017565] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.017616] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.017663] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.017709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.017755] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.017800] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 555.017839] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 555.018401] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.019374] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.019418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.019492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.019538] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.019583] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.019628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.019673] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.019717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.019760] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.019803] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.019846] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.019855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.019898] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.019904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.019948] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.019992] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.020035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.020078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.020121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.020166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.020209] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.020254] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.020298] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.020341] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.020385] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.020428] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.020512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.020566] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.020611] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.020766] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.020804] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.021094] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 555.021148] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.021190] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.021248] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.021559] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.021877] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.021921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.021964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.022007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.022049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.022092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.022135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.022178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.022221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.022264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.022310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.022355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.022428] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.022502] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.023923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.023966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.024010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 555.024776] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.024819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.025558] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 555.025603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 555.026658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 555.028764] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 555.029831] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.030023] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.030076] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.030247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.046989] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.047035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.047081] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.047124] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.047167] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.047211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.047254] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.047297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.047340] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.047383] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.047425] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.047496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.047544] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.047551] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.047595] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.047638] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.047682] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.047725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.047768] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.047814] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.047857] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.047902] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.047947] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.047990] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.048034] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.048077] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.048142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.048194] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.048238] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.063497] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.082014] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.082128] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.082215] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.082542] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.082587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.082631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.082675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.082719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.082762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.082806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.082849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.082893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.082936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.082983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.083028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.083090] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.083134] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.083188] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.083238] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.083284] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.083330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.083376] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.083420] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 555.083483] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 555.084034] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.084496] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.084541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.084586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.084631] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.084674] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.084718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.084762] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.084805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.084849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.084892] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.084935] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.084944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.084986] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.084993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.085037] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.085080] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.085124] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.085166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.085209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.085255] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.085297] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.085342] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.085386] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.085430] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.085496] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.085543] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.085606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.085661] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.085706] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.085865] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.085904] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.086194] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 555.086248] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.086290] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.086348] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.086671] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.086991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.087035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.087078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.087120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.087163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.087206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.087249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.087291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.087334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.087377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.087423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.087511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.087589] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.087633] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.089076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.089119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.089163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 555.089935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.089978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.090714] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 555.090758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 555.091816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 555.093920] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 555.094955] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.095152] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.095206] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.095376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.112126] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.112173] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.112217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.112261] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.112303] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.112347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.112390] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.112498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.112542] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.112586] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.112628] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.112638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.112679] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.112686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.112730] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.112773] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.112816] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.112859] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.112902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.112948] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.112991] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.113036] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.113080] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.113123] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.113167] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.113210] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.113272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.113324] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.113367] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.128570] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.147067] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.147180] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.147267] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.147643] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.147688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.147731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.147775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.147818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.147861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.147904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.147947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.147990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.148033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.148078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.148123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.148190] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.148232] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.148286] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.148335] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.148381] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.148426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.148498] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.148546] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 555.148587] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 555.149136] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.149594] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.149640] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.149685] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.149730] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.149772] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.149816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.149859] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.149902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.149945] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.149988] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.150029] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.150038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.150080] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.150086] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.150129] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.150172] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.150214] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.150257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.150299] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.150344] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.150386] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.150431] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.150500] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.150545] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.150592] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.150637] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.150702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.150757] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.150801] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.150959] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.150996] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.151286] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 555.151340] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.151382] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.151467] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.151759] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.152079] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.152123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.152167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.152210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.152253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.152297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.152340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.152384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.152428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.152513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.152563] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.152610] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.152686] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.152729] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.154167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.154211] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.154255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 555.155029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.155072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.155807] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 555.155851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 555.156893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 555.158983] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 555.159997] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.160195] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.160249] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.160418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.177178] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.177225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.177270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.177314] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.177356] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.177400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.177506] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.177549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.177594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.177636] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.177679] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.177689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.177732] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.177738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.177782] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.177826] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.177870] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.177912] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.177956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.178001] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.178044] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.178089] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.178133] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.178176] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.178220] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.178263] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.178327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.178379] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.178423] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.193633] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.212121] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.212234] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.212322] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.212652] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.212697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.212741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.212784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.212827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.212870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.212912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.212956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.212998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.213041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.213087] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.213132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.213199] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.213241] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.213295] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.213346] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.213391] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.213465] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.213512] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.213557] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 555.213597] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 555.214146] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.214605] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.214650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.214695] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.214739] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.214781] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.214827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.214870] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.214913] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.214956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.214999] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.215041] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.215049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.215091] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.215097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.215140] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.215183] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.215225] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.215268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.215310] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.215355] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.215397] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.215470] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.215516] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.215562] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.215607] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.215653] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.215717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.215772] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.215816] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.215973] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.216011] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.216301] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 555.216354] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.216397] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.216522] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.216769] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.217091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.217136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.217180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.217223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.217267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.217310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.217354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.217397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.217482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.217528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.217577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.217624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.217699] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.217742] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.219179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.219222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.219267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 555.220040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.220083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.220810] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 555.220854] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 555.221894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 555.223981] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 555.225020] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.225226] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.225279] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.225605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.242196] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.242243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.242288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.242332] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.242374] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.242418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.242525] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.242568] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.242611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.242654] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.242696] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.242706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.242748] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.242754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.242798] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.242841] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.242885] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.242928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.242971] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.243016] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.243059] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.243105] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.243148] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.243191] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.243236] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.243279] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.243343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.243395] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.243464] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.258667] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.277157] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.277270] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.277357] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.277680] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.277725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.277769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.277814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.277858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.277901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.277945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.277989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.278032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.278076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.278122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.278167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.278229] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.278271] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.278325] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.278375] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.278421] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.278492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.278540] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.278585] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 555.278625] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 555.279176] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.279633] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.279678] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.279722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.279766] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.279808] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.279852] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.279896] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.279938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.279981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.280023] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.280065] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.280074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.280115] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.280121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.280164] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.280207] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.280250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.280292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.280334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.280379] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.280421] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.280501] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.280549] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.280596] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.280641] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.280687] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.280756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.280811] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.280854] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.281029] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.281067] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.281359] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 555.281412] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.281481] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.281541] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.281830] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.282158] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.282203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.282247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.282290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.282333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.282377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.282420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.282505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.282550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.282598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.282646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.282692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.282769] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.282812] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.284223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.284266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.284310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 555.285085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.285128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.285867] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:09 BXT-2 kernel: [ 555.285911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:09 BXT-2 kernel: [ 555.286955] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:09 BXT-2 kernel: [ 555.289045] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:09 BXT-2 kernel: [ 555.290099] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.290300] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.290354] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.290577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.307269] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.307316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.307361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.307405] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.307511] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.307556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.307599] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.307643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.307687] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.307730] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.307773] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.307783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.307825] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.307832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.307875] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.307919] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.307963] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.308006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.308049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.308095] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.308137] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.308183] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.308227] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.308270] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.308314] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.308357] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.308423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.308499] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.308545] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.323721] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.342221] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.342334] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.342420] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.342804] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.342848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.342892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.342935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.342978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.343021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.343064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.343106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.343149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.343192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.343238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.343283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.343350] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.343392] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.343476] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.343527] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:09 BXT-2 kernel: [ 555.343574] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:09 BXT-2 kernel: [ 555.343623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.343669] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.343715] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:09 BXT-2 kernel: [ 555.343753] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:09 BXT-2 kernel: [ 555.344300] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.344747] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:09 BXT-2 kernel: [ 555.344792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:09 BXT-2 kernel: [ 555.344837] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:09 BXT-2 kernel: [ 555.344881] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:09 BXT-2 kernel: [ 555.344923] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:09 BXT-2 kernel: [ 555.344967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.345010] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:09 BXT-2 kernel: [ 555.345053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.345096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:09 BXT-2 kernel: [ 555.345139] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.345180] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:09 BXT-2 kernel: [ 555.345189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.345231] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:09 BXT-2 kernel: [ 555.345237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.345280] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:09 BXT-2 kernel: [ 555.345323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:09 BXT-2 kernel: [ 555.345365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:09 BXT-2 kernel: [ 555.345408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:09 BXT-2 kernel: [ 555.345482] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:09 BXT-2 kernel: [ 555.345531] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:09 BXT-2 kernel: [ 555.345576] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:09 BXT-2 kernel: [ 555.345622] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:09 BXT-2 kernel: [ 555.345668] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:09 BXT-2 kernel: [ 555.345713] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.345760] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.345806] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:09 BXT-2 kernel: [ 555.345870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.345923] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.345966] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:09 BXT-2 kernel: [ 555.346118] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:09 BXT-2 kernel: [ 555.346156] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:09 BXT-2 kernel: [ 555.346469] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:09 BXT-2 kernel: [ 555.346524] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.346565] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:09 BXT-2 kernel: [ 555.346621] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:09 BXT-2 kernel: [ 555.346907] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.347236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:09 BXT-2 kernel: [ 555.347281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:09 BXT-2 kernel: [ 555.347325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.347368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.347412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.347495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:09 BXT-2 kernel: [ 555.347542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:09 BXT-2 kernel: [ 555.347588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:09 BXT-2 kernel: [ 555.347634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:09 BXT-2 kernel: [ 555.347679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:09 BXT-2 kernel: [ 555.347726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:09 BXT-2 kernel: [ 555.347771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.347845] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:09 BXT-2 kernel: [ 555.347888] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:09 BXT-2 kernel: [ 555.349334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.349378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.349422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:09 BXT-2 kernel: [ 555.350218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:09 BXT-2 kernel: [ 555.350261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.350999] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.351043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.352082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.354171] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.355189] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.355383] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.355470] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.355642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.372373] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.372420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.372525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.372569] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.372612] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.372655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.372699] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.372743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.372787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.372830] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.372872] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.372883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.372924] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.372931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.372975] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.373018] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.373062] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.373105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.373148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.373194] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.373236] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.373281] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.373325] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.373369] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.373412] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.373480] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.373549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.373603] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.373651] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.388827] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.407333] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.407507] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.407597] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.407918] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.407963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.408007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.408049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.408094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.408137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.408180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.408223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.408266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.408309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.408354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.408399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.408495] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.408539] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.408594] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.408645] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.408691] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.408737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.408782] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.408826] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.408864] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.409413] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.409864] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.409909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.409954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.409997] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.410039] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.410083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.410127] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.410170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.410213] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.410255] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.410297] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.410306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.410348] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.410354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.410397] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.410477] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.410521] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.410567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.410611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.410660] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.410705] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.410752] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.410798] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.410844] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.410889] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.410934] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.410997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.411051] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.411094] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.411262] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.411301] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.411616] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.411672] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.411713] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.411769] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.412046] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.412375] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.412420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.412501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.412545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.412591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.412636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.412682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.412725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.412770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.412813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.412860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.412905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.412978] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.413022] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.414430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.414500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.414544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.415303] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.415345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.416083] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.416128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.417176] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.419266] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.420292] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.420557] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.420613] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.420788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.437511] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.437557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.437603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.437647] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.437689] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.437733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.437776] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.437819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.437862] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.437905] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.437946] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.437955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.437997] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.438003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.438046] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.438089] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.438132] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.438175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.438217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.438262] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.438304] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.438349] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.438392] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.438468] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.438514] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.438560] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.438625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.438677] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.438722] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.453911] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.472406] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.472566] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.472654] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.472973] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.473017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.473062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.473105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.473148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.473191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.473233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.473277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.473320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.473363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.473408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.473483] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.473554] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.473598] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.473653] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.473703] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.473749] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.473795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.473839] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.473882] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.473921] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.474501] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.474914] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.474959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.475004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.475047] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.475090] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.475133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.475177] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.475220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.475263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.475305] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.475347] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.475356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.475397] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.475435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.475483] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.475529] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.475574] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.475619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.475664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.475713] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.475756] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.475804] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.475848] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.475894] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.475938] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.475981] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.476045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.476099] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.476142] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.476294] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.476332] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.476646] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.476702] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.476743] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.476801] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.477088] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.477412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.477495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.477541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.477587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.477631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.477675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.477719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.477763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.477806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.477850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.477898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.477943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.478017] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.478061] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.479533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.479578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.479622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.480376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.480419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.481161] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.481204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.482265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.484362] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.485388] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.485632] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.485687] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.485858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.502650] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.502696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.502741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.502785] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.502828] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.502872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.502915] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.502958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.503001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.503043] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.503085] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.503094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.503136] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.503141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.503184] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.503227] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.503270] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.503313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.503355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.503400] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.503475] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.503523] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.503569] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.503614] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.503661] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.503706] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.503770] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.503822] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.503866] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.519072] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.537561] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.537673] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.537761] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.538082] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.538126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.538170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.538213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.538256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.538299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.538341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.538384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.538428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.538532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.538579] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.538627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.538695] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.538738] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.538792] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.538842] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.538889] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.538936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.538982] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.539026] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.539065] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.539643] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.540061] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.540105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.540150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.540194] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.540237] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.540280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.540324] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.540367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.540410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.540485] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.540529] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.540542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.540586] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.540594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.540639] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.540685] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.540731] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.540774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.540816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.540861] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.540904] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.540948] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.540992] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.541035] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.541079] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.541122] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.541184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.541238] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.541282] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.541461] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.541501] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.541793] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.541847] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.541889] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.541948] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.542232] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.542558] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.542603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.542646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.542690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.542734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.542777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.542821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.542864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.542908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.542951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.542998] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.543044] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.543118] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.543162] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.544575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.544619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.544663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.545418] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.545488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.546205] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.546249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.547290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.549382] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.550426] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.550656] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.550710] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.550880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.567676] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.567722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.567768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.567812] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.567854] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.567898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.567941] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.567984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.568027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.568070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.568111] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.568120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.568162] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.568168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.568211] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.568256] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.568298] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.568341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.568383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.568428] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.568502] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.568550] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.568596] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.568641] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.568688] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.568734] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.568799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.568849] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.568895] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.584079] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.602577] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.602690] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.602777] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.603101] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.603145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.603188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.603231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.603274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.603317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.603360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.603402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.603510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.603553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.603602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.603648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.603709] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.603751] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.603805] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.603855] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.603901] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.603948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.603994] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.604038] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.604077] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.604660] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.605080] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.605125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.605169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.605213] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.605255] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.605299] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.605342] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.605385] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.605428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.605501] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.605545] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.605557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.605601] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.605609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.605655] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.605701] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.605746] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.605790] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.605835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.605881] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.605922] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.605967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.606010] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.606053] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.606097] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.606140] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.606202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.606255] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.606298] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.606475] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.606514] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.606807] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.606860] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.606900] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.606957] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.607240] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.607563] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.607608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.607652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.607695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.607738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.607782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.607825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.607868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.607911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.607956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.608003] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.608048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.608123] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.608167] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.609637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.609682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.609727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.610517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.610560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.611278] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.611322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.612366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.614474] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.615522] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.615728] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.615781] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.615951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.632748] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.632795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.632839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.632883] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.632926] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.632969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.633012] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.633055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.633098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.633140] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.633182] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.633190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.633232] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.633238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.633281] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.633323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.633366] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.633409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.633483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.633532] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.633577] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.633623] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.633670] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.633716] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.633762] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.633808] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.633872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.633922] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.633965] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.649172] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.667716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.667829] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.667917] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.668241] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.668285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.668328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.668371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.668413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.668507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.668554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.668599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.668642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.668686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.668732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.668776] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.668838] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.668882] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.668936] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.668986] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.669032] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.669079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.669124] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.669168] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.669207] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.669785] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.670192] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.670236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.670281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.670325] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.670367] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.670410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.670484] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.670529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.670577] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.670621] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.670665] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.670676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.670719] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.670724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.670768] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.670814] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.670859] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.670901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.670943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.670988] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.671029] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.671074] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.671118] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.671162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.671205] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.671249] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.671310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.671363] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.671406] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.671579] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.671617] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.671906] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.671960] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.672000] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.672057] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.672351] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.672672] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.672717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.672761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.672804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.672847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.672891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.672934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.672978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.673021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.673065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.673112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.673157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.673231] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.673275] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.674717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.674760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.674804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.675575] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.675618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.676336] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.676380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.677469] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.679559] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.680624] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.680835] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.680889] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.681059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.697803] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.697851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.697896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.697940] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.697982] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.698027] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.698070] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.698113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.698156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.698199] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.698240] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.698249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.698291] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.698297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.698340] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.698383] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.698426] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.698548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.698591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.698638] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.698680] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.698726] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.698770] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.698813] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.698856] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.698900] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.698964] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.699018] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.699062] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.714249] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.732759] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.732873] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.732961] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.733282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.733326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.733370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.733412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.733519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.733563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.733606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.733649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.733693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.733736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.733784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.733832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.733900] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.733944] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.733998] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.734048] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.734094] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.734140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.734186] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.734230] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.734269] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.734850] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.735270] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.735314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.735359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.735403] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.735478] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.735524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.735571] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.735615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.735660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.735702] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.735744] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.735752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.735794] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.735801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.735845] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.735888] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.735932] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.735975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.736018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.736063] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.736106] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.736152] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.736196] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.736239] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.736283] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.736326] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.736389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.736465] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.736513] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.736666] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.736705] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.736994] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.737048] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.737090] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.737147] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.737434] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.737790] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.737835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.737879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.737923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.737967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.738010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.738054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.738097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.738140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.738184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.738232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.738278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.738352] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.738395] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.739831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.739875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.739919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.740715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.740758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.741485] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.741529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.742565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.744658] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.745663] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.745867] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.745921] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.746093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.762837] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.762885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.762930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.762973] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.763016] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.763060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.763103] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.763146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.763189] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.763231] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.763273] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.763282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.763324] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.763330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.763373] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.763416] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.763568] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.763611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.763657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.763702] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.763744] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.763789] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.763833] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.763877] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.763920] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.763963] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.764029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.764081] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.764124] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.779292] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.797807] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.797922] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.798010] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.798334] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.798378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.798421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.798523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.798567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.798610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.798652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.798696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.798740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.798783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.798831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.798876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.798944] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.798987] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.799042] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.799092] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.799140] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.799187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.799233] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.799278] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.799317] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.799906] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.800332] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.800377] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.800422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.800496] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.800541] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.800588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.800633] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.800677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.800720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.800763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.800804] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.800813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.800855] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.800861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.800907] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.800950] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.800993] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.801036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.801079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.801125] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.801167] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.801213] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.801256] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.801300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.801343] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.801386] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.801469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.801524] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.801570] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.801723] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.801761] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.802050] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.802104] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.802146] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.802204] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.802524] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.802847] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.802892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.802935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.802979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.803023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.803066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.803110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.803153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.803197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.803240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.803287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.803332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.803406] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.803478] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.804891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.804935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.804979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.805747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.805790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.806518] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.806562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.807608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.809708] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.810755] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.810942] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.810995] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.811166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.827916] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.827963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.828008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.828052] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.828094] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.828139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.828182] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.828225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.828268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.828310] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.828351] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.828360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.828402] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.828472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.828518] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.828565] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.828608] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.828650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.828692] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.828737] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.828779] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.828823] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.828867] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.828911] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.828954] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.828998] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.829060] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.829111] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.829154] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.844372] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.862899] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.863013] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.863100] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.863419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.863523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.863568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.863611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.863654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.863697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.863741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.863785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.863828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.863872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.863921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.863967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.864030] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.864073] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.864128] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.864178] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.864226] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.864274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.864320] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.864364] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.864403] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.864980] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.865377] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.865420] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.865502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.865551] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.865595] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.865641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.865685] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.865728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.865771] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.865814] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.865856] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.865866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.865908] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.865915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.865958] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.866002] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.866045] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.866088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.866131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.866176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.866219] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.866264] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.866308] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.866351] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.866395] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.866459] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.866523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.866578] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.866622] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.866778] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.866815] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.867104] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.867158] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.867201] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.867258] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.867564] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.867882] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.867927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.867970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.868014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.868057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.868100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.868144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.868188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.868231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.868274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.868321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.868366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.868464] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.868511] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.869924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.869967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.870011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 555.870789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.870833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 555.871580] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 555.871625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 555.872693] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 555.874782] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 555.875832] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.876026] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.876080] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.876250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.893009] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.893056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.893101] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.893145] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.893187] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.893231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.893274] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.893317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.893360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.893403] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.893512] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.893522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.893564] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.893570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.893613] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.893656] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.893699] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.893743] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.893786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.893831] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.893874] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.893920] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 555.893963] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 555.894007] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.894052] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.894095] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.894159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.894210] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.894254] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.909502] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:10 BXT-2 kernel: [ 555.927998] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:10 BXT-2 kernel: [ 555.928112] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.928200] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.928530] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.928575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.928618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.928662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.928705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.928749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.928793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.928836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.928880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.928924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.928972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.929017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.929085] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.929129] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.929184] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.929234] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.929282] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.929330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.929377] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.929421] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.929485] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.930035] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.930493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.930595] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.930632] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.930921] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.930980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.931024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.931066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.931109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.931152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.931197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.931241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.931284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.931327] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.931371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.931416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.931491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.931554] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.931599] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.931643] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 555.931685] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 555.932232] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.932657] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:10 BXT-2 kernel: [ 555.932722] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:10 BXT-2 kernel: [ 555.991423] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:10 BXT-2 kernel: [ 555.991882] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:10 BXT-2 kernel: [ 555.992675] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 555.993089] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 555.993137] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 555.993251] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 555.993295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 555.993340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 555.993384] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 555.993425] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 555.993846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.993890] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 555.993933] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.993977] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 555.994019] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.994060] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 555.994069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.994110] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 555.994116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.994159] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 555.994202] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 555.994245] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 555.994287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 555.994329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 555.994374] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 555.994415] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 555.995044] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.995087] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.995130] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 555.995198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.995252] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.995296] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 555.996161] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 555.996200] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 555.996625] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 555.997116] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.997159] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 555.997215] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 555.997715] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.998040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 555.998083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 555.998126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.998169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.998211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.998256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 555.998300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 555.998342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 555.998385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 555.998428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 555.998898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 555.998943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 555.999019] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 555.999063] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.000540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.000586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.000632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 556.001389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.001432] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.002215] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 556.002259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 556.003318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 556.005420] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 556.006506] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.023426] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.023533] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.023705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.056970] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.057018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.057063] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.057107] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.057149] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.057193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.057236] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.057279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.057323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.057365] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.057407] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.057483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.057532] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.057541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.057587] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.057633] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.057679] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.057723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.057769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.057815] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.057858] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.057904] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.057948] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.057992] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.058035] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.058102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.058154] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.058198] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.073524] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.092010] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.092123] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.092202] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.092526] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.092572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.092616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.092659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.092703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.092747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.092790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.092834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.092877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.092921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.092969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.093015] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.093084] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.093127] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.093181] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.093231] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.093280] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.093327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.093372] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.093416] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 556.093480] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 556.094029] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.094477] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.094524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.094570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.094614] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.094657] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.094702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.094746] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.094789] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.094834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.094876] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.094919] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.094929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.094971] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.094978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.095022] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.095065] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.095109] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.095152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.095195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.095240] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.095283] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.095328] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.095372] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.095416] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.095491] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.095555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.095610] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.095656] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.095809] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.095847] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.096137] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 556.096192] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.096234] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.096291] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.096623] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.096947] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.096991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.097034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.097077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.097120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.097163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.097206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.097248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.097291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.097334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.097381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.097426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.097541] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.097586] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.099031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.099075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.099119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 556.099897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.099940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.100698] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 556.100742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 556.101786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 556.103877] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 556.104880] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.105074] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.105128] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.105298] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.122057] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.122104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.122150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.122194] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.122236] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.122280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.122324] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.122367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.122410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.122512] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.122557] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.122569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.122611] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.122620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.122665] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.122709] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.122753] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.122796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.122839] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.122885] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.122928] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.122974] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.123018] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.123061] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.123104] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.123170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.123224] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.123268] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.138571] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.157062] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.157176] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.157257] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.157651] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.157698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.157742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.157785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.157828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.157871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.157913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.157956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.157999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.158042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.158091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.158136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.158201] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.158243] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.158297] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.158347] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.158392] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.158478] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.158528] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.158573] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 556.158613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 556.159165] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.159622] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.159667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.159712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.159755] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.159798] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.159841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.159885] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.159929] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.159972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.160014] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.160056] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.160065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.160107] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.160112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.160155] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.160198] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.160241] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.160283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.160325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.160370] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.160412] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.160485] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.160532] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.160579] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.160624] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.160689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.160743] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.160787] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.160940] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.160978] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.161267] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 556.161320] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.161362] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.161420] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.161730] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.162052] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.162096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.162139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.162181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.162224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.162267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.162310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.162352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.162395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.162480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.162531] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.162578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.162654] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.162698] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.164116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.164160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.164204] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 556.165009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.165052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.165783] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 556.165827] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 556.166867] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 556.168976] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 556.169996] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.170189] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.170244] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.170413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.187167] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.187213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.187259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.187302] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.187344] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.187389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.187433] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.187539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.187583] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.187626] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.187668] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.187678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.187720] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.187727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.187771] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.187813] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.187857] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.187901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.187944] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.187989] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.188032] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.188077] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.188120] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.188164] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.188207] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.188270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.188321] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.188365] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.203624] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.222135] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.222248] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.222327] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.222651] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.222696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.222739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.222782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.222825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.222868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.222911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.222954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.222997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.223040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.223085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.223130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.223192] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.223234] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.223288] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.223337] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.223382] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.223427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.223500] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.223547] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 556.223588] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 556.224146] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.224611] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.224656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.224701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.224745] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.224787] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.224831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.224874] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.224917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.224960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.225002] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.225044] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.225053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.225094] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.225100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.225143] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.225186] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.225228] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.225271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.225313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.225357] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.225399] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.225598] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.225641] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.225685] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.225728] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.225789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.225843] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.225886] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.226031] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.226069] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.226359] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 556.226413] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.226481] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.226540] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.226831] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.227157] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.227201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.227245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.227288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.227331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.227375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.227418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.227498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.227544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.227592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.227640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.227686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.227762] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.227806] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.229267] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.229313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.229358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 556.230137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.230181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.230911] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 556.230955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 556.231997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 556.234091] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 556.235135] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.235316] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.235370] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.235570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.252316] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.252363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.252408] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.252512] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.252555] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.252600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.252644] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.252687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.252732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.252774] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.252817] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.252827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.252870] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.252876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.252920] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.252963] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.253008] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.253050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.253093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.253139] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.253182] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.253228] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.253272] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.253315] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.253358] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.253423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.253503] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.253551] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.268765] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.287252] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.287367] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.287506] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.287834] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.287879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.287922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.287965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.288008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.288051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.288094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.288137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.288180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.288225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.288270] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.288315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.288384] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.288426] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.288508] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.288559] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.288606] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.288655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.288700] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.288743] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:10 BXT-2 kernel: [ 556.288782] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:10 BXT-2 kernel: [ 556.289328] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.289775] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.289821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.289866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.289910] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.289952] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.289996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.290040] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.290083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.290126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.290168] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.290210] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.290219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.290260] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.290266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.290309] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.290352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.290395] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.290473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.290517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.290566] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.290611] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.290658] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.290704] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.290750] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.290795] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.290861] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.290916] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.290959] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.291116] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:10 BXT-2 kernel: [ 556.291154] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:10 BXT-2 kernel: [ 556.291470] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:10 BXT-2 kernel: [ 556.291525] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.291566] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:10 BXT-2 kernel: [ 556.291622] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:10 BXT-2 kernel: [ 556.291910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.292237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.292281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:10 BXT-2 kernel: [ 556.292325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.292369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.292412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.292490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:10 BXT-2 kernel: [ 556.292537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:10 BXT-2 kernel: [ 556.292583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:10 BXT-2 kernel: [ 556.292629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:10 BXT-2 kernel: [ 556.292674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:10 BXT-2 kernel: [ 556.292724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:10 BXT-2 kernel: [ 556.292769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.292843] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:10 BXT-2 kernel: [ 556.292886] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.294329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.294373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.294417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:10 BXT-2 kernel: [ 556.295211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.295254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:10 BXT-2 kernel: [ 556.295996] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:10 BXT-2 kernel: [ 556.296040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:10 BXT-2 kernel: [ 556.297079] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:10 BXT-2 kernel: [ 556.299180] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:10 BXT-2 kernel: [ 556.300194] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.300370] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:10 BXT-2 kernel: [ 556.300424] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:10 BXT-2 kernel: [ 556.300629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.317343] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:10 BXT-2 kernel: [ 556.317391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:10 BXT-2 kernel: [ 556.317505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:10 BXT-2 kernel: [ 556.317550] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:10 BXT-2 kernel: [ 556.317592] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:10 BXT-2 kernel: [ 556.317636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.317681] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:10 BXT-2 kernel: [ 556.317725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.317769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:10 BXT-2 kernel: [ 556.317812] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.317854] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:10 BXT-2 kernel: [ 556.317864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.317907] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:10 BXT-2 kernel: [ 556.317913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.317957] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:10 BXT-2 kernel: [ 556.318000] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:10 BXT-2 kernel: [ 556.318044] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:10 BXT-2 kernel: [ 556.318087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:10 BXT-2 kernel: [ 556.318130] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:10 BXT-2 kernel: [ 556.318176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:10 BXT-2 kernel: [ 556.318219] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:10 BXT-2 kernel: [ 556.318264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:10 BXT-2 kernel: [ 556.318308] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:10 BXT-2 kernel: [ 556.318352] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.318395] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:10 BXT-2 kernel: [ 556.318486] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:10 BXT-2 kernel: [ 556.318543] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:10 BXT-2 kernel: [ 556.318589] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:10 BXT-2 kernel: [ 556.333819] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.352321] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.352494] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.352576] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.352898] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.352942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.352986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.353029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.353071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.353115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.353157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.353201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.353243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.353287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.353333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.353377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.353473] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.353519] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.353574] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.353624] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.353669] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.353715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.353758] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.353802] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.353842] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.354389] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.354836] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.354881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.354926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.354970] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.355012] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.355056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.355099] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.355143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.355186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.355228] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.355270] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.355279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.355321] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.355326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.355370] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.355412] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.355487] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.355532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.355577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.355624] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.355669] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.355717] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.355764] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.355810] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.355856] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.355920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.355974] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.356020] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.356174] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.356212] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.356526] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.356582] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.356622] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.356679] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.356965] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.357291] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.357336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.357380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.357424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.357505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.357551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.357598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.357643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.357686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.357729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.357776] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.357821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.357895] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.357939] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.359357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.359401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.359485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.360251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.360293] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.361026] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.361070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.362108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.364196] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.365192] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.365367] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.365421] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.365627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.382357] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.382404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.382511] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.382555] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.382598] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.382643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.382687] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.382731] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.382775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.382818] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.382861] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.382871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.382914] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.382920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.382964] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.383007] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.383051] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.383094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.383137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.383183] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.383226] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.383272] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.383316] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.383359] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.383402] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.383492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.383548] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.383594] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.398816] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.417316] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.417428] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.417570] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.417888] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.417932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.417976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.418019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.418061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.418104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.418147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.418190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.418232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.418275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.418321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.418365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.418427] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.418495] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.418553] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.418604] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.418653] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.418701] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.418746] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.418791] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.418830] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.419378] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.419824] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.419869] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.419913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.419957] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.419999] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.420043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.420086] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.420129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.420172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.420214] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.420255] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.420264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.420306] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.420312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.420354] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.420397] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.420470] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.420516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.420561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.420608] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.420652] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.420698] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.420744] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.420789] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.420836] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.420898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.420953] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.420996] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.421157] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.421194] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.421508] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.421565] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.421608] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.421665] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.421954] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.422282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.422326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.422369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.422412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.422499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.422545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.422590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.422636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.422681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.422724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.422772] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.422817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.422892] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.422936] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.424343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.424387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.424431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.425224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.425266] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.426019] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.426066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.427127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.429219] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.430233] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.430415] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.430508] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.430680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.447401] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.447501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.447546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.447590] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.447632] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.447676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.447720] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.447763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.447806] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.447848] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.447890] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.447899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.447940] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.447946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.447989] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.448032] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.448074] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.448117] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.448159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.448204] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.448245] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.448290] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.448333] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.448376] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.448418] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.448511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.448562] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.448608] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.463859] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.482367] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.482546] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.482628] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.482956] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.483001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.483044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.483087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.483130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.483173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.483215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.483258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.483301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.483344] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.483389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.483462] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.483528] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.483571] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.483625] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.483674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.483720] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.483765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.483809] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.483853] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.483892] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.484464] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.484888] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.484932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.484977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.485021] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.485063] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.485107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.485150] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.485193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.485235] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.485278] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.485319] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.485328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.485370] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.485376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.485418] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.485492] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.485537] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.485582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.485626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.485674] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.485719] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.485767] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.485812] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.485859] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.485905] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.485965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.486018] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.486061] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.486209] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.486246] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.486557] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.486613] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.486654] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.486710] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.486999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.487323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.487367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.487411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.487496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.487542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.487588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.487632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.487674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.487717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.487761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.487808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.487854] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.487929] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.487972] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.489389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.489467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.489514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.490274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.490317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.491050] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.491094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.492152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.494257] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.495280] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.495539] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.495595] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.495766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.512505] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.512553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.512598] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.512642] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.512684] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.512728] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.512771] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.512814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.512857] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.512899] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.512941] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.512949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.512991] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.512997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.513040] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.513082] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.513125] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.513167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.513209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.513255] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.513297] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.513341] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.513384] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.513427] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.513499] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.513561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.513614] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.513661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.528917] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.547416] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.547579] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.547658] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.547980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.548024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.548067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.548109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.548152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.548195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.548238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.548281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.548324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.548367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.548412] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.548487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.548552] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.548595] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.548650] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.548700] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.548746] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.548791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.548835] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.548879] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.548918] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.549501] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.549914] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.549959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.550003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.550047] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.550089] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.550133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.550176] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.550221] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.550264] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.550306] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.550348] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.550357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.550398] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.550436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.550482] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.550528] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.550573] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.550618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.550663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.550712] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.550755] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.550803] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.550849] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.550894] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.550937] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.551000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.551053] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.551095] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.551248] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.551286] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.551599] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.551655] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.551696] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.551752] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.552037] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.552356] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.552401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.552478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.552524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.552569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.552615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.552660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.552703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.552745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.552788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.552835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.552880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.552955] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.552999] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.554436] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.554512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.554556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.555321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.555364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.556105] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.556150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.557198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.559295] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.560257] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.560429] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.560544] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.560715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.577411] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.577511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.577556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.577600] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.577642] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.577686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.577730] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.577773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.577816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.577858] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.577900] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.577908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.577950] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.577956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.577999] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.578041] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.578084] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.578127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.578169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.578214] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.578256] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.578301] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.578344] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.578386] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.578429] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.578523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.578575] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.578621] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.593867] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.612370] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.612538] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.612620] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.612938] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.612983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.613026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.613069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.613111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.613154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.613197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.613240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.613283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.613325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.613371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.613415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.613506] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.613550] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.613605] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.613654] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.613701] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.613748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.613792] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.613836] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.613875] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.614423] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.614872] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.614916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.614961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.615005] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.615047] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.615091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.615133] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.615176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.615219] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.615261] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.615303] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.615312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.615354] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.615360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.615402] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.615477] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.615522] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.615567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.615612] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.615660] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.615705] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.615753] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.615799] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.615845] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.615890] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.615951] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.616004] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.616046] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.616199] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.616237] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.616547] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.616604] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.616644] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.616700] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.616986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.617312] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.617356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.617400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.617479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.617525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.617570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.617616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.617661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.617704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.617750] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.617796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.617841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.617914] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.617958] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.619414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.619495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.619540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.620298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.620341] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.621079] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.621124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.622164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.624253] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.625214] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.625391] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.625506] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.625677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.642386] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.642433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.642538] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.642582] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.642624] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.642669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.642712] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.642757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.642801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.642844] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.642886] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.642896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.642938] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.642945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.642988] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.643032] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.643076] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.643119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.643162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.643207] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.643250] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.643295] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.643339] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.643382] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.643426] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.643517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.643572] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.643618] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.658831] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.677322] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.677510] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.677595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.677916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.677961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.678004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.678047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.678090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.678133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.678176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.678219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.678263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.678307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.678353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.678398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.678505] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.678548] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.678605] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.678654] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.678700] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.678746] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.678791] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.678835] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.678875] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.679423] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.679861] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.679906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.679951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.679995] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.680037] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.680081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.680125] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.680167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.680210] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.680253] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.680295] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.680304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.680345] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.680351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.680394] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.680473] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.680518] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.680564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.680609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.680657] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.680702] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.680751] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.680796] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.680843] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.680888] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.680950] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.681004] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.681050] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.681205] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.681243] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.681557] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.681613] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.681654] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.681710] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.681999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.682322] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.682367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.682411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.682493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.682539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.682586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.682630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.682674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.682718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.682762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.682810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.682856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.682930] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.682974] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.684417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.684489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.684534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.685293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.685335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.686071] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.686114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.687156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.689247] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.690220] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.690413] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.690527] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.690698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.707405] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.707503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.707548] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.707593] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.707635] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.707679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.707722] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.707765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.707809] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.707851] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.707892] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.707901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.707943] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.707949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.707992] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.708034] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.708077] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.708119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.708162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.708207] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.708249] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.708293] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.708336] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.708379] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.708421] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.708518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.708571] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.708616] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.723853] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.741971] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.742084] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.742165] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.742502] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.742546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.742590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.742634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.742679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.742723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.742767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.742811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.742855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.742899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.742947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.742992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.743062] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.743105] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.743160] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.743210] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.743258] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.743305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.743350] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.743395] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.743467] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.744017] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.744424] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.744513] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.744560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.744605] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.744648] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.744692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.744737] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.744780] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.744824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.744868] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.744910] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.744920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.744962] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.744968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.745012] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.745056] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.745099] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.745142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.745185] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.745230] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.745273] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.745318] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.745362] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.745406] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.745473] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.745539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.745594] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.745640] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.745802] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.745840] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.746130] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.746184] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.746226] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.746283] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.746620] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.746943] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.746988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.747031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.747074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.747117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.747160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.747203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.747246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.747288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.747332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.747378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.747423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.747543] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.747587] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.749030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.749073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.749118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.749903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.749946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.750707] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.750751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.751800] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.753894] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.754924] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.755119] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.755173] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.755344] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.772070] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.772117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.772162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.772205] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.772247] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.772291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.772334] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.772377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.772420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.772532] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.772574] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.772587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.772628] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.772641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.772686] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.772728] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.772771] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.772815] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.772858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.772905] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.772947] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.772993] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.773037] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.773080] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.773123] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.773187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.773241] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.773285] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.788550] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.807047] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.807158] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.807236] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.807566] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.807612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.807657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.807700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.807744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.807788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.807831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.807874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.807918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.807963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.808009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.808054] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.808117] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.808160] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.808215] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.808265] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.808312] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.808357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.808401] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.808477] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.808519] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.809078] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.809524] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.809569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.809615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.809659] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.809703] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.809747] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.809792] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.809837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.809881] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.809923] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.809966] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.809975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.810017] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.810024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.810067] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.810110] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.810154] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.810197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.810240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.810285] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.810327] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.810372] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.810416] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.810487] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.810534] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.810597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.810651] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.810695] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.810842] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.810881] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.811177] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.811232] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.811273] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.811331] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.811643] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.811963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.812006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.812049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.812091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.812134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.812177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.812219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.812261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.812304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.812348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.812395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.812472] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.812547] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.812591] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.814014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.814058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.814102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.814900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.814944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.815724] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.815769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.816836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.818496] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.819502] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.819662] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.819718] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.819889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.836639] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.836685] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.836730] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.836774] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.836816] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.836859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.836902] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.836945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.836988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.837030] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.837072] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.837081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.837123] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.837129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.837172] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.837214] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.837257] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.837299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.837341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.837386] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.837428] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.837511] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.837557] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.837606] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.837651] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.837712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.837761] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.837805] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.853071] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.871564] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.871674] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.871753] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.872073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.872117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.872160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.872203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.872246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.872288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.872331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.872373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.872416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.872517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.872567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.872612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.872674] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.872718] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.872773] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.872823] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.872872] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.872919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.872964] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.873008] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.873047] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.873630] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.874041] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.874086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.874131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.874174] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.874216] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.874260] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.874303] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.874346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.874389] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.874431] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.874517] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.874529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.874572] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.874581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.874626] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.874671] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.874717] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.874761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.874804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.874852] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.874894] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.874940] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.874984] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.875027] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.875071] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.875135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.875189] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.875232] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.875385] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.875423] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.875757] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.875813] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.875856] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.875914] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.876171] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.876494] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.876538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.876581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.876625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.876667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.876710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.876753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.876795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.876838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.876880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.876926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.876971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.877043] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.877086] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.878571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.878618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.878663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.879421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.879528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.880250] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.880294] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.881344] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.883445] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.884514] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.884695] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.884750] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.884921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.901749] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.901795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.901840] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.901884] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.901927] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.901971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.902014] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.902057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.902100] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.902142] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.902184] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.902193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.902235] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.902241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.902284] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.902326] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.902369] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.902412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.902488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.902538] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.902583] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.902630] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.902677] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.902722] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.902769] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.902834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.902886] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.902930] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.918131] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.936724] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.936837] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.936916] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.937238] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.937281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.937325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.937368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.937410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.937510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.937557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.937600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.937644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.937688] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.937737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.937784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.937852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.937895] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.937949] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.938000] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.938048] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.938096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.938141] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.938185] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 556.938224] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 556.938806] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.939204] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.939249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.939294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.939338] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.939380] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.939424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.939502] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.939546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.939592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.939634] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.939677] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.939687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.939729] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.939735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.939779] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.939822] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.939866] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.939909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.939953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.939998] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.940041] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.940086] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.940130] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.940173] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.940217] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.940279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.940334] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.940377] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.940551] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 556.940589] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 556.940879] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 556.940933] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.940975] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 556.941032] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 556.941321] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.941649] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.941695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 556.941738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.941781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.941824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.941867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 556.941910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 556.941952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 556.941995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 556.942039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 556.942085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 556.942130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.942202] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 556.942246] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.943699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.943743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.943787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 556.944551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.944594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 556.945304] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 556.945348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 556.946399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 556.948516] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 556.949514] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.949706] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 556.949760] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 556.949931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.966691] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 556.966738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 556.966783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 556.966827] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 556.966870] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 556.966914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.966957] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 556.967000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.967043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 556.967086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.967127] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 556.967137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.967179] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 556.967184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.967228] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 556.967270] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 556.967313] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 556.967356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 556.967398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 556.967543] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 556.967586] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 556.967632] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 556.967676] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 556.967719] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.967763] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 556.967829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 556.967883] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 556.967927] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 556.983164] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.001703] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.001815] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.001894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.002219] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.002263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.002306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.002350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.002393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.002479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.002522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.002570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.002613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.002657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.002704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.002750] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.002818] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.002862] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.002917] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.002967] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.003016] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.003064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.003108] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.003152] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 557.003192] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 557.003770] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.004184] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.004228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.004273] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.004317] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.004359] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.004403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.004478] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.004522] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.004568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.004611] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.004654] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.004664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.004705] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.004712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.004756] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.004800] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.004844] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.004887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.004930] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.004975] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.005019] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.005064] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.005108] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.005152] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.005196] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.005258] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.005313] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.005357] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.005528] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.005567] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.005857] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 557.005911] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.005954] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.006012] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.006298] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.006622] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.006668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.006711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.006754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.006797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.006840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.006883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.006926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.006969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.007012] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.007059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.007104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.007177] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.007220] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.008700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.008743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.008788] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 557.009557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.009600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.010312] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 557.010356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 557.011395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 557.013500] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 557.014556] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.014728] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.014782] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.014952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.031773] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.031820] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.031866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.031909] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.031952] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.031995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.032039] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.032082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.032125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.032168] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.032209] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.032219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.032260] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.032266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.032310] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.032352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.032395] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.032475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.032518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.032568] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.032610] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.032656] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.032700] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.032743] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.032787] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.032851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.032903] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.032948] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.048225] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.066758] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.066870] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.066948] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.067266] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.067310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.067353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.067396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.067491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.067539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.067582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.067625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.067669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.067713] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.067761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.067806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.067875] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.067919] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.067973] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.068023] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.068071] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.068119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.068164] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.068209] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 557.068249] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 557.068829] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.069248] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.069295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.069340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.069384] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.069428] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.069500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.069545] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.069588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.069632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.069675] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.069718] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.069727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.069769] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.069776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.069820] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.069863] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.069907] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.069950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.069993] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.070039] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.070082] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.070127] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.070171] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.070215] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.070258] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.070321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.070376] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.070419] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.070589] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.070627] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.070917] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 557.070971] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.071013] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.071070] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.071360] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.071691] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.071737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.071781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.071824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.071868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.071911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.071955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.071999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.072047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.072090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.072138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.072186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.072261] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.072305] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.073740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.073784] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.073829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 557.074586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.074629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.075338] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 557.075382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 557.076483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 557.078573] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 557.079564] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.079737] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.079791] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.079960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.096773] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.096819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.096864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.096908] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.096950] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.096994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.097037] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.097081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.097124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.097167] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.097209] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.097218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.097260] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.097266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.097309] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.097352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.097396] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.097476] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.097519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.097569] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.097611] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.097657] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.097701] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.097745] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.097789] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.097853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.097905] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.097949] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.113233] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.131754] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.131866] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.131946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.132268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.132312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.132356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.132399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.132476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.132526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.132571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.132617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.132662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.132707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.132754] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.132802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.132869] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.132912] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.132965] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.133014] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.133060] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.133109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.133152] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.133196] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 557.133236] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 557.133874] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.134789] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.134834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.134879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.134923] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.134965] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.135009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.135053] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.135096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.135139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.135181] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.135223] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.135232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.135274] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.135280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.135323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.135366] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.135409] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.135482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.135528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.135575] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.135620] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.135667] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.135712] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.135758] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.135803] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.135868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.135922] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.135969] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.136117] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.136154] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.136468] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 557.136558] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.136600] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.136659] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.136950] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.137274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.137318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.137363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.137406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.137485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.137528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.137572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.137616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.137660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.137704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.137751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.137797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.137872] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.137915] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.139357] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.139401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.139485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 557.140245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.140288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.141003] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 557.141047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 557.142086] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 557.144186] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 557.145189] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.145372] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.145427] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.145665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.162321] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.162368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.162413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.162492] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.162539] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.162585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.162630] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.162674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.162721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.162763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.162805] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.162814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.162856] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.162862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.162905] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.162948] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.162993] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.163035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.163078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.163124] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.163166] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.163212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.163255] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.163299] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.163342] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.163403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.163476] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.163520] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.178834] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.196734] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.196848] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.196926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.197253] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.197297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.197341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.197384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.197427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.197503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.197551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.197597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.197643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.197689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.197739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.197785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.197854] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.197897] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.197950] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.198000] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.198046] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.198094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.198138] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.198183] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 557.198222] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 557.198818] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.199227] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.199274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.199319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.199366] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.199409] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.199525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.199569] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.199612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.199655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.199699] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.199743] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.199755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.199799] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.199808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.199854] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.199898] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.199944] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.199987] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.200030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.200075] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.200118] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.200165] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.200208] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.200252] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.200296] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.200364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.200419] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.200490] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.200637] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.200676] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.200965] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 557.201019] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.201060] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.201118] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.201403] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.201759] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.201805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.201851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.201897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.201942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.201987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.202031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.202075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.202119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.202163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.202210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.202255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.202328] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.202372] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.204372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.204418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.204629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 557.205401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.205635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.206365] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 557.206409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 557.207719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 557.209825] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 557.210866] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.211038] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.211092] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.211262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.228004] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.228050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.228095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.228139] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.228181] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.228225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.228268] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.228311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.228355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.228397] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.228924] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.228934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.228976] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.228981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.229025] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.229068] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.229111] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.229154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.229196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.229241] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.229283] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.229329] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.229372] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.229415] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.229997] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.230069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.230123] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.230166] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.244516] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.262742] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.262855] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.262935] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.263257] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.263300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.263344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.263387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.263430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.263885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.263929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.263972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.264015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.264058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.264106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.264151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.264220] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.264262] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.264316] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.264365] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.264411] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.265527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.265577] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.265620] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 557.265659] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 557.266205] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.266666] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.266713] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.266759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.266803] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.266846] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.266890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.266934] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.266978] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.267021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.267064] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.267106] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.267116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.267159] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.267165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.267209] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.267252] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.267295] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.267337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.267380] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.267425] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.267532] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.267580] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.267626] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.267671] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.267715] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.267780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.267835] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.267878] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.268007] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.268047] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.268343] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 557.268400] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.268482] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.268541] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.268828] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.269163] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.269206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.269249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.269292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.269335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.269377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.269420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.269573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.269617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.269661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.269711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.269757] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.269834] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.269878] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.271346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.271392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.271608] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 557.272383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.272426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.273332] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 557.273376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 557.274591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 557.276691] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 557.277719] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.277914] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.277969] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.278140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.294945] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.294993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.295039] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.295083] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.295125] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.295169] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.295212] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.295255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.295298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.295341] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.295383] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.295392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.295988] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.295996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.296040] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.296083] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.296126] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.296168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.296211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.296256] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.296298] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.296344] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.296387] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.296430] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.296963] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.297036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.297089] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.297133] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.311392] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.328756] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.328869] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.328949] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.329272] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.329317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.329360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.329403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.329812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.329855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.329899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.329942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.329985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.330028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.330077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.330122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.330190] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.330233] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.330286] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.330335] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.330381] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.330427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.331030] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.331074] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:11 BXT-2 kernel: [ 557.331113] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:11 BXT-2 kernel: [ 557.332283] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.332861] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:11 BXT-2 kernel: [ 557.332907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:11 BXT-2 kernel: [ 557.332953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:11 BXT-2 kernel: [ 557.332997] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:11 BXT-2 kernel: [ 557.333039] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:11 BXT-2 kernel: [ 557.333084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.333127] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:11 BXT-2 kernel: [ 557.333170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.333214] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:11 BXT-2 kernel: [ 557.333256] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.333298] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:11 BXT-2 kernel: [ 557.333307] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.333349] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:11 BXT-2 kernel: [ 557.333355] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.333398] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:11 BXT-2 kernel: [ 557.334222] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:11 BXT-2 kernel: [ 557.334266] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:11 BXT-2 kernel: [ 557.334309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:11 BXT-2 kernel: [ 557.334352] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:11 BXT-2 kernel: [ 557.334397] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:11 BXT-2 kernel: [ 557.334696] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:11 BXT-2 kernel: [ 557.334744] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:11 BXT-2 kernel: [ 557.334788] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:11 BXT-2 kernel: [ 557.334832] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.334875] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:11 BXT-2 kernel: [ 557.334944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.334998] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.335042] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.335195] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:11 BXT-2 kernel: [ 557.335233] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:11 BXT-2 kernel: [ 557.335961] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:11 BXT-2 kernel: [ 557.336268] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.336308] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:11 BXT-2 kernel: [ 557.336365] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:11 BXT-2 kernel: [ 557.336889] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.337209] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:11 BXT-2 kernel: [ 557.337253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:11 BXT-2 kernel: [ 557.337296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.337339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.337382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.337425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:11 BXT-2 kernel: [ 557.337817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:11 BXT-2 kernel: [ 557.337861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:11 BXT-2 kernel: [ 557.337904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:11 BXT-2 kernel: [ 557.337947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:11 BXT-2 kernel: [ 557.337995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:11 BXT-2 kernel: [ 557.338040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.338115] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:11 BXT-2 kernel: [ 557.338158] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:11 BXT-2 kernel: [ 557.339919] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.339965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:11 BXT-2 kernel: [ 557.340010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:11 BXT-2 kernel: [ 557.340949] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:11 BXT-2 kernel: [ 557.340997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:11 BXT-2 kernel: [ 557.342065] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:11 BXT-2 kernel: [ 557.343484] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:11 BXT-2 kernel: [ 557.344554] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:11 BXT-2 kernel: [ 557.344748] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:11 BXT-2 kernel: [ 557.344803] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:11 BXT-2 kernel: [ 557.344973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.361802] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.361849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.361894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.361938] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.361980] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.362025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.362068] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.362111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.362154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.362196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.362238] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.362247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.362290] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.362296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.362340] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.362383] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.362426] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.362941] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.362984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.363031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.363073] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.363120] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.363164] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.363207] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.363251] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.363318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.363373] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.363416] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.378194] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.395704] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.395817] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.395897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.396229] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.396273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.396316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.396359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.396401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.396526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.396570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.396617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.396660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.396704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.396753] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.396799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.396863] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.396906] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.396961] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.397012] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.397060] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.397108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.397153] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.397197] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.397237] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.397847] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.398812] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.398859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.398904] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.398948] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.398990] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.399034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.399078] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.399121] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.399164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.399206] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.399248] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.399256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.399298] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.399304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.399347] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.399389] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.399432] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.399605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.399649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.399696] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.399739] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.399788] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.399832] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.399876] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.399919] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.399987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.400044] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.400088] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.400251] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.400289] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.400627] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.400686] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.400728] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.400788] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.401050] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.401374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.401418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.401522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.401568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.401615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.401659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.401703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.401749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.401792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.401836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.401885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.401930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.402008] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.402051] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.403534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.403579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.403624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.404398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.404503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.405246] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.405292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.406331] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.407478] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.408667] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.408859] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.408914] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.409085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.426833] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.426880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.426925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.426969] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.427011] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.427055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.427099] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.427141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.427184] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.427226] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.427268] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.427278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.427319] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.427325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.427368] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.427412] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.428526] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.428570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.428613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.428658] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.428700] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.428746] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.428789] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.428832] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.428875] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.428943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.428998] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.429041] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.442227] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.459728] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.459841] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.459922] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.460246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.460290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.460334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.460376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.460419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.460595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.460639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.460683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.460727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.460771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.460820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.460865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.460928] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.460971] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.461027] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.461077] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.461124] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.461170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.461215] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.461259] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.461299] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.461898] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.462877] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.462924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.462971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.463016] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.463059] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.463104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.463149] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.463194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.463238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.463282] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.463324] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.463334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.463376] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.463383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.463427] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.463511] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.463555] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.463599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.463642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.463689] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.463732] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.463778] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.463822] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.463866] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.463909] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.463978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.464034] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.464078] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.464206] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.464244] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.464567] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.464624] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.464666] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.464724] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.466124] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.466526] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.466571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.466619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.466664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.466707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.466752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.466796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.466839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.466881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.466925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.466973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.467019] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.467095] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.467138] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.469670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.469716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.469760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.470555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.470598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.471313] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.471356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.472499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.474482] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.475493] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.475666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.475721] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.475908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.492696] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.492743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.492788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.492832] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.492874] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.492918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.492961] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.493003] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.493046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.493089] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.493130] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.493139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.493181] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.493187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.493230] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.493272] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.493315] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.493357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.493399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.493485] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.493532] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.493582] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.493627] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.493672] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.493719] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.493779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.493830] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.493875] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.509111] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.526802] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.526914] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.526994] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.527315] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.527359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.527402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.527498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.527543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.527590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.527635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.527679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.527723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.527766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.527813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.527859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.527923] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.527966] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.528021] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.528070] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.528118] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.528165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.528210] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.528254] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.528294] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.528874] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.529305] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.529350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.529395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.529479] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.529525] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.529572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.529617] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.529660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.529706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.529749] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.529792] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.529801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.529845] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.529852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.529896] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.529939] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.529982] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.530025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.530067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.530112] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.530155] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.530202] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.530246] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.530289] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.530332] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.530394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.530475] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.530522] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.530668] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.530707] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.531000] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.531054] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.531096] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.531153] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.531479] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.531812] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.531856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.531899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.531942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.531984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.532027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.532070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.532112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.532155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.532198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.532243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.532288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.532361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.532404] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.533876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.533920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.533964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.534747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.534790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.535509] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.535554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.536603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.538694] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.539686] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.539850] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.539904] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.540073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.556766] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.556811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.556856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.556899] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.556941] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.556985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.557028] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.557070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.557114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.557156] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.557198] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.557208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.557250] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.557256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.557299] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.557342] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.557384] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.557427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.557541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.557590] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.557634] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.557680] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.557724] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.557768] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.557811] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.557873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.557925] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.557969] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.573270] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.591768] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.591878] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.591955] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.592276] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.592321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.592364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.592407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.592496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.592544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.592587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.592631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.592674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.592718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.592766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.592811] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.592872] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.592915] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.592969] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.593019] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.593066] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.593112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.593156] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.593200] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.593239] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.593821] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.594223] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.594267] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.594312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.594355] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.594397] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.594481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.594527] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.594574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.594618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.594661] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.594704] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.594713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.594755] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.594761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.594806] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.594849] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.594892] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.594935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.594978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.595023] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.595066] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.595111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.595154] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.595197] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.595241] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.595303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.595357] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.595401] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.595570] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.595609] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.595904] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.595958] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.596000] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.596058] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.596300] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.596639] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.596684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.596727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.596769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.596812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.596855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.596898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.596940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.596982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.597025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.597071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.597116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.597189] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.597232] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.598710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.598753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.598797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.599567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.599610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.600358] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.600402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.601511] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.603602] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.604602] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.604772] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.604826] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.604996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.621728] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.621773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.621818] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.621861] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.621903] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.621946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.621990] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.622032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.622075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.622117] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.622159] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.622168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.622209] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.622215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.622258] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.622301] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.622344] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.622386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.622428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.622508] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.622552] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.622603] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.622649] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.622694] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.622740] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.622801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.623234] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.623277] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.638192] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.656670] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.656779] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.656856] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.657180] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.657224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.657267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.657310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.657353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.657395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.657477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.657527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.657572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.657617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.657665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.657865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.657925] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.657968] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.658022] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.658073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.658119] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.658165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.658209] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.658253] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.658292] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.658901] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.659846] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.659891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.659936] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.659980] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.660022] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.660065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.660108] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.660151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.660194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.660236] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.660278] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.660287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.660328] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.660334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.660377] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.660420] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.660504] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.660549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.660594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.660642] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.660686] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.660735] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.660781] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.660825] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.660868] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.660932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.660986] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.661030] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.661188] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.661226] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.661546] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.661603] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.661645] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.661703] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.662023] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.662347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.662391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.662478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.662523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.662567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.662610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.662654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.662697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.662740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.662783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.662832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.662877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.662951] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.662995] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.664404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.664478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.664522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.665279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.665321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.666063] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.666108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.667155] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.669252] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.670266] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.670434] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.670524] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.670694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.687384] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.687431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.687546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.687595] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.687638] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.687682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.687727] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.687770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.687814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.687857] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.687900] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.687909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.687951] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.687958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.688002] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.688045] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.688088] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.688131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.688174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.688220] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.688263] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.688307] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.688351] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.688394] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.688466] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.688530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.688584] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.688628] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.703871] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.722507] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.722621] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.722702] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.723024] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.723067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.723110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.723153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.723197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.723242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.723287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.723334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.723379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.723425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.723572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.723626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.723703] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.723748] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.723803] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.723855] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.723903] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.723951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.723997] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.724041] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.724080] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.724671] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.725108] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.725154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.725199] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.725243] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.725285] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.725329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.725372] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.725415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.725494] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.725538] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.725580] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.725589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.725632] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.725638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.725682] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.725725] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.725769] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.725812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.725856] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.725901] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.725944] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.725990] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.726034] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.726078] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.726122] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.726189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.726246] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.726289] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.726491] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.726530] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.726827] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.726882] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.726925] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.726983] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.727963] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.728292] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.728337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.728381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.728424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.728546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.728590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.728633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.728677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.728720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.728763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.728813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.728858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.728935] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.728978] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.730798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.730845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.730889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.731807] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.731853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.732757] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.732803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.734052] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.736173] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.737206] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.737370] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.737424] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.737645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.754320] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.754367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.754412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.754769] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.754811] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.754856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.754901] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.754943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.754986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.755029] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.755070] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.755079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.755121] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.755127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.755170] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.755212] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.755255] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.755297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.755340] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.755384] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.755426] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.755507] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.755553] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.755599] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.755644] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.755710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.755764] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.755808] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.770778] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.788878] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.788991] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.789069] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.789394] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.789489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.789537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.789581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.789625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.789669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.789712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.789756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.789799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.789843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.789891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.789936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.789999] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.790042] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.790096] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.790146] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.790192] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.790238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.790282] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.790326] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.790365] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.790949] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.791353] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.791398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.791481] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.791526] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.791570] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.791614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.791659] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.791702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.791747] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.791789] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.791832] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.791841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.791884] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.791890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.791934] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.791977] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.792020] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.792063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.792106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.792151] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.792194] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.792239] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.792282] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.792326] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.792369] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.792432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.792514] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.792560] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.792706] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.792745] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.793039] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.793093] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.793135] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.793193] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.793512] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.793841] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.793885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.793928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.793971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.794013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.794056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.794098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.794141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.794183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.794226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.794272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.794317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.794390] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.794467] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.795903] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.795948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.795992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.796779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.796823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.797629] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.797673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.798777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.800526] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.801643] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.801826] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.801882] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.802052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.818816] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.818863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.818909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.818952] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.818994] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.819038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.819082] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.819124] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.819168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.819851] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.820553] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.820660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.820708] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.820714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.820758] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.820801] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.820844] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.820887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.820929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.820974] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.821016] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.821062] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.821105] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.821148] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.821191] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.821256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.821310] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.821353] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.835228] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.852879] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.852994] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.853075] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.853392] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.853493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.853539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.853588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.853634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.853681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.853726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.853770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.853816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.853860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.853907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.853952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.854014] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.854056] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.854110] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.854160] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.854210] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.854264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.854319] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.854367] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.854409] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.855047] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.855558] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.855604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.855649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.855693] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.855735] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.855779] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.855823] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.855866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.855909] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.855951] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.855993] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.856002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.856044] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.856049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.856093] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.856135] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.856178] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.856220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.856262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.856307] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.856349] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.856394] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.856483] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.856529] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.856577] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.856643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.856700] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.856744] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.856889] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.856927] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.857219] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.857273] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.857316] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.857374] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.857679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.858012] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.858058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.858102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.858146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.858189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.858232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.858276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.858320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.858363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.858407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.858526] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.858572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.858648] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.858691] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.860127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.860174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.860218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.861024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:12 BXT-2 kernel: [ 557.861068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:12 BXT-2 kernel: [ 557.861842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:12 BXT-2 kernel: [ 557.861887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:12 BXT-2 kernel: [ 557.862623] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.862669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.863722] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.865842] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.866889] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.867068] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.867123] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.867293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.884011] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.884058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.884103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.884147] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.884188] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.884234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.884277] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.884319] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.884363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.884405] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.884512] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.884524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.884567] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.884579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.884625] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.884669] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.884712] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.884758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.884800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.884845] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.884887] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.884931] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.884974] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.885018] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.885061] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.885121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.885170] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.885213] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.900673] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.918874] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.918986] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.919065] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.919385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.919429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.919523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.919569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.919613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.919656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.919702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.919745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.919787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.919830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.919876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.919921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.919983] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.920026] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.920079] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.920128] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.920174] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.920220] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.920264] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.920308] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.920347] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.920925] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.921344] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.921388] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.921459] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.921505] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.921549] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.921593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.921636] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.921678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.921722] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.921764] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.921805] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.921814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.921858] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.921864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.921908] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.921952] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.921995] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.922038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.922081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.922126] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.922169] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.922214] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.922257] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.922300] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.922344] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.922404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.922485] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.922530] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.922668] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.922706] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.922993] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.923046] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.923088] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.923145] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.923374] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.923695] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.923739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.923781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.923824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.923868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.923911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.923955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.923997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.924041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.924084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.924130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.924175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.924249] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.924293] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.925734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.925778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.925822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.926582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.926625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.927338] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.927381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.928483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.930595] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.931662] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.931841] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.931896] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.932067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.948790] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.948837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.948883] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.948927] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.948969] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.949013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.949057] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.949100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.949143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.949185] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.949227] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.949236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.949278] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.949284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.949327] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.949370] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.949413] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.949496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.949543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.949591] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.949636] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.949685] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.949732] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.949778] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.949823] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.949890] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.949944] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.949991] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.965220] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.982691] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.982803] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.982882] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.983199] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.983243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.983286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.983329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.983371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.983414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.983943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.983986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.984028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.984071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.984120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.984164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.984227] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.984269] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.984323] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.984372] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.984417] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.984934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.984983] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.985026] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 557.985065] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 557.986235] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.986784] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 557.986829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 557.986875] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 557.986919] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 557.986961] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 557.987005] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.987049] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 557.987091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.987134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 557.987176] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.987218] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 557.987227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.987269] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 557.987274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.987317] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 557.987360] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 557.987403] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 557.988106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 557.988149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 557.988194] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 557.988236] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 557.988282] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 557.988325] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 557.988367] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.988411] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 557.988803] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.988858] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.988901] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.989052] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 557.989089] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 557.989378] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 557.989752] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.989796] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 557.989853] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 557.990106] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.990426] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 557.990759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 557.990803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.990846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.990888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.990931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 557.990974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 557.991017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 557.991059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 557.991102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 557.991150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 557.991195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.991268] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 557.991311] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 557.993185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.993229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 557.993273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 557.994116] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 557.994160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 557.995225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 557.997327] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 557.998361] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 557.998746] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 557.998802] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 557.998973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.015509] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.015555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.015600] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.015644] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.015686] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.015729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.015772] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.015815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.015858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.015900] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.015942] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.015950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.015992] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.015998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.016041] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.016083] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.016126] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.016168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.016210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.016255] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.016296] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.016341] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.016383] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.016426] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.017371] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.017544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.017602] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.017645] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.031990] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.049853] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.049965] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.050045] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.050370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.050414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.050798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.050841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.050884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.050927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.050970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.051013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.051056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.051099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.051147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.051192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.051255] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.051297] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.051350] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.051399] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.051993] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.052041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.052088] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.052131] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 558.052169] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 558.053335] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.053852] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.053896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.053942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.053985] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.054027] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.054071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.054114] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.054157] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.054200] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.054242] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.054284] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.054292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.054334] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.054339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.054382] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.054425] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.055089] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.055132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.055174] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.055220] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.055261] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.055307] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.055350] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.055393] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.055781] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.055847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.055901] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.055944] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.056088] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.056125] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.056414] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 558.057050] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.057090] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.057147] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.057377] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.057811] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.057857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.057903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.057946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.057989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.058032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.058075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.058118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.058160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.058203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.058251] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.058296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.058372] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.058414] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.060407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.060489] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.060534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 558.061302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.061345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.062374] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 558.062422] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 558.063795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 558.067379] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 558.068393] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.068818] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.068873] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.069042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.085783] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.085831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.085877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.085921] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.085963] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.086006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.086051] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.086094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.086137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.086179] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.086221] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.086229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.086271] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.086277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.086320] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.086363] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.086405] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.086499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.086545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.086596] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.086641] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.086688] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.086735] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.086780] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.086826] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.086888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.086939] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.086984] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.102202] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.119697] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.119810] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.119891] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.120217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.120262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.120306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.120349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.120392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.120490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.120536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.120588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.120634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.120678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.121008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.121056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.121118] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.121161] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.121215] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.121266] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.121314] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.121361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.121405] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.121484] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 558.121525] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 558.122081] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.122559] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.122605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.122654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.122698] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.122740] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.122785] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.122829] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.122872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.122916] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.122959] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.123001] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.123011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.123052] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.123059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.123103] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.123146] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.123189] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.123232] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.123274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.123319] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.123362] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.123407] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.123482] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.123525] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.123569] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.123632] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.123688] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.123732] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.123898] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.123936] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.124232] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 558.124286] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.124329] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.124388] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.125263] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.125865] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.125914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.125958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.126001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.126044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.126087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.126130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.126173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.126216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.126259] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.126309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.126354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.126430] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.126831] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.128335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.128381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.128426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 558.129493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.129539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.130284] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 558.130329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 558.131378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 558.133472] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 558.134527] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.134698] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.134753] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.134922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.151684] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.151731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.151777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.151821] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.151864] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.151908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.151952] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.151995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.152038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.152080] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.152123] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.152131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.152173] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.152179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.152222] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.152265] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.152308] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.152350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.152392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.152494] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.152537] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.152587] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.152630] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.152673] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.152718] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.152785] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.152841] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.152884] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.168119] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.186674] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.186787] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.186866] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.187184] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.187228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.187271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.187314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.187356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.187399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.187487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.187533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.187583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.187628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.187676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.187725] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.187786] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.187831] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.187885] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.187936] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.187982] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.188029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.188074] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.188119] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 558.188158] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 558.188760] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.189712] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.189757] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.189802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.189846] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.189888] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.189932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.189975] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.190017] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.190060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.190102] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.190144] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.190153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.190195] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.190201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.190243] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.190286] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.190329] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.190371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.190413] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.190490] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.190534] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.190582] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.190628] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.190674] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.190720] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.190780] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.190834] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.190877] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.191022] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.191060] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.191358] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 558.191413] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.191487] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.191548] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.191806] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.192128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.192173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.192216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.192259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.192303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.192346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.192390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.192433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.192517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.192562] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.192612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.192659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.192735] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.192779] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.194219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.194265] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.194309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 558.195092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.195136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.195899] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 558.195946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 558.197011] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 558.200363] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 558.201636] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.201830] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.201886] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.202059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.218763] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.218809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.218854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.218897] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.218939] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.218983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.219026] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.219069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.219112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.219154] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.219195] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.219204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.219246] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.219251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.219294] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.219337] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.219379] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.219422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.219503] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.219553] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.219598] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.219644] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.219689] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.219735] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.219780] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.219841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.219890] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.219935] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.235256] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.252772] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.252886] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.252965] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.253300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.253344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.253387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.253430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.253574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.253618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.253661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.253705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.253748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.253792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.253840] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.253885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.253947] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.253992] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.254045] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.254095] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.254141] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.254187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.254232] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.254275] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 558.254314] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 558.254906] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.255333] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.255378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.255424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.255501] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.255544] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.255590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.255634] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.255677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.255721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.255764] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.255806] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.255815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.255858] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.255864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.255908] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.255951] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.255994] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.256037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.256079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.256125] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.256167] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.256214] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.256257] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.256302] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.256346] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.256409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.256529] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.256572] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.256716] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.256754] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.257044] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 558.257097] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.257137] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.257195] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.257491] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.257824] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.257868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.257911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.257954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.257997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.258039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.258082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.258125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.258167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.258210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.258258] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.258303] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.258377] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.258420] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.259908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.259955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.259999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 558.260808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.260854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.261607] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 558.261654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 558.262755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 558.264561] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 558.265722] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.265894] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.265950] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.266119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.282836] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.282883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.282929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.282973] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.283015] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.283058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.283101] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.283144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.283187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.283229] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.283271] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.283280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.283322] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.283327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.283370] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.283413] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.283529] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.283575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.283618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.283664] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.283708] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.283754] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.283797] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.283840] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.283884] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.283948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.283998] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.284042] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.299318] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.317892] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.318005] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.318084] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.318403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.318481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.318531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.318579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.318625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.318669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.318716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.318759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.318803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.318846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.318893] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.318938] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.319001] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.319043] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.319096] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.319146] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.319191] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.319238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.319281] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.319325] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:12 BXT-2 kernel: [ 558.319363] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:12 BXT-2 kernel: [ 558.319949] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.320365] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.320409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.320551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.320595] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.320638] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.320683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.320727] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.320770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.320814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.320856] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.320899] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.320908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.320950] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.320957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.321001] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.321044] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.321087] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.321130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.321173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.321218] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.321260] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.321305] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.321349] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.321392] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.321457] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.321521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.321575] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.321621] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.321766] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:12 BXT-2 kernel: [ 558.321804] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:12 BXT-2 kernel: [ 558.322092] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:12 BXT-2 kernel: [ 558.322145] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.322187] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:12 BXT-2 kernel: [ 558.322244] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:12 BXT-2 kernel: [ 558.322511] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.322829] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.322873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:12 BXT-2 kernel: [ 558.322916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.322958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.323001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.323044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:12 BXT-2 kernel: [ 558.323086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:12 BXT-2 kernel: [ 558.323129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:12 BXT-2 kernel: [ 558.323171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:12 BXT-2 kernel: [ 558.323214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:12 BXT-2 kernel: [ 558.323260] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:12 BXT-2 kernel: [ 558.323304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.323376] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:12 BXT-2 kernel: [ 558.323419] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.324893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.324937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.324980] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:12 BXT-2 kernel: [ 558.325778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.325820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:12 BXT-2 kernel: [ 558.326627] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:12 BXT-2 kernel: [ 558.326674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:12 BXT-2 kernel: [ 558.327872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:12 BXT-2 kernel: [ 558.329514] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:12 BXT-2 kernel: [ 558.330556] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:12 BXT-2 kernel: [ 558.330734] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:12 BXT-2 kernel: [ 558.330789] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:12 BXT-2 kernel: [ 558.330959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.347689] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:12 BXT-2 kernel: [ 558.347736] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:12 BXT-2 kernel: [ 558.347781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:12 BXT-2 kernel: [ 558.347824] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:12 BXT-2 kernel: [ 558.347866] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:12 BXT-2 kernel: [ 558.347910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.347953] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:12 BXT-2 kernel: [ 558.347995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.348038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:12 BXT-2 kernel: [ 558.348080] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.348122] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:12 BXT-2 kernel: [ 558.348131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.348173] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:12 BXT-2 kernel: [ 558.348179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.348222] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:12 BXT-2 kernel: [ 558.348265] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:12 BXT-2 kernel: [ 558.348307] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:12 BXT-2 kernel: [ 558.348349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:12 BXT-2 kernel: [ 558.348391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:12 BXT-2 kernel: [ 558.348473] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:12 BXT-2 kernel: [ 558.348518] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:12 BXT-2 kernel: [ 558.348565] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:12 BXT-2 kernel: [ 558.348609] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:12 BXT-2 kernel: [ 558.348654] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.348700] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:12 BXT-2 kernel: [ 558.348761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:12 BXT-2 kernel: [ 558.348810] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:12 BXT-2 kernel: [ 558.348855] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.364145] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.381769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.381882] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.381962] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.382290] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.382334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.382378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.382421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.382541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.382589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.382634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.382679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.382724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.382768] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.382815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.382863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.382926] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.382968] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.383022] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.383071] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.383117] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.383162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.383206] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.383249] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.383288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.383883] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.384870] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.384916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.384962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.385006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.385048] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.385092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.385136] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.385179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.385222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.385264] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.385306] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.385315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.385357] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.385363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.385406] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.387349] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.387393] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.387797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.387840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.387886] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.387928] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.387975] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.388018] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.388061] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.388105] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.388174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.388229] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.388272] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.388434] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.389190] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.389814] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.390130] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.390172] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.390229] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.390996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.391326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.391369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.391413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.392017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.392061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.392104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.392147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.392190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.392233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.392276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.392327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.392373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.393217] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.393263] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.395179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.395225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.395269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.396294] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.396340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.397399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.399539] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.400601] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.400795] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.400850] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.401019] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.417793] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.417840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.417886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.417930] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.417972] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.418016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.418059] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.418101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.418145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.418187] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.418229] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.418237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.418279] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.418285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.418328] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.418371] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.418414] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.418904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.418947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.418994] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.419036] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.419083] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.419127] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.419170] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.419215] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.419281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.419335] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.419378] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.434233] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.451699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.451813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.451894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.452220] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.452264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.452308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.452350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.452393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.452493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.452540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.452586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.452629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.452674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.452723] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.452768] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.452829] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.452872] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.452925] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.452974] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.453020] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.453066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.453112] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.453156] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.453195] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.453778] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.454217] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.454262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.454308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.454352] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.454394] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.454491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.454536] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.454579] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.454623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.454666] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.454708] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.454718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.454759] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.454766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.454810] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.454853] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.454896] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.454939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.454982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.455027] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.455069] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.455115] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.455158] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.455201] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.455245] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.455310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.455364] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.455407] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.455600] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.455637] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.455928] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.455981] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.456022] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.456080] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.456526] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.456859] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.456903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.456946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.456989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.457032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.457074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.457117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.457160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.457202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.457245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.457292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.457337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.457411] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.457504] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.459077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.459122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.459166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.459975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.460019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.460834] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.460879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.461931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.464036] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.465050] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.465223] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.465279] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.465484] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.482181] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.482227] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.482272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.482315] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.482357] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.482401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.482512] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.482555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.482598] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.482640] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.482682] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.482691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.482734] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.482740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.482783] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.482826] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.482870] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.482913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.482955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.483002] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.483044] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.483090] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.483133] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.483177] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.483220] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.483285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.483339] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.483382] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.498646] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.516762] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.516876] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.516956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.517289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.517333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.517377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.517420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.517872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.517917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.517960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.518003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.518045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.518089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.518139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.518184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.518248] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.518291] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.518345] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.518394] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.518769] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.518816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.518864] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.518908] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.518947] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.520120] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.520858] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.520905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.520951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.520994] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.521037] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.521081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.521125] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.521168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.521212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.521254] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.521296] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.521304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.521346] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.521352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.521396] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.521852] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.521895] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.521939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.521981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.522027] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.522069] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.522116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.522160] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.522204] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.522247] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.522313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.522367] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.522410] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.522881] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.522919] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.523211] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.523265] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.523305] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.523361] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.523994] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.524325] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.524370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.524413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.524780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.524824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.524871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.524914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.524957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.525001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.525044] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.525095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.525140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.525215] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.525259] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.527250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.527296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.527340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.528209] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.528254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.529438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.531488] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.532475] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.532645] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.532701] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.532870] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.549679] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.549726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.549771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.549815] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.549857] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.549901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.549944] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.549987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.550030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.550072] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.550114] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.550123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.550165] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.550170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.550213] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.550256] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.550299] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.550341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.550383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.550428] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.551291] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.551339] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.551382] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.551425] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.551707] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.551777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.551833] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.551876] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.566078] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.584582] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.584693] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.584772] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.585092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.585136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.585179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.585222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.585265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.585308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.585350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.585393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.585489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.585532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.585578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.585624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.585687] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.585729] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.585783] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.585832] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.585878] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.585924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.585968] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.586011] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.586050] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.586623] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.587505] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.587552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.587597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.587641] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.587684] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.587731] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.587774] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.587817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.587861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.587903] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.587946] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.587956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.587998] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.588004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.588048] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.588093] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.588136] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.588178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.588221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.588267] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.588310] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.588355] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.588398] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.588464] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.588507] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.588571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.588625] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.588668] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.588820] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.588857] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.589147] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.589201] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.589242] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.589299] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.589830] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.590155] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.590199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.590242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.590285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.590328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.590370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.590413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.590533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.590576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.590619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.590667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.590712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.590787] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.590830] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.592365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.592410] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.592486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.593284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.593328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.594189] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.594233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.595492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.597584] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.598662] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.598911] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.598990] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.599206] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.615803] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.615850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.615895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.615938] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.615980] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.616024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.616069] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.616111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.616155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.616197] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.616238] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.616247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.616289] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.616295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.616338] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.616380] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.616423] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.616549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.616959] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.617005] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.617048] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.617095] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.617138] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.617182] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.617226] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.617291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.617344] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.617387] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.632274] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.649689] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.649802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.649881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.650198] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.650242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.650285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.650327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.650370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.650413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.650527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.650570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.650614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.650658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.650705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.650750] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.650810] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.650853] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.650907] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.650957] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.651005] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.651051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.651096] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.651140] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.651178] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.651761] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.652192] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.652238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.652284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.652327] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.652369] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.652414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.652502] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.652547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.652590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.652632] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.652675] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.652684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.652727] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.652733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.652778] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.652821] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.652864] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.652907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.652950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.652995] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.653038] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.653082] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.653126] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.653169] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.653213] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.653278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.653332] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.653375] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.653546] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.653584] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.653874] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.653928] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.653968] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.654025] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.654431] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.654888] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.654933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.654977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.655020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.655062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.655105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.655148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.655191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.655233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.655276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.655324] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.655368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.655483] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.655528] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.657067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.657111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.657155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.657945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.657991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.658763] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.658809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.659922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.662015] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.663069] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.663240] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.663294] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.663501] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.680250] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.680299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.680345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.680389] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.680431] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.680549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.680594] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.680637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.680680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.680722] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.680764] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.680773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.680815] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.680821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.680864] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.680907] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.680950] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.680992] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.681034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.681079] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.681121] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.681167] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.681210] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.681253] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.681296] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.681370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.681430] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.681506] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.696639] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.714689] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.714802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.714881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.715202] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.715246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.715289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.715332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.715374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.715417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.715918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.715961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.716004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.716047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.716095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.716140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.716203] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.716246] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.716299] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.716348] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.716394] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.716885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.716932] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.716975] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.717013] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.718178] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.718719] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.718763] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.718809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.718852] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.718894] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.718938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.718982] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.719024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.719067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.719109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.719150] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.719159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.719201] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.719207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.719249] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.719292] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.719335] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.719377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.719420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.720182] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.720225] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.720271] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.720314] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.720357] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.720400] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.720751] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.720806] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.720849] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.720997] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.721035] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.721323] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.721376] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.721416] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.721895] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.722128] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.722594] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.722639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.722683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.722726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.722769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.722812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.722855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.722897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.722940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.722982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.723030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.723074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.723148] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.723191] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.725131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.725177] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.725221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.726071] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.726116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.727181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.729280] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.730264] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.730653] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.730711] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.730881] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.747410] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.747505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.747551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.747594] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.747636] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.747680] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.747724] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.747767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.747810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.747853] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.747894] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.747903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.747945] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.747951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.747994] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.748037] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.748079] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.748122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.748164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.748209] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.748251] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.748296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.748339] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.748382] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.748425] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.748996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.749052] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.749095] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.763855] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.782358] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.782716] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.782800] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.783118] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.783163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.783210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.783254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.783299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.783345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.783389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.783432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.783920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.783963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.784011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.784056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.784120] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.784162] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.784215] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.784264] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.784309] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.784355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.784398] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.784886] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.784924] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.786089] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.786673] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.786718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.786767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.786811] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.786853] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.786897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.786940] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.786983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.787026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.787068] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.787110] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.787119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.787161] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.787166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.787209] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.787254] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.787296] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.787339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.787381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.787426] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.788206] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.788253] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.788296] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.788339] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.788382] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.788748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.788807] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.788850] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.789007] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.789044] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.789333] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.789386] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.789426] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.789873] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.790128] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.790646] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.790691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.790735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.790778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.790820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.790863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.790906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.790949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.790992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.791035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.791085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.791130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.791205] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.791248] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.793773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.793819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.793864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.794831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.794877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.795776] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.795822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.800084] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.801510] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.802489] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.802674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.802728] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.802898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.819680] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.819726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.819771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.819815] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.819857] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.819900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.819944] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.819986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.820029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.820071] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.820113] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.820122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.820164] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.820169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.820212] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.820255] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.820298] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.820340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.820382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.820427] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.820514] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.820561] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.820605] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.820650] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.820695] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.820756] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.820807] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.821204] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.836098] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.853930] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.854042] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.854121] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.854482] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.854765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.854810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.854853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.854897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.854941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.854984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.855027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.855070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.855114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.855162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.855207] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.855269] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.855312] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.855365] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.855415] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.855492] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.855538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.855583] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.855626] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.855665] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.856231] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.856752] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.856800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.856845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.856889] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.856931] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.856975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.857019] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.857062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.857105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.857146] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.857188] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.857197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.857239] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.857245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.857288] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.857331] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.857373] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.857416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.857497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.857543] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.857584] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.857630] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.857673] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.857717] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.857760] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.857824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.857877] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.857921] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.858070] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.858107] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.858397] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.858471] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.858513] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.858569] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.859391] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.859900] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.859945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.859989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.860032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.860075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.860117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.860160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.860202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.860245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.860288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.860335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.860380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.860492] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.860536] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.862254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.862299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.862343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.863175] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.863221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.864481] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.866578] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.867619] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.867803] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.867858] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.868030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.884816] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.884862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.884908] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.884951] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.884994] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.885038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.885082] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.885125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.885168] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.885210] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.885252] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.885261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.885303] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.885309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.885352] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.885394] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.886193] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.886236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.886278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.886324] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.886366] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.886413] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.886729] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.886774] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.886820] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.886924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.886998] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.887044] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.901242] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.918702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.918815] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.918894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.919215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.919259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.919302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.919345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.919388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.919431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.919546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.919589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.919634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.919678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.919724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.919769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.919830] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.919872] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.919927] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.919976] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.920022] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.920068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.920112] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.920155] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.920194] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.920774] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.921199] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.921244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.921290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.921333] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.921376] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.921420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.921537] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.921580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.921624] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.921667] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.921709] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.921719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.921761] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.921767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.921810] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.921854] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.921897] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.921940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.921982] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.922028] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.922071] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.922116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.922159] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.922202] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.922246] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.922311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.922365] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.922408] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.922625] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.922663] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.922952] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.923006] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.923048] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.923105] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.923542] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.923873] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.923917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.923961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.924004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.924048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.924091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.924134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.924177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.924219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.924262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.924308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.924353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.924426] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.924514] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.926144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.926189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.926233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.927169] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.927214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.928435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.930567] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.931607] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.931785] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.931839] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.932008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.948786] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.948832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.948877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.948921] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.948963] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.949006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.949049] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.949092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.949135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.949177] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.949219] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.949228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.949269] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.949275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.949318] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.949361] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.949403] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.950129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.950172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.950217] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.950259] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.950306] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.950349] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.950392] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.950742] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.950809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.950862] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.950905] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.965221] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.982778] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.982894] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.982975] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.983300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.983344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.983387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.983430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.983564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.983607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.983650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.983693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.983735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.983779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.983827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.983872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.983935] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.983977] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.984031] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.984081] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.984127] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.984172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.984216] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.984259] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 558.984298] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 558.984887] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.985308] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 558.985352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 558.985399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 558.985472] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 558.985515] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 558.985559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.985604] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 558.985647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.985691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 558.985734] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.985776] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 558.985785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.985828] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 558.985834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.985878] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 558.985921] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 558.985964] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 558.986007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 558.986050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 558.986095] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 558.986137] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 558.986182] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 558.986226] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 558.986269] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.986313] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 558.986375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.986429] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.986491] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.986640] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 558.986678] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 558.986968] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 558.987021] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.987064] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 558.987121] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 558.987381] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.987705] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 558.987749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 558.987793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.987836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.987879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.987922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 558.987965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 558.988008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 558.988052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 558.988095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 558.988141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 558.988186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.988260] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 558.988303] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 558.989733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.989779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.989824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 558.990757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.990802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 558.991620] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 558.991664] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 558.992860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 558.994501] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 558.995483] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 558.995665] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 558.995719] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 558.995890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.012669] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.012716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.012762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.012806] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.012849] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.012893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.012938] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.012982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.013026] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.013069] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.013118] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.013128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.013180] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.013186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.013238] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.013288] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.013338] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.013388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.013432] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.013566] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.013618] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.013673] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.013724] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.013774] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.013823] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.013927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.013999] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.014043] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.029100] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.047603] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.047715] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.047797] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.048115] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.048159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.048202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.048245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.048288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.048331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.048374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.048417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.048515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.048558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.048605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.048650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.048712] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.048756] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.048809] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.048859] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.048906] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.048952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.048997] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.049041] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 559.049079] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 559.049654] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.050064] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.050109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.050155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.050199] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.050241] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.050285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.050329] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.050373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.050416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.050505] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.050550] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.050559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.050601] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.050607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.050650] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.050693] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.050735] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.050777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.050823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.050870] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.050914] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.050964] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.051009] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.051055] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.051098] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.051161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.051215] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.051258] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.051407] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.051480] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.051778] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 559.051834] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.051875] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.051933] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.053528] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.053852] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.053897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.053940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.053983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.054026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.054068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.054111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.054154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.054196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.054239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.054288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.054333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.054407] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.054528] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.056352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.056398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.056473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 559.057324] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 559.057370] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 559.058628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 559.060737] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 559.061756] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.061945] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.061999] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.062169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.078900] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.078947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.078992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.079036] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.079078] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.079121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.079164] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.079208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.079251] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.079293] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.079335] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.079344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.079386] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.079392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.080080] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.080123] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.080166] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.080208] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.080250] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.080296] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.080337] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.080383] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.080426] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.080845] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.080890] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.080957] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.081012] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.081054] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.095381] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.113700] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.113813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.113892] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.114214] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.114258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.114301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.114343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.114386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.114429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.114525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.114570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.114616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.114661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.114709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.114755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.114815] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.114857] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.114911] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.114961] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.115006] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.115052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.115096] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.115140] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 559.115178] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 559.115758] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.116175] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.116221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.116266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.116310] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.116352] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.116396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.116518] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.116560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.116604] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.116647] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.116689] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.116699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.116740] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.116746] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.116791] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.116834] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.116877] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.116920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.116963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.117008] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.117051] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.117096] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.117139] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.117183] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.117226] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.117291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.117345] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.117388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.117566] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.117604] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.117894] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 559.117947] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.117987] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.118044] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.118806] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.119126] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.119170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.119213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.119255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.119298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.119341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.119384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.119427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.119509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.119554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.119600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.119646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.119720] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.119764] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.121397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.121467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.121511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 559.122269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.122311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.123280] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 559.123326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 559.124421] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 559.126511] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 559.127488] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.127650] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.127705] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.127876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.144611] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.144657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.144701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.144745] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.144787] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.144831] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.144874] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.144917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.144960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.145002] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.145044] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.145052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.145094] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.145100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.145143] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.145185] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.145228] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.145270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.145312] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.145357] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.145399] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.146264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.146307] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.146350] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.146393] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.146662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.146719] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.146763] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.161111] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.178836] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.178949] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.179028] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.179347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.179391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.179488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.179533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.179576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.179621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.179665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.179707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.179750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.179793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.179840] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.179884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.179948] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.179992] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.180046] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.180096] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.180141] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.180188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.180232] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.180276] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 559.180315] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 559.180897] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.181329] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.181374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.181422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.181506] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.181549] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.181593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.181637] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.181680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.181724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.181767] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.181809] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.181819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.181861] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.181867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.181911] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.181954] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.181997] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.182040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.182083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.182128] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.182170] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.182216] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.182259] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.182303] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.182346] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.182408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.182482] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.182525] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.182675] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.182712] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.183002] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 559.183055] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.183096] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.183153] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.184034] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.184364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.184408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.184769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.184813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.184856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.184899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.184941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.184984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.185027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.185070] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.185119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.185164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.185239] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.185282] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.187837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.187883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.187928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 559.189234] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 559.189285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 559.190946] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 559.192500] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 559.193513] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.193682] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.193737] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.193906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.210671] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.210717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.210762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.210806] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.210847] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.210891] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.210934] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.210977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.211020] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.211062] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.211104] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.211113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.211155] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.211161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.211204] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.211247] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.211289] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.211332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.211374] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.211418] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.211952] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.211999] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.212043] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.212087] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.212130] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.212196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.212250] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.212293] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.227105] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.244820] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.244933] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.245014] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.245342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.245386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.245429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.245525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.245570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.245616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.245659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.245703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.245748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.245791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.245839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.245884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.245948] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.245991] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.246045] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.246094] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.246141] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.246186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.246230] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.246273] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 559.246312] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 559.246950] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.247861] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.247907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.247954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.247998] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.248041] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.248085] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.248129] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.248172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.248216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.248259] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.248301] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.248310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.248353] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.248359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.248403] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.248478] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.248521] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.248564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.248608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.248654] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.248696] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.248741] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.248784] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.248828] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.248871] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.248932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.248985] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.249028] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.249177] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.249215] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.249525] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 559.249579] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.249619] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.249676] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.250249] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.250582] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.250628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.250672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.250716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.250759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.250802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.250845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.250888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.250930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.250973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.251023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.251068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.251144] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.251187] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.252623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.252667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.252711] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 559.253493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.253536] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.254248] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 559.254290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 559.255329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 559.257415] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 559.258379] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.258589] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.258644] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.258814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.275578] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.275624] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.275669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.275713] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.275755] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.275798] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.275842] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.275884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.275928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.275970] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.276011] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.276020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.276062] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.276068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.276111] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.276153] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.276196] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.276238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.276280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.276325] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.276963] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.277014] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.277059] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.277104] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.277149] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.277222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.277280] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.277325] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.292011] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.309934] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.310047] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.310127] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.310476] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.310522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.310569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.310612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.310655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.310699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.310742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.310786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.310829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.310873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.310921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.310967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.311030] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.311074] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.311129] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.311179] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.311227] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.311275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.311319] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.311363] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:13 BXT-2 kernel: [ 559.311403] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:13 BXT-2 kernel: [ 559.311979] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.312408] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.312517] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.312564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.312608] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.312652] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.312696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.312741] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.312784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.312828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.312871] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.312914] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.312923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.312966] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.312972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.313016] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.313061] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.313104] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.313147] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.313190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.313235] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.313278] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.313323] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.313367] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.313410] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.313476] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.313540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.313595] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.313641] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.313793] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:13 BXT-2 kernel: [ 559.313832] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:13 BXT-2 kernel: [ 559.314122] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:13 BXT-2 kernel: [ 559.314175] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.314215] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:13 BXT-2 kernel: [ 559.314271] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:13 BXT-2 kernel: [ 559.314513] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.314833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.314877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:13 BXT-2 kernel: [ 559.314920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.314963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.315006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.315048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:13 BXT-2 kernel: [ 559.315091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:13 BXT-2 kernel: [ 559.315134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:13 BXT-2 kernel: [ 559.315177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:13 BXT-2 kernel: [ 559.315220] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:13 BXT-2 kernel: [ 559.315266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:13 BXT-2 kernel: [ 559.315310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.315383] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:13 BXT-2 kernel: [ 559.315426] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.316933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.316978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:13 BXT-2 kernel: [ 559.317022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:13 BXT-2 kernel: [ 559.317958] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:13 BXT-2 kernel: [ 559.318006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:13 BXT-2 kernel: [ 559.319109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:13 BXT-2 kernel: [ 559.320545] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:13 BXT-2 kernel: [ 559.321654] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:13 BXT-2 kernel: [ 559.321866] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:13 BXT-2 kernel: [ 559.321922] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:13 BXT-2 kernel: [ 559.322096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.338824] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:13 BXT-2 kernel: [ 559.338871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:13 BXT-2 kernel: [ 559.338916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:13 BXT-2 kernel: [ 559.338960] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:13 BXT-2 kernel: [ 559.339003] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:13 BXT-2 kernel: [ 559.339047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.339090] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:13 BXT-2 kernel: [ 559.339133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.339177] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:13 BXT-2 kernel: [ 559.339219] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.339261] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:13 BXT-2 kernel: [ 559.339271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.339313] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:13 BXT-2 kernel: [ 559.339319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.339363] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:13 BXT-2 kernel: [ 559.339406] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:13 BXT-2 kernel: [ 559.339536] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:13 BXT-2 kernel: [ 559.339580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:13 BXT-2 kernel: [ 559.339626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:13 BXT-2 kernel: [ 559.339672] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:13 BXT-2 kernel: [ 559.339715] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:13 BXT-2 kernel: [ 559.339760] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:13 BXT-2 kernel: [ 559.339804] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:13 BXT-2 kernel: [ 559.339847] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.339890] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:13 BXT-2 kernel: [ 559.339955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:13 BXT-2 kernel: [ 559.340010] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:13 BXT-2 kernel: [ 559.340053] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.355314] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.372837] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.372950] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.373028] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.373349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.373392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.373492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.373535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.373582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.373627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.373671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.373714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.373757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.373800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.373848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.373893] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.373954] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.373997] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.374051] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.374101] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.374147] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.374193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.374237] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.374281] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.374320] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.374914] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.375325] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.375369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.375414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.375493] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.375540] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.375587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.375631] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.375675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.375719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.375762] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.375804] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.375813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.375855] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.375861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.375906] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.375949] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.375992] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.376035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.376078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.376123] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.376166] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.376211] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.376255] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.376298] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.376342] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.376403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.376483] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.376530] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.376756] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.376794] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.377084] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.377138] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.377178] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.377235] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.377511] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.377837] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.377881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.377924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.377966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.378009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.378051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.378094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.378136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.378179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.378222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.378268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.378312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.378385] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.378428] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.379915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.379959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.380003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.380777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.380819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.381543] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.381587] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.382622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.384717] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.385775] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.385970] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.386024] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.386196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.402920] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.402967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.403013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.403057] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.403099] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.403143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.403187] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.403230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.403273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.403315] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.403357] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.403366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.403408] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.403457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.403507] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.403552] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.403598] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.403643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.403689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.403736] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.403781] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.403829] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.403873] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.403917] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.403963] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.404030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.404083] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.404127] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.419385] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.437716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.437828] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.437909] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.438229] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.438273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.438316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.438359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.438401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.438485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.438531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.438577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.438622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.438666] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.438715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.438761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.438825] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.438868] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.438922] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.438972] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.439018] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.439064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.439108] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.439152] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.439191] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.439775] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.440198] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.440244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.440289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.440333] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.440376] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.440420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.440529] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.440572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.440615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.440657] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.440699] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.440708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.440750] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.440758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.440800] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.440843] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.440886] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.440929] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.440972] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.441018] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.441060] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.441106] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.441149] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.441193] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.441236] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.441304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.441359] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.441402] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.441577] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.441615] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.441905] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.441957] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.441999] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.442057] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.442558] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.442888] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.442932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.442975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.443018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.443061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.443103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.443146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.443189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.443232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.443274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.443321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.443366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.443484] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.443528] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.445116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.445161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.445205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.446042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.446086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.446885] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.446930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.447990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.450093] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.451082] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.451249] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.451303] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.451702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.468177] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.468224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.468269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.468312] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.468354] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.468398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.468824] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.468868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.468911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.468954] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.468996] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.469004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.469046] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.469052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.469095] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.469138] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.469181] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.469223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.469265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.469314] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.469356] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.469401] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.470046] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.470090] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.470133] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.470200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.470253] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.470296] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.484701] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.502687] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.502799] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.502879] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.503196] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.503240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.503284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.503326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.503369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.503411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.503493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.503538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.503581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.503624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.503672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.503717] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.503782] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.503824] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.503878] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.503927] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.503973] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.504019] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.504063] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.504106] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.504145] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.504727] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.505137] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.505182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.505228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.505273] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.505315] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.505361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.505406] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.505519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.505563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.505606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.505648] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.505658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.505699] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.505706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.505749] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.505792] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.505836] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.505878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.505921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.505966] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.506008] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.506053] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.506097] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.506141] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.506184] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.506250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.506304] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.506347] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.506701] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.506739] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.507030] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.507083] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.507124] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.507181] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.507869] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.508194] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.508237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.508280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.508323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.508366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.508409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.508495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.508539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.508582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.508628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.508676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.508723] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.509059] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.509103] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.510557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.510601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.510645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.511398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.511696] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.512430] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.512666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.513804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.515899] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.516915] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.517085] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.517139] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.517310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.534035] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.534082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.534128] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.534171] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.534214] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.534258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.534302] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.534344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.534388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.534430] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.534554] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.534564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.534605] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.534615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.534659] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.534702] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.534745] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.534788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.534830] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.534875] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.534917] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.534963] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.535006] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.535049] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.535092] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.535158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.535213] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.535256] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.550541] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.568686] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.568799] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.568878] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.569200] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.569244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.569287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.569329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.569372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.569415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.569511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.569556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.569600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.569643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.569692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.569737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.569797] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.569840] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.569893] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.569943] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.569990] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.570036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.570081] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.570125] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.570164] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.570757] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.571191] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.571236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.571281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.571325] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.571367] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.571412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.571504] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.571550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.571596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.571640] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.571682] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.571691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.571734] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.571743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.571787] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.571830] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.571872] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.571915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.571957] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.572002] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.572045] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.572090] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.572134] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.572178] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.572221] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.572286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.572341] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.572384] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.572583] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.572621] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.572911] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.572964] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.573006] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.573063] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.573926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.574257] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.574300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.574344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.574386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.574429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.574516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.574562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.574607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.574651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.574696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.574744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.574788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.574865] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.574908] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.576335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.576382] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.576426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.577325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.577369] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.578190] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.578235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.579427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.581574] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.582639] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.582811] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.582865] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.583508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.599828] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.599876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.599922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.599966] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.600008] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.600052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.600095] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.600138] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.600181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.600223] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.600265] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.600274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.600317] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.600322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.600366] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.600408] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.600919] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.600963] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.601006] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.601052] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.601095] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.601142] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.601186] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.601230] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.601273] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.601342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.601397] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.601767] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.616233] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.634500] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.634612] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.634697] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.635055] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.635108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.635152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.635195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.635237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.635280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.635323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.635365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.635408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.635988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.636040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.636085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.636149] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.636192] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.636246] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.636296] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.636342] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.636388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.636795] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.636841] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.636880] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.637720] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.638407] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.638753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.638800] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.638844] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.638886] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.638930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.638976] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.639019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.639062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.639105] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.639147] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.639155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.639197] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.639203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.639246] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.639288] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.639331] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.639374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.639417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.639882] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.639924] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.639972] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.640016] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.640060] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.640105] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.640171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.640226] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.640269] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.640415] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.640494] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.641014] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.641412] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.641499] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.641805] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.642065] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.642395] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.642502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.642775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.642818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.642861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.642904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.642947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.642989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.643032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.643075] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.643125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.643169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.643244] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.643287] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.644934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.644981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.645025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.646010] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.646058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.647161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.649289] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.650770] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.650975] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.651029] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.651200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.667933] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.667980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.668024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.668068] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.668110] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.668154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.668196] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.668239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.668282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.668324] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.668366] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.668375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.668417] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.668487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.668532] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.668583] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.668628] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.668672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.668717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.668764] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.668809] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.668855] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.668902] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.668947] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.668993] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.669057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.669108] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.669152] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.684387] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.696775] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x10001918, pins 0x00000040 >May 24 03:31:14 BXT-2 kernel: [ 559.696908] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short >May 24 03:31:14 BXT-2 kernel: [ 559.697263] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short >May 24 03:31:14 BXT-2 kernel: [ 559.699002] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:14 BXT-2 kernel: [ 559.702773] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.702886] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.702965] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.703285] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.703329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.703372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.703415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.703519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.703565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.703616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.703661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.703705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.703748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.703795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.703840] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.703912] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.703962] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.704017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.706552] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.706597] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.706643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.706678] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.706724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.706768] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.706805] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.706847] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.706881] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.706926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.706963] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.707005] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.707040] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.707083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.707126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.707168] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.707209] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.707218] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.707260] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.707265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.707308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.707351] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.707393] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.707497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.707542] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.707589] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.707634] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.707680] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.707727] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.707772] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.707815] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.707885] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.707939] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.707982] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.708494] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.708643] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.708681] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.709048] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.709104] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.709146] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.709203] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.709595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.709913] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.709956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.709999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.710042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.710084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.710127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.710169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.710212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.710254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.710297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.710343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.710388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.710506] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.710550] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.712074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.712117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.712161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.712934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.712977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.713902] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.713948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.715033] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.717138] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.718195] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.718392] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.718703] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.718878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.735409] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.735550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.735597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.735641] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.735683] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.735728] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.735772] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.735815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.735858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.735900] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.735942] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.735951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.735994] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.736000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.736043] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.736086] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.736129] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.736172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.736214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.736259] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.736301] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.736346] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.736389] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.736432] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.737485] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.737552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.737607] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.737650] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.751772] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.770128] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.770241] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.770320] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.770649] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.770694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.770738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.770781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.770825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.770868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.770911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.770955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.770998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.771042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.771090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.771135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.771199] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.771242] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.771295] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.771345] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.771391] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.771475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.771520] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.771563] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.771602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.772154] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.772624] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.772669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.772715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.772760] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.772802] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.772847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.772892] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.772935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.772979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.773021] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.773064] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.773073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.773116] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.773122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.773166] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.773209] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.773252] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.773295] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.773338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.773383] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.773426] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.773505] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.773548] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.773591] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.773635] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.773698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.773751] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.773795] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.773943] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.773981] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.774270] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.774324] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.774364] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.774421] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.775052] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.775374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.775418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.775514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.775557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.775601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.775644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.775688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.775731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.775774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.775817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.775864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.775909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.775985] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.776028] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.777554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.777598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.777642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.778388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.778431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.779281] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.779326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.780406] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.782506] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.783581] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.783766] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.783820] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.783991] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.800721] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.800768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.800813] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.800856] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.800898] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.800942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.800985] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.801028] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.801071] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.801113] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.801155] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.801163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.801205] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.801211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.801254] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.801296] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.801339] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.801381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.801424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.801526] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.801570] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.801617] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.801661] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.801706] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.801751] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.801812] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.801861] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.801906] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.817160] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.834864] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.834977] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.835057] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.835379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.835422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.835527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.835571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.835616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.835659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.835703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.835747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.835789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.835834] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.835881] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.835926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.835988] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.836030] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.836084] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.836133] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.836179] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.836225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.836269] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.836313] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.836352] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.836948] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.837360] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.837406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.837491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.837538] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.837582] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.837626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.837672] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.837715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.837758] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.837800] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.837842] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.837851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.837893] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.837899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.837942] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.837985] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.838029] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.838071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.838115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.838160] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.838203] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.838248] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.838292] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.838336] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.838380] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.838488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.838545] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.838590] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.838765] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.838803] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.839100] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.839155] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.839199] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.839257] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.839527] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.839861] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.839906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.839950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.839993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.840038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.840081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.840125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.840169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.840213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.840257] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.840305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.840349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.840424] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.840499] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.841939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.841984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.842029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.842880] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.842925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.843983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.846077] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.847105] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.847273] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.847328] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.847861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.864304] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.864351] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.864397] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.864880] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.864923] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.864969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.865015] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.865058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.865102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.865144] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.865186] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.865195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.865237] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.865243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.865286] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.865329] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.865372] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.865415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.866441] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.866791] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.866834] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.866882] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.866926] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.866969] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.867012] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.867081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.867136] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.867179] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.880663] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.898806] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.898918] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.898998] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.899319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.899363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.899406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.899509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.899553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.899598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.899642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.899686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.899730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.899773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.899821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.899867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.899930] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.899973] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.900027] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.900077] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.900123] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.900169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.900213] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.900256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.900295] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.900893] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.901846] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.901893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.901938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.901982] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.902024] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.902068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.902112] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.902154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.902198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.902240] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.902282] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.902290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.902332] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.902338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.902381] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.902424] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.902519] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.902564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.902609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.902656] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.902699] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.902746] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.902790] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.902835] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.902878] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.902939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.902992] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.903035] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.903190] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.903229] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.903554] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.903611] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.903651] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.903708] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.903967] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.904290] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.904334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.904377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.904420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.904520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.904564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.904607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.904650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.904693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.904736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.904784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.904830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.904905] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.904949] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.906377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.906421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.906516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.907291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.907333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.908103] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.908148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.909202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.911297] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.912290] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.912662] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.912719] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.912890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.929407] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.929504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.929549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.929593] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.929635] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.929679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.929723] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.929765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.929808] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.929850] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.929892] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.929901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.929943] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.929949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.929992] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.930034] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.930077] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.930119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.930161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.930206] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.930247] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.930292] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.930335] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.930378] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.930420] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.931437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.931600] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.931643] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.945911] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.963818] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.963931] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.964012] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.964349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.964394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.964497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.964541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.964585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.964629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.964673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.964717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.964762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.964806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.964854] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.964899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.964964] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.965007] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.965061] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.965110] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.965157] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.965203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.965247] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.965291] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 559.965330] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 559.965915] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.966341] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.966386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.966431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.966519] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.966562] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.966606] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.966650] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.966694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.966737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.966781] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.966822] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.966832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.966874] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.966880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.966924] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.966967] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.967010] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.967053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.967096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.967141] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.967184] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.967229] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.967272] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.967315] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.967359] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.967422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.967496] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.967540] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.967692] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 559.967730] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 559.968021] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 559.968074] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.968114] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 559.968172] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 559.968597] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.968929] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.968975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 559.969020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.969064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.969108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.969154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 559.969199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 559.969241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 559.969285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 559.969330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 559.969377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 559.969422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.969545] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 559.969588] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.971246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.971291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 559.971337] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 559.972238] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 559.972284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 559.973439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 559.975583] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 559.976685] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 559.976856] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 559.976910] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 559.977080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.993863] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 559.993910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 559.993956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 559.994000] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 559.994043] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 559.994087] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.994131] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 559.994174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.994218] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 559.994261] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.994303] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 559.994311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.994353] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 559.994359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.994402] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 559.995523] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 559.995566] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 559.995609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 559.995651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 559.995697] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 559.995739] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 559.995786] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 559.995829] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 559.995872] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.995916] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 559.995985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 559.996039] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 559.996083] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.010251] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.027691] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.027803] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.027883] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.028199] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.028243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.028286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.028329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.028371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.028414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.028913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.028957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.029000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.029043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.029092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.029136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.029199] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.029242] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.029295] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.029344] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.029390] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.029889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.029939] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.029982] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 560.030021] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 560.031187] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.031731] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.031776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.031821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.031865] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.031907] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.031951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.031994] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.032037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.032080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.032122] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.032164] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.032173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.032214] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.032220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.032263] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.032306] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.032349] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.032391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.033106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.033152] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.033194] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.033239] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.033283] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.033326] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.033369] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.033750] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.033807] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.033850] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.033999] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.034036] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.034324] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 560.034378] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.034418] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.034884] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.035120] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.035600] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.035645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.035688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.035731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.035774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.035817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.035859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.035902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.035945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.035988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.036035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.036079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.036153] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.036196] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.038201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.038246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.038290] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 560.039151] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 560.039195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 560.040238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 560.042335] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 560.043343] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.043749] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.043806] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.043977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.060536] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.060582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.060627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.060671] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.060713] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.060756] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.060799] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.060842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.060885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.060928] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.060969] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.060978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.061020] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.061026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.061069] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.061111] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.061154] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.061196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.061238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.061283] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.061325] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.061369] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.061412] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.062329] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.062373] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.062588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.062645] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.062688] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.076989] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.094791] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.094903] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.094982] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.095307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.095351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.095395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.095496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.095539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.095882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.095925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.095969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.096012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.096056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.096105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.096150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.096214] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.096257] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.096311] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.096360] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.096406] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.096503] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.096547] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.096590] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 560.096629] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 560.097194] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.097638] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.097686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.097732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.097778] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.097820] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.097864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.097908] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.097952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.097995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.098037] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.098079] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.098088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.098129] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.098135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.098178] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.098220] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.098263] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.098305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.098347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.098392] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.098479] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.098526] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.098569] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.098613] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.098657] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.098722] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.098777] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.098821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.098969] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.099007] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.099298] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 560.099351] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.099393] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.099517] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.100176] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.100508] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.100552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.100597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.100641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.100685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.100728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.100772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.100815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.100858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.100901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.100948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.100993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.101067] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.101111] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.102961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.103006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.103051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 560.103934] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 560.103979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 560.105259] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 560.107374] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 560.108443] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.108681] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.108736] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.108907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.125660] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.125708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.125752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.125796] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.125839] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.125882] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.125925] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.125968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.126011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.126053] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.126095] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.126104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.126145] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.126151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.126194] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.126237] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.126279] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.126321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.126363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.126408] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.127240] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.127287] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.127330] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.127374] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.127418] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.127732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.127788] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.127831] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.142063] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.159738] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.159851] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.159931] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.160252] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.160296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.160340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.160383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.160426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.160900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.160944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.160987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.161030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.161073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.161124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.161168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.161234] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.161276] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.161330] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.161380] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.161426] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.162056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.162105] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.162148] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 560.162187] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 560.163358] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.163919] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.163965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.164011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.164054] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.164096] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.164141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.164184] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.164227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.164270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.164312] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.164354] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.164363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.164405] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.164963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.165021] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.165065] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.165107] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.165150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.165192] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.165238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.165280] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.165326] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.165369] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.165412] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.165976] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.166045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.166100] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.166143] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.166301] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.166339] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.166951] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 560.167268] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.167309] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.167366] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.167940] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.168275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.168319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.168362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.168405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.168762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.168806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.168849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.168891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.168934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.168977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.169026] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.169071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.169146] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.169189] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.171121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.171167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.171211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 560.172239] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 560.172286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 560.174924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 560.176485] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 560.177513] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.177691] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.177745] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.177917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.194643] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.194690] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.194735] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.194778] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.194820] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.194864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.194907] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.194950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.194993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.195035] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.195076] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.195085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.195127] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.195133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.195176] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.195218] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.195261] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.195303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.195345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.195389] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.196403] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.196489] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.196532] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.196582] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.196627] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.196697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.196752] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.196796] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.211133] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.228702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.228814] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.228894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.229222] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.229266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.229309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.229352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.229395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.229472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.229600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.229644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.229688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.229731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.229778] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.229824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.229885] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.229927] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.229981] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.230031] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.230077] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.230122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.230166] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.230210] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 560.230249] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 560.230856] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.231792] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.231837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.231882] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.231925] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.231967] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.232011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.232054] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.232096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.232139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.232181] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.232223] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.232232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.232273] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.232279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.232322] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.232364] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.232407] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.232511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.232556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.232604] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.232648] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.232693] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.232739] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.232783] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.232826] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.232887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.232940] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.232983] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.233126] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.233164] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.233480] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 560.233537] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.233579] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.233636] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.233944] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.234270] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.234314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.234356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.234399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.234484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.234529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.234575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.234620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.234663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.234706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.234753] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.234798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.234872] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.234916] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.236350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.236393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.236475] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 560.237230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.237272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.238048] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 560.238095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 560.239143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 560.241234] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 560.242201] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.242370] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.242425] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.242820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.259338] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.259384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.259430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.259749] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.259791] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.259836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.259880] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.259923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.259966] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.260008] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.260050] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.260059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.260101] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.260106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.260149] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.260192] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.260234] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.260277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.260319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.260364] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.260406] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.261102] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.261146] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.261189] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.261231] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.261297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.261349] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.261392] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.275769] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.293832] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.293946] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.294027] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.294359] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.294405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.294531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.294574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.294619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.294663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.294706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.294749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.294792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.294836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.294885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.294930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.294995] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.295038] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.295092] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.295142] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.295187] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.295234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.295278] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.295321] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:14 BXT-2 kernel: [ 560.295360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:14 BXT-2 kernel: [ 560.295963] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.296914] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.296960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.297006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.297050] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.297093] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.297138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.297183] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.297226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.297271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.297319] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.297369] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.297379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.297425] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.297522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.297576] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.297619] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.297663] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.297710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.297760] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.297813] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.297862] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.297918] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.297969] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.298020] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.298070] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.298174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.298248] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.298299] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.298705] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:14 BXT-2 kernel: [ 560.298746] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:14 BXT-2 kernel: [ 560.299038] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:14 BXT-2 kernel: [ 560.299094] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.299135] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:14 BXT-2 kernel: [ 560.299193] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:14 BXT-2 kernel: [ 560.300505] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.300828] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.300873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:14 BXT-2 kernel: [ 560.300917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.300960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.301004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.301047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:14 BXT-2 kernel: [ 560.301091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:14 BXT-2 kernel: [ 560.301134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:14 BXT-2 kernel: [ 560.301178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:14 BXT-2 kernel: [ 560.301221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:14 BXT-2 kernel: [ 560.301268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:14 BXT-2 kernel: [ 560.301313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.301388] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:14 BXT-2 kernel: [ 560.301431] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.302917] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.302961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:14 BXT-2 kernel: [ 560.303006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:14 BXT-2 kernel: [ 560.303828] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:14 BXT-2 kernel: [ 560.303873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:14 BXT-2 kernel: [ 560.304909] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:14 BXT-2 kernel: [ 560.306482] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:14 BXT-2 kernel: [ 560.307471] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.307649] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:14 BXT-2 kernel: [ 560.307703] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:14 BXT-2 kernel: [ 560.307873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.324637] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:14 BXT-2 kernel: [ 560.324684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:14 BXT-2 kernel: [ 560.324729] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:14 BXT-2 kernel: [ 560.324773] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:14 BXT-2 kernel: [ 560.324815] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:14 BXT-2 kernel: [ 560.324859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.324903] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:14 BXT-2 kernel: [ 560.324946] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.324989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:14 BXT-2 kernel: [ 560.325031] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.325073] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:14 BXT-2 kernel: [ 560.325082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.325124] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:14 BXT-2 kernel: [ 560.325130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.325173] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:14 BXT-2 kernel: [ 560.325215] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:14 BXT-2 kernel: [ 560.325258] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:14 BXT-2 kernel: [ 560.325300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:14 BXT-2 kernel: [ 560.325343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:14 BXT-2 kernel: [ 560.325387] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:14 BXT-2 kernel: [ 560.325429] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:14 BXT-2 kernel: [ 560.325546] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:14 BXT-2 kernel: [ 560.325592] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:14 BXT-2 kernel: [ 560.325637] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.325682] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:14 BXT-2 kernel: [ 560.325749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:14 BXT-2 kernel: [ 560.325803] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:14 BXT-2 kernel: [ 560.325849] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:14 BXT-2 kernel: [ 560.341043] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.358712] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.358824] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.358904] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.359225] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.359269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.359312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.359355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.359398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.359503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.359550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.359594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.359640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.359685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.359731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.359779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.359840] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.359883] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.359936] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.359986] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.360031] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.360077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.360122] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.360166] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.360204] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.360787] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.361205] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.361250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.361295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.361338] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.361381] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.361424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.361508] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.361553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.361599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.361642] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.361687] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.361697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.361739] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.361747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.361791] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.361834] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.361878] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.361921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.361963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.362009] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.362052] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.362097] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.362140] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.362184] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.362227] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.362290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.362344] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.362387] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.362561] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.362598] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.362888] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.362941] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.362983] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.363039] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.363497] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.363818] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.363862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.363905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.363948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.363991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.364033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.364076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.364118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.364161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.364204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.364250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.364295] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.364368] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.364411] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.366128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.366175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.366219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.367211] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.367258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.368758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.370866] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.371893] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.372072] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.372126] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.372296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.389055] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.389102] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.389148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.389191] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.389234] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.389278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.389322] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.389365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.389408] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.389938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.389980] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.389989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.390031] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.390037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.390080] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.390123] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.390166] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.390210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.390252] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.390297] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.390339] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.390385] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.390428] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.391051] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.391095] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.391160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.391217] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.391259] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.405588] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.423694] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.423806] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.423885] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.424209] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.424253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.424296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.424339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.424381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.424424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.424506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.424553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.424598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.424643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.424690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.424736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.424796] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.424841] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.424895] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.424945] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.424990] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.425036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.425080] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.425123] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.425162] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.425738] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.426167] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.426213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.426258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.426302] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.426344] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.426389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.426433] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.426548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.426592] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.426634] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.426677] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.426686] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.426729] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.426735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.426779] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.426822] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.426865] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.426908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.426951] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.426996] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.427039] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.427084] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.427128] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.427171] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.427215] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.427282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.427336] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.427379] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.427551] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.427590] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.427880] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.427933] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.427973] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.428031] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.428427] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.428859] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.428905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.428948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.428991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.429033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.429076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.429119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.429161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.429204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.429247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.429294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.429338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.429413] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.429506] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.431052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.431096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.431140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.431952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.431997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.433195] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.433242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.434600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.436707] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.437725] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.437921] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.437975] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.438146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.454882] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.454929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.454973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.455017] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.455059] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.455103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.455146] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.455189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.455232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.455274] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.455316] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.455324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.455366] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.455372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.455415] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.455505] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.455550] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.455595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.455639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.455686] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.455730] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.455777] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.455822] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.455865] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.455907] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.455972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.456022] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.456065] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.471380] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.489698] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.489813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.489894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.490218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.490262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.490305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.490348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.490391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.490493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.490540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.490585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.490630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.490675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.490720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.490768] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.490829] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.490872] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.490925] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.490975] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.491022] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.491068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.491114] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.491158] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.491200] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.491806] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.492767] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.492814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.492860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.492903] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.492945] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.492990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.493033] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.493075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.493118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.493160] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.493202] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.493211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.493252] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.493258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.493301] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.493344] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.493386] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.493428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.493507] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.493554] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.493598] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.493645] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.493691] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.493736] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.493781] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.493842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.493896] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.493939] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.494091] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.494129] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.494428] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.494536] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.494578] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.494637] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.494897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.495223] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.495269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.495313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.495356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.495399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.495495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.495540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.495582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.495627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.495671] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.495719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.495764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.495838] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.495883] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.497314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.497360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.497406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.498232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.498275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.499132] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.499177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.500249] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.502353] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.503338] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.503592] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.503649] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.503821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.520444] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.520516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.520561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.520605] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.520647] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.520691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.520734] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.520776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.520819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.520861] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.520903] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.520912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.520954] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.520960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.521002] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.521045] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.521087] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.521130] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.521172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.521216] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.521258] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.521302] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.521345] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.521388] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.521431] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.521532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.521582] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.521628] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.536912] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.554807] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.554919] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.554998] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.555318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.555362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.555405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.555493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.555538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.555583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.555627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.555669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.555715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.555759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.555805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.555851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.555914] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.555956] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.556010] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.556060] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.556107] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.556153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.556197] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.556240] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.556279] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.556859] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.557287] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.557334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.557379] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.557423] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.557533] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.557580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.557624] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.557668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.557711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.557754] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.557796] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.557806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.557849] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.557855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.557899] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.557942] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.557986] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.558029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.558072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.558117] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.558160] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.558205] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.558249] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.558292] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.558336] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.558402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.558481] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.558524] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.559868] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.559910] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.560201] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.560258] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.560298] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.560356] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.561002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.561334] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.561378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.561422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.561500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.561543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.561586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.561629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.561672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.561715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.561758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.561808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.561852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.561929] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.561972] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.564104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.564150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.564195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.565026] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.565073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.566148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.568273] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.569290] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.569544] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.569602] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.569773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.586389] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.586475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.586521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.586565] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.586607] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.586651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.586694] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.586736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.586779] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.586821] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.586863] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.586872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.586913] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.586919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.586962] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.587005] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.587047] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.587089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.587131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.587176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.587218] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.587262] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.587305] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.587348] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.587390] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.587554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.587605] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.587652] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.602867] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.620722] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.620835] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.620915] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.621240] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.621284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.621327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.621369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.621412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.621512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.621560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.621608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.621652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.621696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.621748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.621793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.621857] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.621900] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.621954] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.622004] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.622050] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.622096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.622140] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.622184] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.622223] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.622817] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.623249] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.623295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.623340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.623384] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.623427] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.623519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.623566] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.623612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.623658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.623702] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.623744] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.623753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.623795] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.623801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.623844] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.623887] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.623930] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.623972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.624014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.624059] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.624101] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.624146] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.624189] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.624231] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.624274] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.624342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.624399] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.624480] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.624642] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.624682] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.624974] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.625029] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.625070] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.625127] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.626598] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.626925] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.626969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.627013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.627056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.627099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.627143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.627185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.627228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.627271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.627314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.627361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.627406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.627686] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.627730] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.629528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.629574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.629618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.630384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.630427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.631200] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.631244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.632329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.634420] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.635541] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.635706] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.635761] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.635931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.652712] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.652758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.652803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.652847] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.652889] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.652933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.652977] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.653019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.653062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.653105] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.653147] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.653155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.653197] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.653203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.653246] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.653289] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.653332] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.653374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.653417] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.653689] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.653738] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.653784] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.653829] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.653873] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.653916] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.653980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.654033] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.654077] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.669157] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.687714] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.687827] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.687907] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.688225] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.688269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.688312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.688354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.688397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.688482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.688530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.688578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.688624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.688669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.688719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.688764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.688833] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.688875] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.688929] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.688979] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.689025] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.689072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.689118] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.689161] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.689200] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.689779] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.690215] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.690261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.690308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.690352] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.690394] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.690503] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.690550] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.690595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.690641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.690686] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.690728] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.690737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.690781] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.690787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.690830] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.690873] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.690916] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.690959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.691002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.691048] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.691090] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.691136] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.691180] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.691223] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.691267] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.691332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.691388] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.691432] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.691624] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.691663] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.691957] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.692012] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.692053] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.692110] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.692411] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.692779] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.692824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.692868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.692911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.692954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.692997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.693041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.693084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.693127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.693171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.693218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.693264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.693339] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.693382] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.694889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.694935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.694981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.695764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.695807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.696673] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.696718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.698040] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.700147] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.701185] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.701362] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.701417] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.701871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.718341] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.718388] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.718654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.718699] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.718742] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.718787] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.718832] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.718875] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.718918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.718961] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.719002] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.719013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.719054] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.719060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.719103] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.719146] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.719189] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.719231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.719273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.719318] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.719361] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.719405] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.720251] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.720295] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.720338] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.720405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.720696] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.720739] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.734761] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.753286] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.753400] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.753561] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.753892] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.753936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.753979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.754022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.754065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.754108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.754150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.754193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.754236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.754279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.754329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.754374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.754495] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.754542] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.754598] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.754648] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.754694] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.754741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.754786] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.754829] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.754868] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.755416] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.755872] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.755919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.755965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.756009] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.756051] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.756096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.756139] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.756182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.756226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.756268] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.756310] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.756319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.756360] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.756366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.756409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.756504] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.756552] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.756598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.756642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.756689] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.756733] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.756781] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.756825] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.756868] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.756911] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.756977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.757031] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.757075] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.757819] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.757859] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.758150] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.758205] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.758245] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.758302] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.759067] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.759397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.759509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.759751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.759794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.759838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.759883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.759932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.759983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.760033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.760085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.760151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.760205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.760299] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.760351] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.762961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.763007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.763053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.764074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.764120] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.765019] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.765065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.766108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.767529] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.768562] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.768725] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.768780] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.768949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.785717] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.785764] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.785809] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.785853] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.785895] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.785939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.785981] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.786024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.786067] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.786109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.786151] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.786160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.786202] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.786207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.786250] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.786293] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.786336] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.786378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.786420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.787227] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.787270] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.787317] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.787360] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.787403] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.787695] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.787768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.787822] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.787865] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.802177] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.819769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.819885] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.819966] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.820298] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.820342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.820385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.820428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.820846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.820890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.820932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.820975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.821018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.821061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.821112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.821157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.821220] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.821263] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.821317] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.821367] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.821413] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.821798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.821847] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.821890] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.821929] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.823101] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.823734] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.823780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.823826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.824025] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.824069] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.824114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.824161] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.824204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.824248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.824291] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.824333] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.824343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.824385] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.824391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.824859] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.824904] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.824947] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.824990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.825033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.825078] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.825121] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.825167] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.825211] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.825254] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.825298] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.825363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.825418] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.825744] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.825903] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.825940] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.826230] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.826284] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.826327] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.826385] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.826984] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.827309] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.827356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.827399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.827489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.827532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.827580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.827627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.827674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.827718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.827762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.828094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.828139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.828214] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.828258] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.829873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.829918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.829964] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.830871] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.830916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.832054] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.834150] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.835154] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.835332] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.835386] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.835796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.852289] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.852336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.852380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.852424] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.852782] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.852827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.852872] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.852919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.852962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.853004] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.853046] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.853058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.853099] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.853107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.853150] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.853194] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.853237] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.853280] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.853322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.853366] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.853408] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.854109] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.854152] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.854195] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.854238] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.854305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.854359] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.854402] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.869586] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.885713] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.885826] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.885906] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.886233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.886278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.886321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.886364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.886407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.886900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.886944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.886986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.887029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.887072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.887121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.887166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.887231] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.887273] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.887327] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.887376] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.887422] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.887971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.888019] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.888062] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.888100] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.889269] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.889843] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.889889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.889935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.889979] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.890021] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.890064] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.890108] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.890150] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.890193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.890236] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.890277] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.890286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.890328] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.890334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.890377] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.890419] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.891092] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.891136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.891178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.891225] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.891267] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.891318] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.891361] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.891404] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.891772] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.891840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.891894] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.891937] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.892089] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.892126] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.892416] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.893068] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.893109] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.893166] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.893417] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.893988] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.894032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.894076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.894119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.894161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.894204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.894247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.894290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.894332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.894375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.894422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.894906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.894982] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.895025] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.896480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.896525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.896570] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.897342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.897384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.898408] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.898497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.899591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.901691] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.902730] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.902904] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.902959] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.903130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.919869] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.919916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.919961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.920005] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.920047] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.920091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.920135] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.920178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.920221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.920264] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.920306] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.920315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.920357] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.920362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.920406] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.921159] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.921203] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.921246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.921288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.921334] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.921376] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.921422] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.921854] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.921899] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.921942] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.922009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.922064] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.922107] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.936311] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.954753] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.954866] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.954947] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.955277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.955321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.955365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.955407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.955502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.955545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.955588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.955630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.955673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.955716] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.955764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.955809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.955874] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.955917] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.955970] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.956019] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.956064] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.956110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.956153] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.956196] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 560.956235] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 560.956849] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.959327] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.959374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.959420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.959513] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.959558] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.959835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.959880] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.959924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.959968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.960011] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.960053] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.960062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.960104] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.960110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.960154] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.960197] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.960241] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.960284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.960327] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.960373] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.960416] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.960528] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.960572] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.960615] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.960659] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.960723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.960778] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.960821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.960966] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 560.961004] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 560.961294] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 560.961347] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.961388] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 560.961468] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 560.961934] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.962263] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.962306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 560.962350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.962393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.962503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.962547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 560.962590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 560.962634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 560.962677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 560.962721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 560.962769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 560.962814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.962889] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 560.962933] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.964451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.964549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.964594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 560.965344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.965386] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 560.966159] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 560.966205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 560.967294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 560.969399] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 560.970448] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 560.970643] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 560.970697] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 560.970867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.987728] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 560.987776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 560.987822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 560.987867] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 560.987909] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 560.987953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.987998] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 560.988041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.988084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 560.988126] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.988168] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 560.988177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.988219] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 560.988225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.988268] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 560.988311] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 560.988353] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 560.988396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 560.989203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 560.989249] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 560.989291] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 560.989338] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 560.989381] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 560.989425] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.989827] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 560.989899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 560.989953] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 560.989996] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.004100] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.021689] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.021801] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.021880] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.022203] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.022247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.022290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.022333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.022375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.022418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.022527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.022570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.022615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.022659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.022705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.022749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.022810] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.022852] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.022906] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.022957] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.023002] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.023048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.023093] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.023137] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 561.023175] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 561.023754] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.024168] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.024214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.024259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.024303] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.024346] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.024390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.024514] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.024558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.024601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.024644] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.024687] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.024697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.024738] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.024745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.024789] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.024832] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.024876] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.024918] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.024961] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.025006] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.025049] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.025094] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.025138] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.025181] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.025224] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.025290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.025344] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.025388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.025573] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.025612] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.025903] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 561.025956] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.025996] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.026054] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.026858] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.027190] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.027234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.027277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.027320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.027363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.027406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.027492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.027537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.027579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.027622] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.027670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.027715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.027790] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.027833] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.029529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.029574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.029618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 561.030387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.030430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.031534] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 561.031580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 561.032752] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 561.034856] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 561.035907] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.036101] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.036156] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.036331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.053077] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.053125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.053170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.053214] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.053256] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.053300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.053344] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.053387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.053430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.053894] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.053937] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.053947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.053989] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.053996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.054039] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.054082] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.054126] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.054168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.054211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.054257] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.054300] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.054346] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.054390] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.054777] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.054822] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.054888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.054943] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.054985] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.069655] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.087732] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.087844] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.087924] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.088251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.088295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.088338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.088380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.088423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.088512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.088558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.088603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.088649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.088693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.088739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.088787] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.088851] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.088893] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.088947] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.088996] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.089042] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.089088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.089132] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.089175] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 561.089214] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 561.089811] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.090240] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.090286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.090331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.090375] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.090417] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.090506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.090550] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.090594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.090640] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.090684] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.090727] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.090739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.090783] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.090789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.090832] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.090875] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.090918] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.090961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.091003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.091049] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.091091] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.091137] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.091180] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.091224] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.091267] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.091331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.091385] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.091429] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.091999] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.092037] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.092327] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 561.092383] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.092425] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.092521] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.093112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.093435] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.093564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.093779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.093822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.093865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.093908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.093951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.093994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.094037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.094080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.094130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.094175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.094250] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.094293] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.095998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.096045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.096090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 561.096958] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 561.097006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 561.098195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 561.100304] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 561.101282] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.101502] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.101557] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.101728] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.118404] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.118511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.118556] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.118600] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.118642] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.118686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.118730] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.118773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.118816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.118859] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.118901] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.118909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.118951] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.118957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.119000] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.119043] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.119085] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.119128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.119170] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.119215] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.119257] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.119301] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.119344] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.119387] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.119430] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.119526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.119578] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.119624] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.134844] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.153181] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.153298] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.153380] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.153725] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.153771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.153814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.153857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.153900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.153943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.153986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.154028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.154071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.154114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.154162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.154206] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.154270] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.154314] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.154367] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.154417] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.154497] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.154543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.154588] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.154631] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 561.154670] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 561.155230] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.155692] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.155739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.155784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.155828] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.155870] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.155914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.155957] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.156000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.156043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.156085] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.156126] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.156136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.156178] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.156184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.156227] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.156270] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.156313] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.156355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.156397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.156475] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.156517] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.156562] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.156605] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.156648] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.156691] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.156754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.156809] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.156852] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.159595] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.159636] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.159926] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 561.159981] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.160021] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.160079] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.160416] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.161444] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.161882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.161927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.161970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.162013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.162055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.162098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.162141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.162184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.162227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.162277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.162322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.162397] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.163300] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.165132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.165178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.165222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 561.166539] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 561.166586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 561.167803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 561.169902] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 561.170934] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.171121] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.171176] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.171346] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.188087] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.188134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.188179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.188222] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.188264] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.188310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.188354] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.188398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.188502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.188544] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.188588] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.188597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.188639] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.188649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.188692] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.188740] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.188784] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.188826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.188869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.188914] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.188956] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.189002] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.189045] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.189088] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.189132] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.189198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.189251] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.189295] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.204621] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.222685] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.222797] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.222878] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.223197] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.223241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.223284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.223327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.223369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.223412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.223525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.223568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.223613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.223657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.223703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.223748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.223810] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.223852] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.223906] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.223957] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.224003] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.224049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.224093] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.224136] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 561.224175] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 561.224786] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.225784] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.225830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.225876] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.225919] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.225961] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.226006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.226049] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.226092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.226135] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.226177] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.226219] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.226228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.226270] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.226275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.226318] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.226361] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.226404] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.226486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.226530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.226578] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.226622] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.226670] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.226714] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.226759] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.226804] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.226866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.226918] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.226964] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.227114] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.227153] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.227488] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 561.227545] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.227585] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.227642] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.228186] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.228741] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.228788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.228833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.228876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.228919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.228963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.229006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.229050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.229093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.229136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.229185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.229230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.229306] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.229350] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.231111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.231156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.231201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 561.232135] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 561.232180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 561.233238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 561.234507] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 561.235487] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.235675] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.235730] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.235900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.252666] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.252712] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.252757] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.252801] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.252843] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.252887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.252930] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.252972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.253015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.253057] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.253099] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.253107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.253149] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.253155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.253198] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.253240] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.253283] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.253325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.253367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.253412] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.254043] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.254091] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.254135] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.254179] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.254222] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.254292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.254347] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.254390] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.269107] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.286818] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.286931] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.287011] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.287330] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.287374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.287417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.287513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.287558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.287601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.287646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.287689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.287732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.287776] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.287824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.287868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.287931] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.287974] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.288027] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.288078] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.288125] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.288171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.288215] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.288258] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:15 BXT-2 kernel: [ 561.288299] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:15 BXT-2 kernel: [ 561.288881] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.289305] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.289350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.289396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.289485] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.289529] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.289573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.289620] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.289663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.289706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.289750] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.289792] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.289802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.289843] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.289850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.289894] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.289937] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.289980] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.290023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.290066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.290111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.290153] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.290198] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.290242] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.290285] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.290329] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.290394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.290466] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.290509] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.290661] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:15 BXT-2 kernel: [ 561.290699] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:15 BXT-2 kernel: [ 561.290989] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:15 BXT-2 kernel: [ 561.291042] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.291084] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:15 BXT-2 kernel: [ 561.291141] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:15 BXT-2 kernel: [ 561.291637] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.291963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.292007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:15 BXT-2 kernel: [ 561.292050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.292092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.292135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.292178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:15 BXT-2 kernel: [ 561.292221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:15 BXT-2 kernel: [ 561.292263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:15 BXT-2 kernel: [ 561.292306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:15 BXT-2 kernel: [ 561.292348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:15 BXT-2 kernel: [ 561.292395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:15 BXT-2 kernel: [ 561.292508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.292584] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:15 BXT-2 kernel: [ 561.292627] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.294576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.294622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.294666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:15 BXT-2 kernel: [ 561.295431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.295528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:15 BXT-2 kernel: [ 561.296378] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:15 BXT-2 kernel: [ 561.296426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:15 BXT-2 kernel: [ 561.297575] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:15 BXT-2 kernel: [ 561.299693] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:15 BXT-2 kernel: [ 561.300721] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.300892] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:15 BXT-2 kernel: [ 561.300947] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:15 BXT-2 kernel: [ 561.301120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.317924] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:15 BXT-2 kernel: [ 561.317971] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:15 BXT-2 kernel: [ 561.318017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:15 BXT-2 kernel: [ 561.318061] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:15 BXT-2 kernel: [ 561.318103] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:15 BXT-2 kernel: [ 561.318147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.318192] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:15 BXT-2 kernel: [ 561.318234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.318277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:15 BXT-2 kernel: [ 561.318320] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.318362] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:15 BXT-2 kernel: [ 561.318371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.318413] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:15 BXT-2 kernel: [ 561.318476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.318521] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:15 BXT-2 kernel: [ 561.318563] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:15 BXT-2 kernel: [ 561.318606] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:15 BXT-2 kernel: [ 561.318648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:15 BXT-2 kernel: [ 561.318690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:15 BXT-2 kernel: [ 561.318736] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:15 BXT-2 kernel: [ 561.318778] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:15 BXT-2 kernel: [ 561.318823] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:15 BXT-2 kernel: [ 561.318868] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:15 BXT-2 kernel: [ 561.318911] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.318956] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:15 BXT-2 kernel: [ 561.319022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:15 BXT-2 kernel: [ 561.319078] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:15 BXT-2 kernel: [ 561.319121] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:15 BXT-2 kernel: [ 561.334293] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.352702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.352814] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.352894] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.353214] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.353258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.353302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.353344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.353387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.353430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.353515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.353560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.353605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.353650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.353697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.353742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.353805] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.353848] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.353901] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.353950] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.353996] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.354042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.354087] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.354130] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.354169] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.354766] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.355204] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.355250] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.355295] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.355339] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.355381] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.355426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.355537] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.355580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.355623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.355665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.355707] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.355717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.355759] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.355767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.355810] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.355852] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.355895] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.355939] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.355981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.356027] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.356069] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.356115] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.356158] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.356202] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.356245] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.356312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.356367] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.356411] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.356628] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.356666] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.356957] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.357010] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.357050] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.357108] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.357941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.358271] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.358315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.358358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.358401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.358500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.358545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.358588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.358631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.358674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.358718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.358765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.358810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.358885] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.358929] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.360625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.360670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.360714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.361500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.361543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.362360] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.362404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.363508] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.365607] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.366637] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.366819] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.366873] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.367042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.383772] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.383819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.383865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.383908] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.383950] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.383994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.384037] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.384079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.384122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.384164] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.384206] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.384215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.384256] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.384262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.384305] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.384347] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.384390] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.384432] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.384513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.384562] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.384606] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.384652] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.384697] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.384742] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.384787] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.384848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.384896] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.384942] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.400229] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.418742] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.418855] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.418934] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.419251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.419295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.419338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.419381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.419424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.419524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.419568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.419613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.419656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.419699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.419745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.419790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.419852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.419894] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.419947] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.419997] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.420043] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.420091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.420135] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.420179] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.420218] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.420811] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.421234] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.421280] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.421328] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.421372] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.421414] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.421506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.421551] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.421595] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.421638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.421681] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.421723] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.421733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.421774] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.421781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.421825] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.421868] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.421911] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.421954] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.421996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.422042] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.422084] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.422129] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.422173] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.422216] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.422260] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.422326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.422381] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.422425] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.422625] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.422663] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.422953] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.423007] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.423050] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.423107] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.423566] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.423899] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.423943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.423986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.424029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.424072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.424114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.424157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.424199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.424242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.424286] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.424333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.424378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.424494] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.424538] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.426174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.426219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.426263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.427152] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.427197] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.428427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.430561] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.431564] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.431748] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.431802] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.431971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.448746] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.448793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.448839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.448882] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.448925] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.448969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.449013] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.449056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.449099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.449141] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.449183] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.449192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.449234] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.449240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.449283] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.449326] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.449369] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.449411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.450253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.450299] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.450341] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.450389] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.450432] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.450798] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.450842] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.450912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.450967] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.451010] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.465154] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.482838] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.482950] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.483030] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.483354] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.483398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.483496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.483541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.483584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.483627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.483671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.483714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.483757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.483801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.483848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.483893] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.483961] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.484005] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.484059] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.484109] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.484155] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.484201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.484246] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.484289] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.484329] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.485518] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.485944] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.485988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.486033] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.486077] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.486119] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.486163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.486206] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.486249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.486292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.486334] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.486376] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.486385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.486426] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.486483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.486528] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.486573] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.486615] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.486658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.486701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.486746] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.486788] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.486834] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.486877] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.486921] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.486964] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.487026] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.487080] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.487123] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.487264] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.487302] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.487616] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.487670] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.487710] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.487767] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.488706] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.489035] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.489079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.489123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.489165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.489208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.489251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.489294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.489336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.489379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.489422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.489507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.489555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.489630] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.489674] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.491728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.491774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.491819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.492749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.492793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.493695] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.493740] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.494904] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.496495] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.497507] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.497690] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.497744] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.497913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.514656] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.514702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.514747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.514791] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.514833] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.514876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.514921] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.514963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.515006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.515049] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.515090] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.515099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.515141] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.515146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.515190] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.515232] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.515275] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.515317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.515359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.515404] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.516248] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.516296] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.516340] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.516383] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.516426] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.516757] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.516814] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.516857] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.531141] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.548765] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.548877] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.548957] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.549860] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.549910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.549954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.549997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.550040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.550083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.550126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.550169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.550212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.550256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.550304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.550349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.550418] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.551351] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.551405] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.551917] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.551966] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.552013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.552060] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.552104] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.552142] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.553539] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.553972] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.554016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.554062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.554106] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.554148] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.554192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.554236] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.554279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.554322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.554364] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.554406] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.555215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.555273] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.555279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.555323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.555366] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.555409] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.556006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.556049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.556095] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.556137] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.556185] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.556228] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.556271] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.556315] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.556382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.557185] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.557232] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.557421] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.557502] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.557801] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.557858] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.557900] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.557957] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.558226] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.558555] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.558600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.558643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.558685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.558728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.558771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.558813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.558856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.558898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.558941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.558988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.559032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.559106] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.559149] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.560845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.560890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.560934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.561729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.561772] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.562599] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.562646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.563748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.565475] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.566868] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.567050] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.567106] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.567276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.584029] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.584077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.584122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.584166] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.584208] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.584252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.584295] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.584338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.584381] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.584423] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.584525] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.584537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.584579] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.584585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.584628] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.584671] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.584714] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.584758] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.584801] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.584846] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.584889] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.584934] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.584978] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.585021] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.585065] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.585128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.585179] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.585222] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.600548] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.619064] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.619176] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.619255] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.619869] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.619916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.619959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.620002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.620045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.620089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.620132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.620175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.620218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.620261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.620308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.620353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.620417] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.620528] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.620769] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.620821] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.620870] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.620918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.620964] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.621008] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.621048] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.621665] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.622753] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.622799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.622844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.622888] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.622931] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.622975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.623019] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.623062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.623105] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.623147] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.623189] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.623198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.623240] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.623246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.623289] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.623332] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.623375] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.623417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.623490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.623540] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.623585] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.623632] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.623678] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.623723] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.623770] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.623837] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.624260] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.624305] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.624528] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.624567] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.624858] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.624912] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.624955] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.625012] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.626532] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.626857] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.626902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.626945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.626988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.627031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.627074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.627117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.627160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.627203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.627246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.627293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.627338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.627412] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.627490] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.628916] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.628961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.629005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.629772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.629816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.630541] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.630585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.631626] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.633718] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.634734] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.634914] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.634969] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.635139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.651863] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.651910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.651955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.651999] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.652042] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.652086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.652129] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.652172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.652215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.652258] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.652300] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.652309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.652350] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.652356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.652400] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.652485] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.652528] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.652575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.652621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.652669] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.652715] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.652763] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.652809] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.652855] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.652901] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.652967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.653017] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.653063] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.668343] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.686857] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.686968] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.687047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.687371] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.687414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.687492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.687542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.687587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.687632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.687677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.687721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.687766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.687810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.687858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.687903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.687971] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.688015] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.688070] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.688120] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.688166] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.688212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.688257] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.688301] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.688340] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.688923] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.689345] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.689390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.689470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.689516] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.689560] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.689604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.689648] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.689692] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.689735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.689779] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.689821] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.689831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.689873] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.689879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.689923] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.689966] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.690010] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.690053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.690096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.690141] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.690184] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.690230] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.690274] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.690317] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.690360] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.690424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.690532] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.690578] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.690733] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.690771] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.691061] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.691115] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.691157] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.691215] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.691556] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.691879] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.691923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.691967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.692009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.692052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.692095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.692138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.692181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.692223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.692266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.692312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.692357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.692430] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.692508] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.693920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.693963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.694007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.694777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.694820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.695545] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.695590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.696630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.698721] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.699749] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.699918] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.699972] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.700142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.716914] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.716961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.717006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.717049] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.717092] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.717136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.717179] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.717222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.717265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.717307] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.717349] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.717358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.717400] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.717469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.717520] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.717564] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.717611] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.717656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.717701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.717749] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.717793] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.717839] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.717885] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.717929] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.717972] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.718035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.718086] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.718129] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.733358] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.751874] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.751987] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.752067] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.752385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.752429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.752537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.752584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.752631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.752676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.752722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.752765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.752810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.752855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.752902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.752947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.753016] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.753058] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.753112] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.753162] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.753209] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.753254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.753299] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.753343] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.753382] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.753967] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.754392] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.754472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.754520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.754565] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.754607] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.754651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.754695] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.754737] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.754781] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.754826] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.754868] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.754877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.754919] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.754926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.754970] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.755014] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.755057] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.755101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.755143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.755189] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.755232] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.755277] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.755321] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.755365] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.755409] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.755500] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.755555] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.755599] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.755751] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.755789] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.756080] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.756134] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.756176] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.756234] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.756517] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.756836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.756881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.756924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.756967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.757010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.757053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.757096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.757139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.757182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.757225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.757272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.757317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.757389] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.757433] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.758887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.758931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.758976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.759748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.759791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.760509] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.760553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.761584] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.763675] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.764686] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.764871] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.764925] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.765095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.781863] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.781910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.781956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.782000] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.782042] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.782086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.782129] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.782172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.782215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.782257] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.782299] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.782308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.782350] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.782356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.782399] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.782551] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.782595] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.782640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.782684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.782729] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.782771] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.782816] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.782860] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.782903] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.782946] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.783013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.783065] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.783109] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.798316] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.816830] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.816943] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.817022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.817344] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.817388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.817432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.817535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.817582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.817625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.817668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.817712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.817756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.817800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.817847] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.817893] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.817962] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.818005] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.818060] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.818110] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.818158] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.818206] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.818250] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.818294] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.818333] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.818916] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.819337] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.819382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.819427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.819505] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.819551] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.819598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.819644] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.819688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.819734] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.819777] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.819819] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.819829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.819871] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.819878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.819922] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.819965] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.820008] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.820052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.820095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.820140] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.820183] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.820228] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.820272] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.820316] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.820360] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.820421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.820504] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.820549] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.820703] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.820741] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.821031] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.821085] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.821127] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.821185] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.821511] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.821838] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.821882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.821925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.821968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.822013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.822056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.822099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.822142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.822184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.822227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.822274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.822318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.822392] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.822467] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.823885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.823929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.823974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.824750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.824793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.825513] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.825558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.826593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.828682] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.829732] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.829916] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.829972] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.830143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.846887] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.846934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.846979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.847023] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.847066] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.847110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.847153] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.847196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.847239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.847282] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.847324] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.847332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.847375] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.847380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.847424] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.847535] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.847583] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.847626] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.847669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.847715] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.847758] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.847804] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.847848] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.847892] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.847936] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.848004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.848056] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.848101] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.863361] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.881870] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.881983] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.882061] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.882384] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.882428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.882532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.882576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.882622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.882665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.882710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.882753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.882797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.882841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.882889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.882936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.883005] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.883048] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.883103] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.883153] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.883200] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.883246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.883291] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.883335] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.883374] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.883951] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.884378] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.884423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.884499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.884548] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.884592] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.884637] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.884683] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.884728] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.884772] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.884815] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.884858] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.884867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.884910] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.884916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.884961] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.885004] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.885048] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.885091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.885134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.885179] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.885222] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.885268] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.885312] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.885355] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.885399] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.885488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.885547] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.885592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.885748] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.885787] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.886076] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.886130] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.886172] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.886230] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.886518] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.886844] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.886888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.886931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.886974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.887017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.887060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.887103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.887146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.887189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.887231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.887278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.887323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.887396] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.887475] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.888883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.888927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.888971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.889760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.889804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.890530] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.890574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.891610] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.893710] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.894726] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.894895] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.894950] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.895120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.911887] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.911936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.911981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.912025] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.912067] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.912111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.912154] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.912197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.912241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.912283] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.912325] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.912334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.912375] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.912381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.912424] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.912535] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.912585] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.912629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.912673] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.912721] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.912767] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.912815] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.912858] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.912906] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.912950] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.913014] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.913066] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.913110] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.928340] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.946865] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.946978] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.947057] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.947374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.947418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.947523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.947569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.947614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.947658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.947703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.947747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.947790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.947833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.947880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.947925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.947995] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.948037] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.948092] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.948142] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.948191] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.948238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.948283] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.948328] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 561.948367] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 561.948952] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.949377] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.949423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.949502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.949549] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.949593] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.949638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.949683] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.949725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.949769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.949811] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.949854] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.949864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.949906] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.949912] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.949955] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.949999] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.950042] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.950086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.950129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.950174] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.950217] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.950262] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.950306] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.950350] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.950393] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.950481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.950536] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.950579] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.950732] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 561.950771] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 561.951060] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 561.951113] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.951153] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 561.951209] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 561.951432] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.951787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.951836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 561.951882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.951928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.951972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.952015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 561.952063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 561.952107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 561.952150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 561.952194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 561.952242] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 561.952287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.952362] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 561.952406] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.953877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.953921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.953966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 561.954750] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.954793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 561.955514] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 561.955558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 561.956594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 561.958688] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 561.959696] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.959879] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 561.959934] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 561.960103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.976883] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 561.976931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 561.976976] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 561.977021] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 561.977064] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 561.977108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.977152] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 561.977195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.977239] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 561.977282] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.977325] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 561.977334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.977376] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 561.977382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.977425] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 561.977535] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 561.977584] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 561.977627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 561.977670] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 561.977716] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 561.977759] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 561.977805] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 561.977849] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 561.977898] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.977943] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 561.978011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 561.978066] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 561.978110] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 561.993337] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.011854] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.011967] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.012047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.012369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.012413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.012518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.012564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.012607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.012651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.012695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.012739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.012783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.012826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.012874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.012920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.012990] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.013033] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.013088] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.013138] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.013186] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.013233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.013278] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.013322] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 562.013361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 562.013938] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.014340] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.014385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.014430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.014504] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.014549] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.014595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.014640] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.014684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.014728] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.014771] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.014814] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.014823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.014866] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.014872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.014916] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.014959] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.015003] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.015046] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.015089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.015134] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.015177] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.015222] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.015266] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.015309] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.015353] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.015416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.015500] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.015546] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.015700] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.015738] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.016028] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 562.016082] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.016123] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.016180] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.016517] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.016835] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.016880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.016923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.016966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.017008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.017051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.017094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.017137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.017180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.017223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.017270] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.017314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.017388] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.017431] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.018881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.018925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.018970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 562.019753] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.019798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.020515] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 562.020559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 562.021592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 562.025489] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 562.026525] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.026694] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.026748] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.026917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.043678] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.043725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.043770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.043814] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.043856] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.043899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.043942] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.043985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.044028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.044070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.044112] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.044121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.044162] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.044168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.044211] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.044254] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.044297] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.044339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.044381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.044426] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.044514] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.044562] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.044607] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.044653] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.044698] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.044760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.044809] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.044854] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.060106] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.077881] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.077994] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.078074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.078396] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.078485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.078530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.078574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.078617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.078662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.078705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.078748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.078791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.078834] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.078880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.078925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.078990] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.079033] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.079088] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.079138] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.079184] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.079231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.079276] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.079320] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 562.079359] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 562.079948] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.080379] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.080426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.080536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.080581] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.080622] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.080667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.080712] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.080755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.080799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.080842] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.080885] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.080894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.080937] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.080943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.080987] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.081030] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.081073] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.081116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.081159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.081204] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.081247] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.081292] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.081336] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.081379] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.081422] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.081507] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.081562] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.081605] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.081754] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.081792] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.082081] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 562.082135] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.082177] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.082234] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.082716] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.083038] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.083081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.083125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.083167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.083210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.083253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.083295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.083338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.083381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.083423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.084141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.084187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.084264] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.084307] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.085964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.086010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.086054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 562.086842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.086885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.087621] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 562.087666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 562.088808] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 562.090903] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 562.091924] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.092088] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.092143] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.092313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.109106] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.109170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.109229] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.109284] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.109335] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.109392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.109531] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.109585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.109638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.109689] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.109739] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.109755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.109808] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.109814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.109863] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.109907] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.109950] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.109993] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.110035] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.110080] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.110123] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.110170] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.110214] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.110257] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.110300] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.110370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.110427] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.110510] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.125601] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.143844] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.143956] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.144037] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.144357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.144401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.144505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.144550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.144593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.144636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.144679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.144722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.144766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.144810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.144856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.144901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.144967] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.145009] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.145064] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.145113] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.145159] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.145205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.145250] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.145293] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 562.145332] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 562.145930] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.146910] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.146956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.147002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.147045] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.147087] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.147132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.147175] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.147218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.147261] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.147303] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.147344] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.147354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.147395] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.147432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.147476] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.147519] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.147562] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.147604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.147647] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.147691] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.147733] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.147779] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.147823] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.147867] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.147910] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.147978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.148032] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.148075] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.148221] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.148259] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.148575] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 562.148629] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.148671] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.148729] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.149715] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.150042] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.150086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.150129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.150172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.150215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.150257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.150300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.150343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.150385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.150429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.150517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.150563] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.150638] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.150682] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.152394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.152467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.152513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 562.153399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.153575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.154339] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 562.154386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 562.155556] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 562.157672] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 562.158722] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.158911] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.158966] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.159136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.175869] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.175917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.175962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.176006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.176048] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.176092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.176136] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.176179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.176222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.176265] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.176307] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.176316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.176358] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.176363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.176407] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.176502] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.176548] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.176596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.176642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.176689] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.176734] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.176781] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.176825] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.176868] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.176912] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.176978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.177029] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.177073] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.192352] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.210754] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.210868] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.210946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.211265] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.211308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.211352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.211395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.211530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.211573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.211617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.211660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.211704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.211748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.211796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.211842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.211911] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.211955] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.212011] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.212062] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.212109] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.212155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.212200] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.212244] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 562.212283] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 562.212863] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.213270] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.213314] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.213360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.213404] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.213479] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.213524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.213569] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.213612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.213656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.213700] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.213742] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.213752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.213794] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.213800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.213844] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.213888] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.213932] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.213975] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.214018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.214064] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.214106] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.214152] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.214195] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.214239] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.214282] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.214345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.214399] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.214463] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.214649] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.214687] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.214977] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 562.215031] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.215074] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.215131] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.215421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.215775] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.215820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.215863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.215906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.215949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.215992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.216035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.216078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.216121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.216164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.216210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.216255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.216329] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.216372] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.217814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.217858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.217902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 562.218668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.218714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.219427] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 562.219498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 562.220548] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 562.222644] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 562.223703] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.223896] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.223952] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.224122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.240870] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.240917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.240962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.241006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.241048] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.241092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.241136] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.241179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.241222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.241264] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.241306] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.241315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.241356] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.241362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.241405] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.241517] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.241564] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.241607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.241650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.241696] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.241738] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.241785] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.241828] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.241872] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.241915] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.241982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.242034] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.242078] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.257343] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.275848] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.275960] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.276040] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.276360] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.276404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.276537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.276581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.276624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.276668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.276712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.276755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.276799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.276843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.276891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.276937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.277006] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.277049] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.277104] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.277154] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.277202] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.277250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.277294] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.277338] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 562.277377] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 562.277982] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.278925] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.278970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.279015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.279059] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.279101] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.279146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.279189] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.279232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.279275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.279317] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.279359] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.279368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.279409] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.279445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.279490] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.279533] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.279576] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.279619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.279662] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.279708] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.279751] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.279797] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.279840] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.279884] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.279927] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.279989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.280044] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.280087] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.280236] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.280274] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.280584] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 562.280639] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.280681] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.280738] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.281024] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.281344] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.281389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.281472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.281519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.281565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.281609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.281652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.281696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.281740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.281784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.281833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.281878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.281953] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.281997] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.283439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.283510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.283555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 562.284310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.284353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.285092] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:16 BXT-2 kernel: [ 562.285135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:16 BXT-2 kernel: [ 562.286174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:16 BXT-2 kernel: [ 562.288265] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:16 BXT-2 kernel: [ 562.289243] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.289431] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.289576] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.289748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.306412] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.306483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.306528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.306572] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.306614] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.306658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.306701] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.306745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.306788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.306830] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.306872] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.306881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.306923] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.306929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.306972] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.307015] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.307058] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.307101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.307143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.307188] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.307230] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.307275] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.307318] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.307361] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.307404] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.307503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.307556] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.307599] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.322868] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.341377] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.341587] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.341668] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.341997] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.342041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.342084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.342127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.342170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.342213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.342256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.342299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.342342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.342385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.342431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.342506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.342576] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.342619] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.342674] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.342724] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:16 BXT-2 kernel: [ 562.342773] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:16 BXT-2 kernel: [ 562.342821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.342866] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.342910] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:16 BXT-2 kernel: [ 562.342949] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:16 BXT-2 kernel: [ 562.343552] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.344520] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:16 BXT-2 kernel: [ 562.344568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:16 BXT-2 kernel: [ 562.344614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:16 BXT-2 kernel: [ 562.344658] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:16 BXT-2 kernel: [ 562.344704] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:16 BXT-2 kernel: [ 562.344748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.344791] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:16 BXT-2 kernel: [ 562.344834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.344879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:16 BXT-2 kernel: [ 562.344922] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.344964] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:16 BXT-2 kernel: [ 562.344973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.345016] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:16 BXT-2 kernel: [ 562.345023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.345067] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:16 BXT-2 kernel: [ 562.345110] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:16 BXT-2 kernel: [ 562.345154] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:16 BXT-2 kernel: [ 562.345197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:16 BXT-2 kernel: [ 562.345240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:16 BXT-2 kernel: [ 562.345286] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:16 BXT-2 kernel: [ 562.345329] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:16 BXT-2 kernel: [ 562.345374] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:16 BXT-2 kernel: [ 562.345418] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:16 BXT-2 kernel: [ 562.345495] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.345539] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:16 BXT-2 kernel: [ 562.345603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.345658] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.345701] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:16 BXT-2 kernel: [ 562.345852] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:16 BXT-2 kernel: [ 562.345890] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:16 BXT-2 kernel: [ 562.346181] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:16 BXT-2 kernel: [ 562.346235] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.346278] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:16 BXT-2 kernel: [ 562.346335] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:16 BXT-2 kernel: [ 562.346654] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.346976] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:16 BXT-2 kernel: [ 562.347020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:16 BXT-2 kernel: [ 562.347063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.347106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.347149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.347192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:16 BXT-2 kernel: [ 562.347235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:16 BXT-2 kernel: [ 562.347278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:16 BXT-2 kernel: [ 562.347321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:16 BXT-2 kernel: [ 562.347364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:16 BXT-2 kernel: [ 562.347410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:16 BXT-2 kernel: [ 562.347505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.347581] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:16 BXT-2 kernel: [ 562.347625] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:16 BXT-2 kernel: [ 562.349061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.349105] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.349149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:16 BXT-2 kernel: [ 562.349905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:16 BXT-2 kernel: [ 562.349948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.350699] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.350744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.351788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.353882] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.354874] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.355044] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.355098] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.355269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.372030] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.372077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.372122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.372166] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.372208] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.372252] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.372296] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.372339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.372383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.372425] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.372536] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.372549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.372592] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.372598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.372641] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.372685] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.372729] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.372772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.372815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.372861] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.372904] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.372950] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.372993] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.373037] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.373081] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.373147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.373200] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.373244] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.388512] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.406746] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.406858] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.406940] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.407256] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.407301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.407346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.407389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.407432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.407524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.407569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.407612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.407656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.407700] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.407746] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.407791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.407855] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.407897] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.407951] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.408000] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.408049] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.408094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.408138] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.408182] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.408221] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.408805] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.409227] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.409272] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.409318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.409362] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.409404] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.409496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.409541] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.409584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.409627] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.409670] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.409712] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.409722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.409764] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.409770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.409814] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.409857] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.409900] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.409943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.409986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.410031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.410074] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.410119] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.410163] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.410206] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.410250] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.410314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.410368] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.410411] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.410610] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.410648] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.410938] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.410991] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.411033] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.411090] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.411522] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.411855] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.411901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.411949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.411992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.412035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.412079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.412122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.412165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.412208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.412252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.412299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.412344] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.412420] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.412521] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.414323] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.414368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.414413] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 562.415577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.415622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.416359] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.416404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.424094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.426193] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.427215] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.427378] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.427433] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.427855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.444326] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.444373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.444418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.444735] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.444777] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.444823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.444868] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.444911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.444954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.444996] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.445038] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.445047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.445089] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.445095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.445138] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.445180] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.445223] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.445265] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.445307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.445353] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.445395] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.446249] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.446292] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.446336] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.446378] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.446674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.446731] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.446774] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.460882] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.478718] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.478831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.478911] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.479230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.479274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.479318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.479361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.479403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.479879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.479922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.479965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.480008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.480050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.480099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.480143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.480206] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.480248] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.480301] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.480350] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.480396] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.480952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.481000] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.481044] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.481082] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.482364] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.483058] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.483105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.483151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.483195] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.483238] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.483283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.483326] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.483370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.483413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.483918] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.483961] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.483970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.484012] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.484018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.484061] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.484104] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.484147] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.484190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.484232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.484278] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.484320] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.484366] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.484410] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.484991] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.485034] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.485101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.485154] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.485197] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.485345] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.485382] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.485992] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.486299] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.486339] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.486396] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.486893] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.487217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.487260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.487306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.487350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.487393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.487736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.487779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.487822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.487864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.487907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.487955] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.488000] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.488074] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.488117] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.489881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.489926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.489970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 562.490915] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.490961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.492126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.493513] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.494503] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.494677] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.494731] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.494901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.511832] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.511879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.511925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.511969] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.512011] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.512055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.512098] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.512141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.512185] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.512227] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.512269] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.512278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.512320] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.512326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.512369] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.512412] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.512492] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.512539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.512585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.512634] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.512680] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.512727] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.512773] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.512820] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.512866] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.512931] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.512981] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.513028] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.528097] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.546677] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.546790] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.546869] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.547186] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.547230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.547273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.547316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.547359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.547402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.547496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.547543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.547589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.547634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.547683] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.547730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.547792] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.547837] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.547890] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.547939] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.547985] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.548031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.548074] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.548118] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.548158] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.548731] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.549164] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.549209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.549254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.549298] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.549340] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.549384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.549427] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.549545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.549589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.549631] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.549673] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.549682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.549724] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.549731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.549775] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.549817] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.549861] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.549904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.549947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.549993] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.550036] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.550082] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.550126] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.550170] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.550213] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.550274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.550328] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.550372] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.550547] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.550585] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.550875] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.550928] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.550971] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.551028] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.551330] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.551655] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.551702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.551748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.551793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.551838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.551884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.551929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.551975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.552020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.552067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.552115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.552162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.552237] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.552280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.554823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.554878] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.554924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 562.555775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.555820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.556674] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.556718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.557894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.559988] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.561006] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.561175] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.561230] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.561399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.578140] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.578187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.578232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.578276] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.578318] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.578362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.578406] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.578499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.578548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.578592] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.578637] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.578649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.578692] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.578699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.578742] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.578789] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.578834] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.578877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.578920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.578964] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.579006] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.579051] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.579095] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.579139] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.579183] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.579245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.579296] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.579339] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.594597] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.612760] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.612875] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.612953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.613280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.613324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.613368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.613410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.613536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.613582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.613628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.613673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.613717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.613762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.613812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.613858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.613927] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.613970] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.614024] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.614076] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.614121] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.614168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.614212] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.614257] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.614297] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.614880] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.615307] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.615352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.615399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.615473] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.615515] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.615559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.615606] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.615651] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.615698] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.615743] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.615785] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.615797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.615841] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.615848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.615892] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.615935] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.615979] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.616022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.616065] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.616111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.616153] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.616198] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.616242] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.616286] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.616329] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.616394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.616481] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.616529] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.616686] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.616724] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.617015] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.617068] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.617110] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.617168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.617489] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.617816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.617860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.617904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.617948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.617992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.618035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.618079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.618122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.618166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.618209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.618256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.618301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.618376] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.618420] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.619883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.619927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.619971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 562.620749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.620791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.621511] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.621555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.622588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.624675] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.625673] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.625846] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.625901] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.626071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.642829] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.642875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.642921] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.642964] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.643006] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.643050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.643093] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.643136] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.643180] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.643222] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.643264] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.643273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.643314] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.643320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.643363] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.643406] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.643520] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.643565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.643609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.643659] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.643702] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.643748] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.643792] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.643836] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.643879] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.643943] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.643995] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.644038] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.659320] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.677835] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.677948] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.678026] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.678350] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.678394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.678471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.678520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.678568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.678614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.678659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.678703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.678751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.678795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.678842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.678888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.678957] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.679000] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.679054] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.679105] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.679153] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.679200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.679245] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.679290] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.679329] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.679928] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.680876] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.680921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.680966] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.681009] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.681052] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.681095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.681139] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.681182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.681225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.681268] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.681309] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.681318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.681360] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.681366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.681409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.681515] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.681559] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.681603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.681645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.681692] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.681734] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.681780] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.681823] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.681867] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.681910] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.681974] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.682028] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.682072] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.682228] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.682266] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.682584] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.682642] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.682684] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.682743] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.683020] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.683339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.683383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.683426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.683508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.683552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.683596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.683643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.683688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.683733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.683779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.683829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.683875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.683949] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.683993] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.685432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.685502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.685547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 562.686306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.686349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.687084] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.687127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.688171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.690264] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.691268] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.691511] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.691566] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.691738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.708437] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.708536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.708582] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.708626] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.708669] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.708713] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.708756] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.708799] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.708842] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.708884] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.708927] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.708936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.708978] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.708983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.709027] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.709070] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.709113] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.709155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.709198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.709243] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.709285] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.709329] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] FB:79, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:31:17 BXT-2 kernel: [ 562.709373] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:31:17 BXT-2 kernel: [ 562.709416] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.709499] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.709564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.709619] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.709662] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.724905] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:17 BXT-2 kernel: [ 562.743422] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:17 BXT-2 kernel: [ 562.743632] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.743712] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.744038] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.744082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.744125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.744168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.744211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.744254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.744297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.744340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.744383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.744426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.744505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.744557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.744627] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.744670] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.744725] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.744776] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.744822] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.744869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.744913] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.744957] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.744997] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.745575] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.745979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.746075] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.746113] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.746401] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.746497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.746545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.746591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.746637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.746681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.746727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.746774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.746817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.746860] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.746904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.746950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.746995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.747057] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 562.747102] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.747145] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 562.747183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 562.747757] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.779335] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 562.779378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 562.779421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 562.779527] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 562.779568] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 562.779611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.779654] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:17 BXT-2 kernel: [ 562.779696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.779738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 562.779779] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.779819] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 562.779828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.779869] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 562.779873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.779915] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 562.779957] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 562.779998] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 562.780040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 562.780080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 562.780125] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 562.780166] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 562.780208] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.780249] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.780290] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.780331] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 562.780375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.780425] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.780485] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:17 BXT-2 kernel: [ 562.780608] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 562.780644] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 562.780932] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 562.780986] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.781025] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 562.781080] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 562.781352] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.781677] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 562.781719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 562.781761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.781802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.781843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.781885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 562.781926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 562.781967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 562.782009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 562.782050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 562.782095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 562.782139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.782211] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:17 BXT-2 kernel: [ 562.782253] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.783721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.783763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.783807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 562.784576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.784617] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 562.785357] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 562.785400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 562.786519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 562.788539] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 562.789752] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:17 BXT-2 kernel: [ 562.806643] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 562.806697] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 562.806874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 562.807240] Console: switching to colour frame buffer device 240x67 >May 24 03:31:17 BXT-2 kernel: [ 563.029316] Console: switching to colour dummy device 80x25 >May 24 03:31:17 BXT-2 kernel: [ 563.049930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:17 BXT-2 kernel: [ 563.049990] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:17 BXT-2 kernel: [ 563.050006] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:17 BXT-2 kernel: [ 563.050028] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.050074] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.050852] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:17 BXT-2 kernel: [ 563.051734] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:17 BXT-2 kernel: [ 563.051780] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:17 BXT-2 kernel: [ 563.051823] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:17 BXT-2 kernel: [ 563.051865] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:17 BXT-2 kernel: [ 563.052349] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:17 BXT-2 kernel: [ 563.052391] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:17 BXT-2 kernel: [ 563.057195] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:17 BXT-2 kernel: [ 563.057260] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:17 BXT-2 kernel: [ 563.057267] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057272] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057277] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057282] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057287] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057293] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057298] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:17 BXT-2 kernel: [ 563.057303] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057308] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.057313] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:17 BXT-2 kernel: [ 563.057318] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:17 BXT-2 kernel: [ 563.057323] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:17 BXT-2 kernel: [ 563.058633] [drm:drm_mode_addfb2] [FB:76] >May 24 03:31:17 BXT-2 kernel: [ 563.058693] [drm:drm_mode_addfb2] [FB:80] >May 24 03:31:17 BXT-2 kernel: [ 563.176332] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.176558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.176733] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:17 BXT-2 kernel: [ 563.190785] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:17 BXT-2 kernel: [ 563.190899] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.190986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.191307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.191352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 563.191396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.192116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.192160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.192203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 563.192255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.192298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.192340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.192384] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.192431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 563.193202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 563.193247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.193312] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 563.193355] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.193409] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.194047] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.194107] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 563.194151] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 563.194189] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 563.195379] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 563.196034] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:17 BXT-2 kernel: [ 563.196643] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:17 BXT-2 kernel: [ 563.197181] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.197226] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.197340] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 563.197419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 563.197499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 563.197543] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 563.197585] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 563.197629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.197673] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:17 BXT-2 kernel: [ 563.197729] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.197775] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 563.197820] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.197863] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 563.197872] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.197914] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 563.197923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.197966] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.198011] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 563.198054] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 563.198098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 563.198140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.198186] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 563.198228] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 563.198271] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.198315] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.198358] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.198402] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.198497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.198551] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.198594] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:17 BXT-2 kernel: [ 563.199308] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 563.199348] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 563.199671] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 563.199730] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.199770] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.199827] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 563.200069] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.200392] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.200470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 563.200515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.200560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.200605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.200649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 563.200691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.200735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.200778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.200822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 563.200869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 563.200914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.200989] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:17 BXT-2 kernel: [ 563.201032] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.202487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 563.202531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 563.202576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 563.203338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 563.203380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 563.204172] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 563.204216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 563.205308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 563.207402] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 563.208536] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:17 BXT-2 kernel: [ 563.225449] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.225564] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.225739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.242034] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.242095] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.258866] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.259008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.275432] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:17 BXT-2 kernel: [ 563.293913] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:17 BXT-2 kernel: [ 563.294025] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.294113] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.294723] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.294768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 563.294812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.294854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.294897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.294940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 563.294987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.295030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.295072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.295207] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.295255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 563.295300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 563.295345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.295404] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 563.296017] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.296071] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.296136] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.296190] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:17 BXT-2 kernel: [ 563.296233] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:17 BXT-2 kernel: [ 563.296272] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:17 BXT-2 kernel: [ 563.297433] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:17 BXT-2 kernel: [ 563.297627] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.297679] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.297797] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:17 BXT-2 kernel: [ 563.297839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:17 BXT-2 kernel: [ 563.297884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:17 BXT-2 kernel: [ 563.297928] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:17 BXT-2 kernel: [ 563.297970] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:17 BXT-2 kernel: [ 563.298013] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.298056] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:17 BXT-2 kernel: [ 563.298098] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.298141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:17 BXT-2 kernel: [ 563.298183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.298225] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:17 BXT-2 kernel: [ 563.298231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.298273] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:17 BXT-2 kernel: [ 563.298279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.298322] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:17 BXT-2 kernel: [ 563.298364] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:17 BXT-2 kernel: [ 563.298407] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:17 BXT-2 kernel: [ 563.299277] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:17 BXT-2 kernel: [ 563.299320] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:17 BXT-2 kernel: [ 563.299365] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:17 BXT-2 kernel: [ 563.299407] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:17 BXT-2 kernel: [ 563.299673] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.299716] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.299759] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.299802] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:17 BXT-2 kernel: [ 563.299867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.299920] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.299963] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:17 BXT-2 kernel: [ 563.300103] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:17 BXT-2 kernel: [ 563.300141] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:17 BXT-2 kernel: [ 563.300810] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:17 BXT-2 kernel: [ 563.301118] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.301158] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:17 BXT-2 kernel: [ 563.301213] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:17 BXT-2 kernel: [ 563.301649] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.301968] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.302012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:17 BXT-2 kernel: [ 563.302056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.302098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.302141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.302184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:17 BXT-2 kernel: [ 563.302226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:17 BXT-2 kernel: [ 563.302269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:17 BXT-2 kernel: [ 563.302311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:17 BXT-2 kernel: [ 563.302354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:17 BXT-2 kernel: [ 563.302400] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:17 BXT-2 kernel: [ 563.302907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.303101] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:17 BXT-2 kernel: [ 563.303144] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.304742] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:17 BXT-2 kernel: [ 563.304785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:17 BXT-2 kernel: [ 563.304830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:17 BXT-2 kernel: [ 563.306000] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:17 BXT-2 kernel: [ 563.306046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:17 BXT-2 kernel: [ 563.307143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:17 BXT-2 kernel: [ 563.309273] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:17 BXT-2 kernel: [ 563.310336] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:17 BXT-2 kernel: [ 563.327260] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:17 BXT-2 kernel: [ 563.327318] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.327840] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:17 BXT-2 kernel: [ 563.328195] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:17 BXT-2 kernel: [ 563.328341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:17 BXT-2 kernel: [ 563.343871] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.361902] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.362015] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.362103] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.362423] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.362786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.362831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.362874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.363012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.363055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.363104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.363147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.363190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.363233] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.363280] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.363325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.363370] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.363579] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.363623] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.363678] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.363740] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.363795] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.363839] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.363877] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.364425] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.364631] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.364685] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.364808] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.364851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.364896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.364939] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.364981] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.365025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.365068] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.365111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.365154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.365196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.365238] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.365245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.365287] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.365293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.365336] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.365378] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.365421] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.365508] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.365551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.365596] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.365638] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.365682] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.365725] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.365768] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.365811] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.365874] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.365925] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.365969] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.366111] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.366148] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.366460] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.366515] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.366556] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.366612] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.367002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.367323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.367366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.367409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.367505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.367551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.367596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.367639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.367683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.367726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.367769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.367817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.367861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.367935] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.367978] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.369422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.369490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.369534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.370355] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.370399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.371503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.373507] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.374538] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.391452] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.391564] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.391736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.392085] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.392216] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.408083] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.425713] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.425826] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.425914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.426237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.426281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.426324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.426367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.426410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.426495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.426547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.426596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.426642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.426688] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.426737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.426783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.426832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.426900] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.426942] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.426997] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.427059] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.427111] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.427154] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.427193] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.427810] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.428499] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.428553] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.428679] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.428723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.428767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.428811] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.428853] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.428896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.428939] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.428982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.429025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.429067] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.429108] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.429115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.429156] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.429162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.429205] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.429248] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.429290] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.429333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.429375] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.429419] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.429509] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.429555] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.429601] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.429646] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.429692] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.429759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.429813] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.429862] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.430011] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.430049] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.430338] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.430393] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.430466] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.430526] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.430772] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.431094] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.431138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.431182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.431225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.431268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.431312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.431355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.431398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.431511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.431556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.431606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.431653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.431728] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.431771] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.433229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.433272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.433317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.434104] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.434149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.434900] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.434946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.435997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.438092] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.439108] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.455988] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.456044] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.456215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.456599] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.456744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.472641] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.490696] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.490809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.490898] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.491222] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.491266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.491309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.491352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.491395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.491497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.491548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.491593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.491637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.491683] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.491731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.491776] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.491821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.491883] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.491926] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.491980] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.492044] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.492097] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.492142] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.492181] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.492764] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.492942] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.492996] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.493121] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.493166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.493212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.493258] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.493301] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.493345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.493390] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.493467] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.493515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.493560] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.493605] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.493615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.493659] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.493667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.493711] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.493757] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.493801] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.493844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.493886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.493931] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.493973] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.494019] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.494062] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.494106] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.494148] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.494213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.494266] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.494310] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.494487] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.494529] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.494830] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.494886] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.494926] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.494986] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.495251] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.495583] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.495628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.495672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.495714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.495757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.495802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.495845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.495888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.495931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.495975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.496023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.496068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.496143] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.496186] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.497918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.497963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.498008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.498911] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.498956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.500001] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.502086] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.503171] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.520064] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.520121] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.520291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.520685] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.520833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.536705] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.555250] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.555364] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.555881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.556211] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.556256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.556301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.556344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.556387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.556431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.556813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.556857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.556901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.556944] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.556993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.557040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.557085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.557147] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.557190] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.557244] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.557305] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.557358] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.557401] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.557754] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.558347] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.559446] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.559556] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.559720] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.559779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.559834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.559880] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.559922] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.559967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.560013] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.560056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.560099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.560142] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.560184] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.560193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.560235] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.560241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.560283] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.560326] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.560369] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.560412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.560972] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.561018] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.561060] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.561104] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.561148] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.561191] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.561234] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.561303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.561356] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.561400] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.561825] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.561863] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.562157] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.562213] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.562254] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.562311] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.562895] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.563219] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.563263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.563306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.563349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.563392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.563518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.563780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.563823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.563867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.563911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.563960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.564005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.564080] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.564124] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.565577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.565622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.565666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.566415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.566704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.567432] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.567613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.568809] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.570908] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.571987] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.588867] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.588924] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.589095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.589704] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.589869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.605589] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.623047] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.623160] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.623248] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.624012] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.624061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.624105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.624221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.624264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.624308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.624389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.624432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.625233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.625278] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.625331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.625377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.625422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.626051] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.626094] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.626148] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.626209] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.626262] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.626305] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.626344] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.627776] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.627963] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.628015] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.628130] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.628174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.628219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.628262] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.628304] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.628348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.628391] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.628492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.628537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.628580] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.628624] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.628632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.628675] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.628682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.628727] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.628772] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.628818] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.628861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.628904] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.628950] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.628993] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.629037] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.629079] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.629122] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.629164] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.629227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.629281] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.629325] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.629547] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.629585] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.629875] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.629930] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.629972] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.630028] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.630642] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.630970] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.631014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.631058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.631101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.631144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.631186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.631229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.631272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.631314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.631357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.631404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.631495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.631571] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.631846] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.633294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.633339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.633383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.634207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.634251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.635123] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.635168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.636246] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.638354] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.639392] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.656338] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.656395] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.656635] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.656955] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.657094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.673008] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.691562] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.691675] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.691763] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.692086] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.692130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.692173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.692216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.692259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.692301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.692348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.692390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.692492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.692541] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.692591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.692638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.692685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.692745] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.692790] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.692843] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.692904] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.692955] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.692997] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.693037] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.693618] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.693794] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.693845] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.693965] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.694009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.694054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.694099] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.694142] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.694186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.694230] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.694273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.694317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.694360] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.694403] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.694431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.694476] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.694482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.694526] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.694569] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.694613] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.694656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.694699] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.694744] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.694787] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.694831] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.694875] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.694918] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.694962] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.695028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.695083] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.695127] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.695294] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.695333] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.695654] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.695711] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.695753] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.695810] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.696034] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.696355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.696399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.696486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.696531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.696575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.696619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.696662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.696705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.696748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.696791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.696838] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.696882] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.696956] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.696999] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.698407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.698481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.698526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.699291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.699334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.700068] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.700112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.701154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.703273] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.704287] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.721213] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.721269] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.721501] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.721901] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.722047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.737900] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.756409] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.756544] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.756633] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.756953] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.756997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.757041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.757085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.757128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.757172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.757219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.757262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.757305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.757349] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.757397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.757532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.757581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.757642] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.757689] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.757744] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.757812] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.757866] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.757910] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.757949] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.758549] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.759220] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.759274] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.759391] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.759476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.759527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.759573] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.759617] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.759662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.759708] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.759753] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.759797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.759839] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.759882] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.759888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.759932] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.759938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.759981] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.760025] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.760072] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.760114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.760157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.760203] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.760246] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.760290] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.760333] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.760376] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.760420] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.760508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.760561] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.760605] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.760754] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.760793] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.761083] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.761137] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.761180] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.761236] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.761510] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.761833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.761877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.761921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.761964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.762007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.762050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.762094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.762137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.762180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.762224] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.762271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.762316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.762390] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.762457] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.763896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.763940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.763985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.764780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.764823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.765545] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.765590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.766628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.768723] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.769752] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.786664] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.786721] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.786890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.787282] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.787426] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.803371] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.822039] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.822152] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.822236] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.822687] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.822734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.822778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.822821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.822864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.822907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.822955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.822998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.823041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.823086] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.823134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.823180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.823225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.823288] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.823331] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.823385] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.823485] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.823538] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.823581] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.823620] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.824170] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.824337] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.824371] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.824545] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.824589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.824635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.824681] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.824723] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.824768] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.824811] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.824855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.824899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.824941] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.824984] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.824991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.825034] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.825040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.825084] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.825127] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.825171] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.825213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.825256] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.825302] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.825344] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.825387] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.825431] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.825536] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.825578] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.825642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.825694] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.825738] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.825878] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.825915] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.826204] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.826258] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.826299] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.826355] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.827211] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.827539] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.827585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.827629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.827673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.827716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.827760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.827803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.827846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.827889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.827932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.827980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.828025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.828101] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.828144] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.829887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.829931] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.829975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.830792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.830837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.831591] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.831635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.832747] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.834845] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.835904] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.852825] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.852881] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.853052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.853783] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.853939] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.869577] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.888087] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.888200] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.888288] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.888918] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.888964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.889008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.889051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.889094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.889137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.889186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.889230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.889273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.889317] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.889365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.889411] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.889817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.889879] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.889924] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.889980] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.890044] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.890099] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.890143] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.890183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.891353] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.891744] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.891795] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.891916] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.891960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.892005] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.892049] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.892091] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.892136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.892179] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.892222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.892265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.892308] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.892350] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.892356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.892398] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.892790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.892850] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.892894] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.892938] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.892981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.893025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.893071] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.893114] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.893158] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.893202] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.893245] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.893289] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.893358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.893411] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.893803] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.893957] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.893996] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.894287] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.894341] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.894382] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.894766] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.895023] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.895341] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.895385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.895429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.895768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.895812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.895857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.895900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.895944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.895987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.896031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.896081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.896126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.896202] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.896245] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.897809] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.897853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.897898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.898671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.898714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.899425] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.899594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.900648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.902745] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.903788] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.920706] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.920763] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.920934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.921328] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.921676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.937382] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.955753] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.955870] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.955959] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.956280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.956324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.956367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.956410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.956855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.956901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.956950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.956993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.957036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.957079] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.957127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.957172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.957217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.957278] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.957321] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.957374] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.957516] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.957573] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.957619] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 563.957658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 563.958210] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.958387] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.958469] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.958589] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 563.958633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 563.958678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 563.958722] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 563.958765] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 563.958809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.958853] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 563.958897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.958941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 563.958983] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.959026] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 563.959033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.959075] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 563.959082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.959125] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 563.959168] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 563.959212] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 563.959255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 563.959298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 563.959343] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 563.959386] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 563.959430] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.959501] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.959548] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.959594] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 563.959656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.959710] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.959755] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.959903] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 563.959941] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 563.960231] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 563.960285] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.960325] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 563.960381] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 563.960717] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.961055] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 563.961100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 563.961144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.961186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.961229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.961272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 563.961315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 563.961358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 563.961400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 563.961515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 563.961566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 563.961612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.961687] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 563.961730] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.963151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.963195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.963239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 563.964032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.964075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 563.964803] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 563.964847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 563.965893] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 563.967991] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 563.969036] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 563.985944] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 563.986000] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.986170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 563.986633] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 563.986783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.002631] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.021150] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.021263] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.021351] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.021679] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.021725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.021771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.021815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.021860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.021904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.021953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.021998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.022043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.022088] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.022137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.022183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.022230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.022300] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.022344] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.022400] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.022488] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.022543] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.022586] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 564.022626] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 564.023176] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.023359] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.023427] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.023549] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 564.023594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 564.023640] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 564.023685] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 564.023728] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 564.023773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.023817] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 564.023860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.023904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 564.023948] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.023991] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 564.023998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.024040] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 564.024046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.024090] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.024134] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 564.024178] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 564.024221] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 564.024264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.024310] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 564.024353] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 564.024396] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.024461] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.024504] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.024548] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.024610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.024664] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.024708] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.024857] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.024895] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.025186] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 564.025241] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.025284] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.025341] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.025662] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.025988] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.026033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.026077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.026120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.026163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.026206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.026249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.026292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.026334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.026378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.026424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.026511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.026586] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.026629] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.028066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.028110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.028155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 564.028925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.028968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.029714] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 564.029758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 564.030791] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 564.032880] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 564.033925] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.050842] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.050898] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.051069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.051800] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.051955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.067578] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.086093] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.086206] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.086294] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.086718] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.086764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.086809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.086852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.086896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.086940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.086988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.087032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.087076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.087119] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.087167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.087215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.087261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.087322] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.087365] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.087420] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.087639] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.087693] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.087738] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 564.087778] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 564.088326] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.088601] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.088650] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.088768] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 564.088812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 564.088857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 564.088902] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 564.088944] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 564.088988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.089032] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 564.089074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.089118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 564.089160] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.089202] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 564.089209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.089251] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 564.089257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.089300] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.089343] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 564.089386] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 564.089429] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 564.089634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.089680] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 564.089723] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 564.089766] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.089810] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.089854] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.089897] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.089962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.090015] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.090059] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.090205] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.090243] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.090647] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 564.091153] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.091195] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.091250] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.091582] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.091908] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.091951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.091995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.092038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.092081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.092124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.092167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.092210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.092253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.092296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.092342] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.092388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.092615] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.092660] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.094092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.094135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.094180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 564.094983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.095026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.095780] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 564.095825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 564.096949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 564.099053] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 564.100116] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.117035] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.117092] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.117263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.118092] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.118239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.133717] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.152242] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.152355] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.152820] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.153154] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.153198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.153242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.153285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.153328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.153372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.153419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.153518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.153564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.153612] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.153663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.153710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.153758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.153821] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.153864] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.153919] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.153984] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.154037] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.154084] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 564.154123] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 564.154699] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.154877] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.154930] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.155051] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 564.155094] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 564.155139] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 564.155183] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 564.155225] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 564.155268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.155311] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 564.155354] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.155398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 564.155476] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.155522] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 564.155531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.155576] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 564.155584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.155630] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.155675] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 564.155719] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 564.155762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 564.155805] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.155851] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 564.155894] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 564.155937] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.155981] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.156024] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.156068] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.156131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.156184] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.156229] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.156378] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.156416] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.156731] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 564.156786] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.156828] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.156885] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.157176] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.157503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.157549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.157593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.157636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.157679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.157722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.157765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.157807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.157852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.157895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.157942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.157986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.158060] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.158104] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.159555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.159599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.159643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 564.160398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.160469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.161184] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 564.161228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 564.162293] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 564.164388] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 564.165468] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.182383] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.182500] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.182674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.183079] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.183224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.199068] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.217570] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.217683] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.217770] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.218092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.218136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.218180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.218223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.218266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.218310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.218356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.218399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.218504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.218554] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.218605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.218652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.218699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.218767] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.218810] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.218867] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.218929] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.218981] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.219024] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 564.219063] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 564.219639] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.219809] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.219866] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.219982] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 564.220026] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 564.220072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 564.220116] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 564.220159] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 564.220204] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.220248] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 564.220291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.220336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 564.220378] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.220421] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 564.220453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.220496] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 564.220502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.220546] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.220590] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 564.220633] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 564.220676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 564.220719] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.220765] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 564.220808] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 564.220852] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.220896] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.220939] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.220982] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.221045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.221098] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.221142] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.221294] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.221332] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.221645] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 564.221700] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.221742] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.221799] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.222085] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.222403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.222488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.222535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.222580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.222626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.222672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.222718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.222764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.222809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.222855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.222904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.222950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.223026] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.223069] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.224524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.224568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.224612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 564.225363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.225405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.226261] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 564.226305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 564.227350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 564.229441] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 564.230516] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.247436] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.247546] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.247718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.248118] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.248245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.264118] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.282066] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.282178] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.282265] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.282643] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.282688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.282732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.282776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.282820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.282864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.282912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.282956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.282999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.283043] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.283091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.283138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.283184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.283243] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.283286] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.283340] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.283403] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.283489] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.283535] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 564.283575] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 564.284126] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.284306] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.284354] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.284508] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:18 BXT-2 kernel: [ 564.284552] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:18 BXT-2 kernel: [ 564.284597] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:18 BXT-2 kernel: [ 564.284642] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:18 BXT-2 kernel: [ 564.284685] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:18 BXT-2 kernel: [ 564.284729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.284772] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:18 BXT-2 kernel: [ 564.284816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.284860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:18 BXT-2 kernel: [ 564.284903] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.284946] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:18 BXT-2 kernel: [ 564.284953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.284995] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:18 BXT-2 kernel: [ 564.285001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.285045] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:18 BXT-2 kernel: [ 564.285088] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:18 BXT-2 kernel: [ 564.285132] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:18 BXT-2 kernel: [ 564.285175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:18 BXT-2 kernel: [ 564.285218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:18 BXT-2 kernel: [ 564.285263] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:18 BXT-2 kernel: [ 564.285306] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:18 BXT-2 kernel: [ 564.285349] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.285393] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.285462] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.285509] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:18 BXT-2 kernel: [ 564.285573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.285627] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.285673] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.285827] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:18 BXT-2 kernel: [ 564.285865] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.286155] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:18 BXT-2 kernel: [ 564.286210] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.286252] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.286309] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.286643] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.286969] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.287013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.287056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.287099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.287142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.287184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.287227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.287270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.287313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.287356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.287403] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.287493] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.287569] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.287613] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.289020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.289062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.289106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:18 BXT-2 kernel: [ 564.289901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.289944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:18 BXT-2 kernel: [ 564.290698] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:18 BXT-2 kernel: [ 564.290742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:18 BXT-2 kernel: [ 564.291805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:18 BXT-2 kernel: [ 564.293906] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:18 BXT-2 kernel: [ 564.294929] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.311855] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.311911] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.312082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.313008] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.313175] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.328607] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:18 BXT-2 kernel: [ 564.347108] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:18 BXT-2 kernel: [ 564.347221] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.347311] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.347901] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:18 BXT-2 kernel: [ 564.347947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:18 BXT-2 kernel: [ 564.347990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.348033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.348076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.348119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:18 BXT-2 kernel: [ 564.348167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:18 BXT-2 kernel: [ 564.348210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:18 BXT-2 kernel: [ 564.348253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:18 BXT-2 kernel: [ 564.348296] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:18 BXT-2 kernel: [ 564.348343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:18 BXT-2 kernel: [ 564.348388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:18 BXT-2 kernel: [ 564.348791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:18 BXT-2 kernel: [ 564.348854] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:18 BXT-2 kernel: [ 564.348898] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.348953] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:18 BXT-2 kernel: [ 564.349016] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:18 BXT-2 kernel: [ 564.349068] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:18 BXT-2 kernel: [ 564.349112] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:18 BXT-2 kernel: [ 564.349151] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:18 BXT-2 kernel: [ 564.350323] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.350722] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.350773] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.350895] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.350939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.350984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.351028] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.351070] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.351114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.351157] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.351200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.351244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.351286] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.351328] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.351335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.351377] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.351383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.351426] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.351902] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.351946] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.351990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.352033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.352079] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.352122] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.352165] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.352209] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.352253] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.352296] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.352363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.352416] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.352752] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.352905] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.352943] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.353233] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.353287] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.353327] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.353383] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.353932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.354261] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.354305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.354348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.354391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.354709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.354754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.354796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.354839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.354882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.354925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.354973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.355018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.355092] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.355135] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.356844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.356888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.356933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.358022] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.358068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.359131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.361245] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.362291] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.379221] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.379278] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.379828] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.380228] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.380373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.395894] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.414433] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.414596] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.414685] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.415007] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.415051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.415094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.415137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.415180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.415223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.415270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.415313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.415356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.415400] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.415864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.415912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.415958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.416019] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.416063] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.416117] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.416180] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.416234] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.416278] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.416318] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.417510] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.417696] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.417750] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.417869] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.417912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.417957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.418001] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.418043] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.418088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.418130] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.418173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.418217] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.418259] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.418301] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.418308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.418350] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.418356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.418399] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.418868] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.418913] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.418956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.418999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.419046] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.419088] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.419132] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.419176] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.419220] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.419263] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.419329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.419383] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.419427] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.419615] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.419653] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.419944] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.419999] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.420041] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.420098] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.420392] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.420761] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.420806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.420849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.420892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.420935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.420978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.421021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.421064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.421106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.421150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.421196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.421241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.421315] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.421358] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.422805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.422849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.422893] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.423662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.423705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.424421] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.424490] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.425527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.427616] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.428648] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.445584] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.445640] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.445811] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.446213] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.446337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.462259] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.480716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.480828] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.480916] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.481234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.481278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.481321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.481364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.481406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.481487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.481536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.481578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.481622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.481666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.481714] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.481759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.481805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.481866] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.481908] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.481962] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.482025] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.482188] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.482233] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.482272] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.482879] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.483590] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.483638] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.483759] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.483802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.483847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.483891] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.483933] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.483977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.484020] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.484167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.484212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.484255] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.484296] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.484303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.484345] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.484351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.484394] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.484501] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.484546] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.484590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.484632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.484680] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.484722] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.484765] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.484808] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.484851] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.484894] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.484960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.485013] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.485058] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.485208] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.485247] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.485570] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.485625] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.485668] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.485724] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.486215] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.486680] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.486726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.486770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.486812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.486855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.486902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.486944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.486986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.487029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.487074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.487121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.487166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.487240] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.487283] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.489041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.489086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.489130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.489939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.489982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.490877] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.491353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.492516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.494506] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.495570] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.512448] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.512524] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.512694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.513033] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.513169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.529109] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.546860] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.546974] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.547062] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.547382] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.547426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.547556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.547840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.547883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.547931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.547982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.548025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.548069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.548112] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.548160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.548207] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.548252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.548313] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.548356] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.548410] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.548517] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.548570] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.548616] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.548655] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.549219] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.549448] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.549501] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.549627] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.549671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.549717] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.549761] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.549803] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.549848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.549891] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.549936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.549980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.550022] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.550065] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.550072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.550115] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.550121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.550165] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.550208] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.550251] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.550294] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.550336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.550381] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.550424] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.550490] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.550533] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.550576] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.550619] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.550680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.550732] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.550776] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.550917] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.550955] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.551244] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.551298] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.551339] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.551394] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.552202] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.552540] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.552586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.552631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.552674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.552717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.552761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.552804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.552848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.552891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.552934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.552982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.553027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.553104] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.553147] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.554905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.554949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.554993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.555834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.555880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.556612] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.556656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.557719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.559829] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.560881] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.577797] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.577854] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.578025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.578589] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.578745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.594548] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.613050] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.613163] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.613251] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.613588] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.613634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.613682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.613725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.613769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.613813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.613861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.613905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.613949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.613992] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.614041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.614087] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.614132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.614193] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.614238] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.614292] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.614355] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.614408] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.614591] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.614631] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.615178] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.615355] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.615557] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.615684] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.615728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.615774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.615819] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.615862] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.615907] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.615951] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.615995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.616039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.616082] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.616124] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.616132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.616175] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.616181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.616225] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.616269] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.616313] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.616356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.616399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.616582] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.616625] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.616669] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.616712] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.616756] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.616800] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.616864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.616918] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.616962] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.617105] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.617144] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.617547] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.618056] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.618097] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.618153] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.618438] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.618893] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.618937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.618981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.619024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.619067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.619110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.619153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.619196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.619239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.619282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.619329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.619373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.619564] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.619609] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.621030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.621074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.621119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.621949] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.621994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.623044] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.625146] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.626196] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.643129] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.643185] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.643355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.643905] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.644052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.659812] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.678331] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.678758] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.678849] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.679174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.679218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.679261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.679304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.679347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.679390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.679840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.679886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.679929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.679972] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.680020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.680066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.680111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.680171] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.680213] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.680267] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.680329] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.680382] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.680425] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.680833] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.681381] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.682115] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.682165] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.682287] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.682331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.682376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.682420] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.682745] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.682791] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.682835] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.682879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.682923] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.682966] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.683659] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.683669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.683712] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.683719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.683762] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.683805] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.683848] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.683891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.683933] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.683979] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.684021] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.684064] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.684108] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.684151] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.684194] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.684267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.684322] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.684549] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.684682] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.684720] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.685010] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.685065] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.685107] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.685163] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.685421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.685871] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.685915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.685960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.686004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.686046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.686093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.686137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.686179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.686222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.686264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.686311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.686355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.686429] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.686501] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.687984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.688030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.688074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.688859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.688903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.689644] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.689690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.690732] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.692827] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.693906] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.710804] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.710860] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.711032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.711457] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.711594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.727530] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.745878] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.745991] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.746080] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.746398] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.746511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.746555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.746602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.746645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.746690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.746738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.746782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.746826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.746870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.746918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.746964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.747010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.747079] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.747122] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.747177] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.747239] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.747292] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.747337] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.747376] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.747955] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.748138] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.748191] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.748310] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.748353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.748398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.748478] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.748523] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.748571] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.748617] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.748660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.748705] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.748747] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.748790] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.748797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.748840] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.748846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.748890] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.748933] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.748977] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.749020] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.749063] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.749108] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.749151] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.749195] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.749239] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.749283] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.749327] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.749390] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.749464] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.749512] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.749669] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.749708] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.749998] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.750053] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.750095] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.750152] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.750480] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.750804] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.750848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.750891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.750934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.750977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.751020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.751062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.751105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.751147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.751191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.751237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.751281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.751354] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.751397] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.752829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.752873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.752917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.753727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.753771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.754502] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.754546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.755583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.757693] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.758745] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.775674] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.775731] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.775901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.776298] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.776441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.792351] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.810878] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.810991] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.811079] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.811400] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.811479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.811523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.811566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.811618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.811665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.811712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.811756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.811804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.811849] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.811900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.811948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.811996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.812061] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.812104] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.812159] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.812222] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.812275] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.812320] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.812360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.812944] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.813124] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.813177] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.813298] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.813341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.813386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.813430] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.813539] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.813584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.813629] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.813673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.813717] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.813760] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.813803] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.813810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.813853] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.813859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.813903] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.813946] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.813990] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.814033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.814076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.814122] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.814165] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.814208] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.814252] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.814295] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.814338] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.814403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.814478] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.814523] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.814676] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.814714] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.815004] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.815059] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.815100] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.815157] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.815434] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.815780] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.815824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.815871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.815914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.815957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.816000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.816043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.816086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.816129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.816172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.816218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.816263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.816336] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.816379] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.817872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.817916] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.817961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.818779] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.818822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.819547] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.819592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.820629] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.822731] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.823817] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.840735] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.840792] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.840963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.841355] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.841569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.857423] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.875983] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.876096] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.876183] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.876505] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.876554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.876597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.876640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.876684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.876728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.876777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.876820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.876864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.876907] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.876955] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.877001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.877047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.877106] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.877150] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.877204] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.877267] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.877320] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.877364] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.877403] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.877987] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.878164] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.878200] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.878322] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.878365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.878411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.878499] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.878542] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.878589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.878633] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.878676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.878720] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.878763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.878806] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.878814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.878857] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.878863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.878906] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.878950] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.878993] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.879036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.879079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.879125] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.879167] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.879211] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.879254] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.879298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.879341] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.879406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.879479] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.879524] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.879684] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.879723] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.880015] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.880069] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.880111] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.880168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.880496] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.880821] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.880865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.880909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.880951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.880994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.881037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.881080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.881122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.881165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.881208] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.881255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.881299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.881372] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.881415] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.882882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.882925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.882969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.883771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.883815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.884538] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.884586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.885620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.887712] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.888758] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.905672] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.905728] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.905898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.906285] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.906423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.922361] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.940864] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.940976] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.941064] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.941383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.941427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.941529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.941577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.941623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.941669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.941718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.941761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.941806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.941852] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.941899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.941945] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.941990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.942055] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.942098] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.942152] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.942216] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.942267] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.942312] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 564.942351] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 564.942928] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.943104] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.943157] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.943274] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 564.943318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 564.943364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 564.943409] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 564.943475] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 564.943520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.943564] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 564.943607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.943651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 564.943694] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.943737] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 564.943744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.943787] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 564.943793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.943837] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 564.943881] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 564.943925] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 564.943968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 564.944011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 564.944056] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 564.944099] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 564.944142] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.944186] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.944230] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.944273] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 564.944335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.944388] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.944432] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.944596] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 564.944634] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 564.944924] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 564.944978] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.945020] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 564.945077] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 564.945367] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.945702] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.945747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 564.945790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.945833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.945876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.945919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 564.945963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 564.946009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 564.946051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 564.946095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 564.946143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 564.946188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.946262] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 564.946306] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.947752] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.947796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.947840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 564.948600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.948643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 564.949356] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 564.949399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 564.950503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 564.952595] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 564.953609] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 564.970569] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 564.970626] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.970796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 564.971191] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 564.971336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 564.987201] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.006100] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.006213] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.006301] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.006631] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.006676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.006720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.006764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.006808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.006852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.006900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.006943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.006987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.007031] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.007079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.007125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.007170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.007234] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.007278] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.007332] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.007394] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.007477] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.007525] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 565.007566] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 565.008116] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.008290] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.008344] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.008497] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 565.008542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 565.008587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 565.008632] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 565.008675] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 565.008721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.008768] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 565.008813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.008860] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 565.008904] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.008947] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 565.008956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.008999] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 565.009007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.009053] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.009097] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 565.009140] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 565.009183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 565.009227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.009272] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 565.009315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 565.009359] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.009402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.009472] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.009520] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.009583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.009636] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.009680] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.009831] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.009869] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.010159] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 565.010214] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.010256] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.010314] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.010560] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.010885] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.010930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.010973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.011016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.011059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.011102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.011145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.011188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.011230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.011273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.011319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.011364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.011482] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.011527] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.012945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.012988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.013032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 565.013804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.013847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.014569] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 565.014613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 565.015673] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 565.017769] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 565.018823] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.035710] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.035766] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.035936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.036329] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.036544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.052427] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.070848] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.070961] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.071050] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.071371] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.071416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.071522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.071565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.071609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.071653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.071701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.071744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.071788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.071831] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.071879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.071924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.071969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.072029] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.072072] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.072126] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.072188] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.072240] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.072284] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 565.072322] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 565.072910] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.073091] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.073125] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.073244] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 565.073288] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 565.073334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 565.073378] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 565.073420] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 565.073501] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.073544] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 565.073588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.073631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 565.073674] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.073716] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 565.073724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.073766] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 565.073772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.073816] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.073860] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 565.073903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 565.073946] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 565.073989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.074034] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 565.074077] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 565.074120] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.074164] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.074208] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.074251] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.074315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.074367] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.074411] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.074982] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.075020] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.075314] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 565.075370] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.075410] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.075576] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.075838] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.076168] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.076213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.076256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.076299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.076342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.076384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.076427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.076652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.076695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.076738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.076787] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.076831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.076906] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.076949] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.078831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.078879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.078925] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 565.079984] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 565.080032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 565.081153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 565.082586] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 565.083702] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.100620] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.100677] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.100848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.101181] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.101314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.117240] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.135862] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.135975] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.136063] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.136386] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.136431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.136558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.136606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.136649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.136692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.136742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.136785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.136829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.136872] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.136922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.136969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.137015] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.137077] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.137120] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.137175] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.137240] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.137293] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.137337] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 565.137377] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 565.137982] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.138699] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.138751] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.138875] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 565.138918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 565.138963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 565.139007] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 565.139049] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 565.139093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.139136] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 565.139179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.139222] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 565.139265] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.139307] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 565.139314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.139356] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 565.139361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.139405] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.139495] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 565.139544] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 565.139589] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 565.139634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.139681] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 565.139726] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 565.139771] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.139818] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.139863] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.139909] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.139976] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.140030] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.140074] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.140927] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.140967] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.141258] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 565.141313] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.141353] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.141409] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.142007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.142334] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.142378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.142421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.142797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.142841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.142884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.142927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.142970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.143012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.143056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.143106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.143150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.143226] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.143268] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.145011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.145057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.145102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 565.146200] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 565.146246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 565.147620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 565.149518] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 565.150640] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.167601] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.167659] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.167829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.168157] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.168304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.184156] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.201722] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.201835] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.201922] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.202242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.202288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.202331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.202374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.202416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.202502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.202551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.202601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.202645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.202689] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.202739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.202786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.202833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.202893] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.202937] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.202992] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.203056] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.203109] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.203154] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 565.203192] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 565.203790] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.204498] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.204551] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.204672] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 565.204715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 565.204760] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 565.204804] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 565.204846] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 565.204890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.204932] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 565.204975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.205018] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 565.205060] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.205102] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 565.205109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.205150] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 565.205156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.205199] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.205241] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 565.205284] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 565.205326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 565.205369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.205413] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 565.205516] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 565.205559] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.205606] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.205652] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.205696] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.205761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.205814] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.205859] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.206006] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.206045] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.206341] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 565.206398] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.206479] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.206538] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.206823] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.207153] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.207198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.207242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.207285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.207329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.207372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.207415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.207555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.207601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.207648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.207699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.207745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.207821] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.207865] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.209958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.210004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.210049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 565.210852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.210897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.211655] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 565.211703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 565.212799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 565.216311] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 565.217405] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.234340] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.234397] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.234615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.234929] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.235073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.250976] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.268781] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.268930] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.269046] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.269378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.269424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.269914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.269958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.270000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.270043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.270094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.270137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.270182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.270226] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.270275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.270321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.270366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.270855] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.270901] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.270956] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.271021] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.271077] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.271122] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 565.271162] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 565.272335] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.272767] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.272824] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.272948] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 565.272991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 565.273037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 565.273081] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 565.273123] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 565.273168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.273212] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 565.273254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.273297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 565.273340] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.273381] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 565.273390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.273432] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 565.273786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.273846] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.273891] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 565.273935] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 565.273978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 565.274021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.274067] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 565.274110] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 565.274153] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.274197] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.274240] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.274284] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.274354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.274410] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.274892] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.275057] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.275096] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.275390] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 565.275504] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.275546] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.275604] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.275874] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.276196] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.276239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.276282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.276324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.276367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.276410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.276498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.276546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.276589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.276635] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.276685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.276731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.276807] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.276851] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.278407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.278503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.278549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 565.279329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.279372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.280382] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 565.280430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 565.281792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 565.283514] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 565.284588] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.301536] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.301592] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.301762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.302125] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.302263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.318138] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.336699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.336812] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.336898] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.337228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.337273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.337316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.337361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.337404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.337500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.337549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.337594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.337638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.337684] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.337732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.337778] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.337825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.337890] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.337933] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.337988] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.338051] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.338105] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.338149] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:19 BXT-2 kernel: [ 565.338188] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:19 BXT-2 kernel: [ 565.338769] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.338948] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:19 BXT-2 kernel: [ 565.339000] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:19 BXT-2 kernel: [ 565.339116] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:19 BXT-2 kernel: [ 565.339160] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:19 BXT-2 kernel: [ 565.339206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:19 BXT-2 kernel: [ 565.339250] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:19 BXT-2 kernel: [ 565.339293] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:19 BXT-2 kernel: [ 565.339338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.339381] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:19 BXT-2 kernel: [ 565.339425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.339496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:19 BXT-2 kernel: [ 565.339543] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.339588] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:19 BXT-2 kernel: [ 565.339596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.339641] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:19 BXT-2 kernel: [ 565.339648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.339694] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:19 BXT-2 kernel: [ 565.339738] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:19 BXT-2 kernel: [ 565.339785] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:19 BXT-2 kernel: [ 565.339829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:19 BXT-2 kernel: [ 565.339872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:19 BXT-2 kernel: [ 565.339920] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:19 BXT-2 kernel: [ 565.339963] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:19 BXT-2 kernel: [ 565.340007] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.340050] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.340094] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.340137] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:19 BXT-2 kernel: [ 565.340200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.340253] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.340297] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:19 BXT-2 kernel: [ 565.340472] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:19 BXT-2 kernel: [ 565.340513] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:19 BXT-2 kernel: [ 565.340806] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:19 BXT-2 kernel: [ 565.340860] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.340902] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:19 BXT-2 kernel: [ 565.340959] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:19 BXT-2 kernel: [ 565.341242] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.341566] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:19 BXT-2 kernel: [ 565.341611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:19 BXT-2 kernel: [ 565.341654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.341697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.341741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.341784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:19 BXT-2 kernel: [ 565.341827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:19 BXT-2 kernel: [ 565.341870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:19 BXT-2 kernel: [ 565.341912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:19 BXT-2 kernel: [ 565.341955] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:19 BXT-2 kernel: [ 565.342002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:19 BXT-2 kernel: [ 565.342047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.342120] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:19 BXT-2 kernel: [ 565.342164] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:19 BXT-2 kernel: [ 565.343621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.343665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.343710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:19 BXT-2 kernel: [ 565.344501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.344547] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:19 BXT-2 kernel: [ 565.345260] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:19 BXT-2 kernel: [ 565.345304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:19 BXT-2 kernel: [ 565.346352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:19 BXT-2 kernel: [ 565.348449] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:19 BXT-2 kernel: [ 565.349530] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.366422] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.366529] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.366702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.367046] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.367192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.383058] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.401574] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.401687] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.401776] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.402099] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.402142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.402186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.402229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.402272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.402314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.402361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.402404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.402514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.402560] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.402610] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.402657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.402704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.402768] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.402811] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.402864] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.402926] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.402978] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.403021] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.403062] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.403642] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.403818] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.403872] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.403992] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.404035] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.404081] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.404125] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.404169] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.404213] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.404257] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.404300] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.404344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.404387] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.404430] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.404459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.404502] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.404508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.404552] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.404596] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.404640] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.404683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.404726] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.404771] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.404814] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.404858] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.404902] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.404945] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.404989] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.405052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.405104] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.405148] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.405300] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.405338] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.405647] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.405703] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.405744] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.405801] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.406091] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.406420] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.406513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.406557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.406599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.406642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.406685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.406728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.406771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.406814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.406857] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.406905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.406951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.407027] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.407070] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.408526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.408570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.408614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.409366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.409408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.410177] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.410221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.411308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.413400] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.414404] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.431330] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.431387] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.431617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.431958] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.432107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.447970] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.466519] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.466632] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.466718] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.467041] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.467084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.467127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.467170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.467213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.467256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.467302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.467345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.467388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.467431] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.467514] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.467565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.467612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.467675] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.467717] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.467773] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.467836] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.467887] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.467929] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.467968] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.468545] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.468718] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.468772] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.468890] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.468934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.468980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.469024] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.469067] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.469111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.469155] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.469199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.469242] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.469285] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.469328] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.469335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.469378] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.469385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.469429] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.469494] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.469538] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.469581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.469624] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.469669] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.469712] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.469755] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.469798] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.469842] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.469885] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.469947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.470000] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.470044] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.470192] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.470230] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.470546] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.470602] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.470645] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.470701] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.470995] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.471313] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.471357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.471400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.471484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.471530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.471576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.471621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.471663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.471706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.471749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.471795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.471840] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.471913] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.471956] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.473401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.473478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.473523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.474283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.474325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.475055] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.475099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.476137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.478251] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.479396] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.496378] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.496499] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.496670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.497011] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.497144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.512984] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.531489] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.531602] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.531690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.532007] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.532051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.532095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.532137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.532180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.532223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.532270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.532313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.532356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.532399] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.532523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.532570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.532616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.532683] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.532726] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.532781] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.532846] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.532900] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.532944] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.532983] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.533570] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.533750] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.533798] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.533917] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.533961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.534006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.534051] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.534093] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.534137] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.534180] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.534222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.534266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.534308] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.534350] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.534357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.534399] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.534440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.534485] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.534528] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.534572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.534615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.534658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.534705] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.534749] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.534795] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.534841] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.534887] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.534933] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.534997] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.535050] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.535096] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.535247] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.535285] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.535599] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.535657] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.535699] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.535756] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.536041] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.536363] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.536407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.536493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.536537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.536581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.536624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.536667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.536710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.536754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.536797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.536843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.536889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.536963] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.537007] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.538475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.538520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.538565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.539326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.539368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.540099] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.540143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.541185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.543304] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.544354] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.561261] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.561318] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.561547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.561903] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.562045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.577872] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.595504] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.595617] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.595705] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.596028] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.596072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.596115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.596159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.596202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.596244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.596291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.596334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.596377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.596421] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.596500] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.596550] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.596598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.596666] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.596709] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.596765] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.596829] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.596880] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.596923] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.596961] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.597534] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.597711] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.597766] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.597883] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.597927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.597971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.598015] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.598058] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.598102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.598146] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.598190] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.598234] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.598277] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.598319] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.598326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.598369] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.598375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.598419] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.598492] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.598538] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.598583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.598628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.598677] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.598722] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.598768] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.598814] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.598860] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.598906] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.598971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.599024] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.599070] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.599219] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.599256] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.599568] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.599624] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.599665] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.599720] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.600007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.600331] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.600375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.600419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.600502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.600546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.600592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.600638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.600685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.600729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.600775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.600821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.600866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.600940] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.600984] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.602393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.602465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.602510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.603265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.603308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.604033] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.604077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.605119] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.607211] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.608234] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.625140] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.625196] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.625370] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.625790] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.625938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.641769] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.660279] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.660392] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.660533] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.660861] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.660907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.660950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.660994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.661037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.661081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.661129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.661173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.661217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.661261] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.661310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.661356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.661401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.661501] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.661545] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.661600] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.661663] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.661715] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.661760] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.661799] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.662348] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.662556] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.662613] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.662732] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.662776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.662821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.662865] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.662908] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.662953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.662997] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.663041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.663085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.663128] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.663171] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.663178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.663220] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.663226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.663270] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.663314] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.663357] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.663400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.663479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.663524] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.663566] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.663610] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.663654] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.663698] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.663741] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.663804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.663858] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.663902] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.664056] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.664094] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.664384] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.664457] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.664500] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.664557] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.664846] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.665181] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.665226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.665269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.665312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.665355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.665398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.665486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.665533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.665579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.665625] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.665673] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.665718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.665792] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.665835] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.667277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.667321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.667365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.668136] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.668179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.668900] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.668943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.669981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.672076] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.673105] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.690028] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.690085] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.690255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.690656] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.690804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.706630] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.725137] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.725250] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.725338] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.725731] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.725777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.725820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.725863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.725906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.725949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.725997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.726040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.726083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.726126] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.726174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.726219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.726264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.726330] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.726372] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.726426] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.726532] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.726587] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.726630] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.726673] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.727221] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.727393] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.727478] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.727598] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.727643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.727688] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.727733] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.727777] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.727821] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.727864] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.727908] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.727951] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.727995] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.728038] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.728045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.728087] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.728093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.728137] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.728181] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.728225] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.728268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.728311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.728356] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.728400] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.728470] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.728514] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.728557] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.728600] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.728664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.728717] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.728761] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.728911] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.728949] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.729239] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.729294] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.729336] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.729392] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.729709] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.730030] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.730075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.730118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.730162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.730205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.730248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.730291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.730334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.730377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.730420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.730512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.730561] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.730635] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.730679] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.732116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.732160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.732205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.733006] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.733050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.733772] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.733816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.734849] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.736942] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.737978] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.754909] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.754966] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.755135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.755573] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.755721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.771518] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.789846] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.789959] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.790047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.790371] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.790415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.790521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.790568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.790611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.790655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.790703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.790747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.790791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.790834] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.790884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.790932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.790979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.791045] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.791088] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.791142] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.791205] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.791258] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.791302] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.791341] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.791919] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.792094] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.792148] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.792267] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.792310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.792355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.792399] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.792481] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.792527] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.792575] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.792619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.792663] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.792706] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.792749] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.792756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.792799] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.792805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.792849] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.792892] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.792936] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.792979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.793023] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.793068] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.793111] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.793154] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.793198] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.793241] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.793285] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.793350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.793403] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.793471] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.793625] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.793663] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.793954] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.794009] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.794051] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.794108] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.794396] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.794759] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.794804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.794847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.794890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.794933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.794976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.795019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.795062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.795105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.795148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.795194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.795239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.795313] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.795356] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.796794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.796838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.796883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.797651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.797694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.798407] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.798477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.799515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.801611] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.802670] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.819607] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.819664] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.819835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.820184] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.820327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.836212] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.854762] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.854874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.854961] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.855314] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.855358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.855401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.855835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.855879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.855922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.855972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.856015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.856058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.856101] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.856149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.856194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.856239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.856306] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.856350] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.856403] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.857011] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.857068] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.857111] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.857150] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.858316] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.858592] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.858650] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.858775] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.858819] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.858863] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.858908] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.858950] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.858994] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.859037] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.859081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.859124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.859167] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.859209] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.859215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.859257] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.859263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.859306] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.859349] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.859392] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.860198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.860241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.860286] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.860328] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.860372] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.860415] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.860731] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.860774] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.860847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.860901] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.860944] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.861095] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.861133] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.861422] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.862110] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.862152] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.862208] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.862682] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.863006] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.863050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.863093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.863136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.863179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.863222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.863265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.863308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.863351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.863394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.863918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.863963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.864039] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.864082] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.865723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.865767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.865812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.866718] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.866763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.867699] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.867744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.868869] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.870965] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.872015] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.888916] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.888972] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.889142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.889760] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.889922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.905528] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.923705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.923818] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.923905] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.924223] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.924269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.924314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.924357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.924400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.924959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.925010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.925053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.925096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.925139] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.925186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.925232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.925277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.925345] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.925658] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.925714] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.925781] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.925837] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.925881] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.925921] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.926509] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.926688] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.926726] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.926843] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.926887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.926932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.926976] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.927018] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.927062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.927105] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.927148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.927191] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.927233] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.927276] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.927282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.927324] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.927330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.927373] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.927415] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.927491] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.927540] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.927586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.927633] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.927678] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.927725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.927770] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.927816] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.927862] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.927926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.927979] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.928025] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.928170] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.928208] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.928521] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.928576] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.928619] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.928675] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.928966] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.929292] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.929336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.929380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.929424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.929501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.929544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.929588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.929632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.929675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.929719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.929768] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.929813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.929889] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.929933] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.931377] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.931420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.931504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.932259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.932302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.933032] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.933075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.934110] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 565.936201] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 565.937226] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.954136] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.954193] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.954363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.954768] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.954916] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.970775] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.989282] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.989395] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.989547] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.989868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.989913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.989957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.990000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.990044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.990088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.990135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.990179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.990223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.990266] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.990315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.990361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.990406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.990503] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.990546] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.990601] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.990664] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.990716] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.990760] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 565.990799] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 565.991346] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.991559] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 565.991614] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 565.991732] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 565.991776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 565.991822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 565.991867] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 565.991910] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 565.991954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.991999] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 565.992043] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.992087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 565.992130] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.992172] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 565.992180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.992223] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 565.992229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.992274] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 565.992317] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 565.992361] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 565.992404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 565.992479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 565.992524] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 565.992566] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 565.992610] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.992654] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.992697] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.992741] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 565.992807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.992859] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.992904] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 565.993054] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 565.993092] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 565.993383] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 565.993464] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.993506] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 565.993562] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 565.993879] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.994200] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 565.994245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 565.994289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.994332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.994376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.994420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 565.994502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 565.994546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 565.994590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 565.994634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 565.994681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 565.994726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.994803] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 565.994847] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 565.996293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.996336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.996380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 565.997190] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.997233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 565.997995] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 565.998039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 565.999075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 566.001169] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 566.002173] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.019104] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.019161] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.019332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.019740] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.019887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.035707] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.054215] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.054328] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.054417] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.054795] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.054840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.054884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.054927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.054971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.055015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.055064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.055108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.055151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.055195] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.055243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.055290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.055336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.055403] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.055473] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.055528] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.055593] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.055647] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.055692] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 566.055732] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 566.056280] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.056484] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.056540] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.056659] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 566.056704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 566.056750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 566.056797] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 566.056839] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 566.056885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.056930] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 566.056974] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.057019] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 566.057063] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.057106] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 566.057114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.057157] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 566.057164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.057208] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.057252] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 566.057296] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 566.057338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 566.057381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.057427] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 566.057498] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 566.057542] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.057586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.057629] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.057673] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.057737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.057792] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.057840] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.057993] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.058032] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.058322] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 566.058377] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.058419] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.058504] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.059066] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.059386] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.059430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.059759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.059803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.059846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.059889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.059932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.059975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.060019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.060062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.060110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.060156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.060230] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.060273] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.061974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.062019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.062064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 566.062992] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 566.063038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 566.064111] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 566.066215] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 566.067258] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.084152] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.084209] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.084380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.085081] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.085231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.100781] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.119292] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.119405] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.119834] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.120154] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.120198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.120242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.120285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.120328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.120371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.120419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.120744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.120788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.120832] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.120883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.120931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.120977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.121038] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.121082] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.121137] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.121201] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.121254] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.121298] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 566.121338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 566.122535] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.122725] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.122761] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.122882] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 566.122925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 566.122970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 566.123014] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 566.123056] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 566.123100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.123143] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 566.123186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.123230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 566.123272] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.123314] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 566.123320] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.123363] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 566.123368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.123412] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.123917] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 566.123961] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 566.124005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 566.124048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.124094] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 566.124137] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 566.124181] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.124225] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.124268] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.124312] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.124380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.124435] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.124779] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.124933] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.124971] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.125263] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 566.125318] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.125358] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.125414] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.125987] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.126310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.126354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.126398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.126780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.126824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.126868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.126911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.126954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.126997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.127040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.127088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.127133] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.127208] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.127251] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.129036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.129082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.129127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 566.129988] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 566.130033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 566.131085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 566.133191] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 566.134229] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.151147] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.151204] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.151374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.151875] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.152019] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.167760] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.186272] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.186385] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.186543] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.186867] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.186912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.186955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.186998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.187041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.187084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.187131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.187174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.187217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.187260] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.187307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.187353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.187398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.187496] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.187541] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.187596] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.187660] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.187713] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.187757] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 566.187796] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 566.188344] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.188554] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.188607] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.188726] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 566.188770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 566.188814] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 566.188858] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 566.188900] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 566.188944] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.188988] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 566.189030] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.189074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 566.189116] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.189158] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 566.189165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.189206] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 566.189212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.189255] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.189298] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 566.189341] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 566.189383] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 566.189426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.189503] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 566.189549] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 566.189596] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.189643] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.189689] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.189735] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.189799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.189852] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.189898] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.190048] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.190085] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.190375] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 566.190457] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.190501] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.190559] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.190844] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.191164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.191209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.191253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.191296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.191340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.191383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.191427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.191510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.191556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.191602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.191653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.191699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.191774] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.191817] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.193259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.193303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.193348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 566.194124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.194167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.194890] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 566.194933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 566.195968] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 566.198057] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 566.199115] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.216029] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.216086] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.216256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.216661] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.216809] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.232654] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.251019] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.251134] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.251223] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.251543] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.251588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.251635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.251679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.251722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.251765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.251814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.251857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.251901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.251944] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.251992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.252038] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.252083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.252146] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.252190] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.252245] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.252309] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.252362] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.252406] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 566.252487] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 566.253036] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.253214] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.253266] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.253384] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 566.253428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 566.253521] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 566.253569] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 566.253611] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 566.253656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.253699] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 566.253743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.253787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 566.253830] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.253872] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 566.253879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.253922] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 566.253928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.253973] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.254016] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 566.254060] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 566.254102] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 566.254146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.254191] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 566.254234] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 566.254277] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.254321] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.254364] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.254407] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.254517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.254570] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.254614] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.254764] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.254803] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.255093] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 566.255148] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.255188] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.255244] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.255578] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.255902] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.255947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.255991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.256034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.256077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.256120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.256163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.256206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.256249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.256292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.256339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.256384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.256528] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.256572] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.258006] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.258050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.258094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 566.258900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.258942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.259718] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 566.259765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 566.260828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 566.262926] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 566.263966] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.280865] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.280921] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.281091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.281509] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.281661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.297534] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.316041] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.316153] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.316241] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.316567] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.316612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.316657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.316701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.316744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.316788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.316837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.316881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.316925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.316968] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.317016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.317064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.317110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.317177] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.317221] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.317275] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.317338] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.317391] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.317464] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:20 BXT-2 kernel: [ 566.317506] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:20 BXT-2 kernel: [ 566.318056] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.318235] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.318293] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.318407] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:20 BXT-2 kernel: [ 566.318488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:20 BXT-2 kernel: [ 566.318534] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:20 BXT-2 kernel: [ 566.318579] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:20 BXT-2 kernel: [ 566.318625] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:20 BXT-2 kernel: [ 566.318669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.318713] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:20 BXT-2 kernel: [ 566.318757] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.318800] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:20 BXT-2 kernel: [ 566.318843] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.318886] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:20 BXT-2 kernel: [ 566.318893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.318936] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:20 BXT-2 kernel: [ 566.318943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.318987] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:20 BXT-2 kernel: [ 566.319030] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:20 BXT-2 kernel: [ 566.319074] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:20 BXT-2 kernel: [ 566.319118] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:20 BXT-2 kernel: [ 566.319161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:20 BXT-2 kernel: [ 566.319206] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:20 BXT-2 kernel: [ 566.319249] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:20 BXT-2 kernel: [ 566.319293] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.319337] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.319380] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.319424] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:20 BXT-2 kernel: [ 566.319508] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.319561] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.319605] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.319757] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:20 BXT-2 kernel: [ 566.319795] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:20 BXT-2 kernel: [ 566.320085] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:20 BXT-2 kernel: [ 566.320139] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.320182] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:20 BXT-2 kernel: [ 566.320239] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:20 BXT-2 kernel: [ 566.320523] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.320842] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:20 BXT-2 kernel: [ 566.320887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:20 BXT-2 kernel: [ 566.320931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.320975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.321018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.321062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:20 BXT-2 kernel: [ 566.321105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:20 BXT-2 kernel: [ 566.321148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:20 BXT-2 kernel: [ 566.321191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:20 BXT-2 kernel: [ 566.321235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:20 BXT-2 kernel: [ 566.321282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:20 BXT-2 kernel: [ 566.321327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.321401] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:20 BXT-2 kernel: [ 566.321471] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.323537] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.323583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.323629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:20 BXT-2 kernel: [ 566.324381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.324423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:20 BXT-2 kernel: [ 566.325531] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:20 BXT-2 kernel: [ 566.325576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:20 BXT-2 kernel: [ 566.326637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:20 BXT-2 kernel: [ 566.328740] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:20 BXT-2 kernel: [ 566.329823] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:20 BXT-2 kernel: [ 566.346739] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:20 BXT-2 kernel: [ 566.346795] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.346966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:20 BXT-2 kernel: [ 566.347316] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:20 BXT-2 kernel: [ 566.347444] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.363385] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.382119] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.382232] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.382320] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.382847] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.382893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.382936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.382979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.383022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.383065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.383113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.383156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.383199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.383243] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.383290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.383336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.383380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.383975] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.384020] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.384074] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.384141] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.384196] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.384239] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.384278] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.385465] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.385649] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.385701] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.385824] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.385868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.385913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.385957] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.385999] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.386043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.386086] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.386129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.386172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.386214] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.386256] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.386262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.386304] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.386310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.386353] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.386396] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.387217] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.387261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.387303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.387348] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.387391] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.387674] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.387718] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.387761] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.387804] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.387878] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.387931] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.387975] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.388126] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.388164] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.388864] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.389172] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.389213] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.389268] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.389804] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.390127] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.390171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.390214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.390257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.390300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.390343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.390386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.390429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.390905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.390949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.390998] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.391043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.391118] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.391161] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.392793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.392837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.392882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.393756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.393800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.394646] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.394691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.395857] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.397956] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.398976] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.415868] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.415924] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.416093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.416658] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.416815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.432563] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.451070] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.451182] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.451270] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.451919] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.451966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.452010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.452052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.452095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.452138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.452187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.452230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.452272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.452316] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.452363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.452408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.452975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.453043] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.453086] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.453140] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.453202] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.453256] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.453299] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.453337] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.454529] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.454707] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.454762] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.454882] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.454925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.454970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.455014] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.455056] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.455100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.455144] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.455186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.455230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.455272] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.455314] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.455321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.455362] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.455368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.455411] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.456192] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.456236] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.456279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.456321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.456367] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.456409] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.456722] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.456766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.456809] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.456852] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.456925] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.456979] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.457022] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.457193] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.457231] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.457943] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.458251] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.458291] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.458346] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.458864] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.459189] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.459235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.459278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.459321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.459364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.459407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.459810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.459854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.459897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.459940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.459988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.460033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.460108] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.460151] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.461873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.461918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.461962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.462917] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.462963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.464048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.466151] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.467201] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.484122] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.484180] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.484351] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.484926] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.485074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.500736] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.519236] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.519349] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.519514] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.519838] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.519883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.519926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.519969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.520012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.520055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.520103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.520146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.520189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.520232] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.520279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.520325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.520369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.520463] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.520508] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.520565] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.520629] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.520682] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.520727] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.520766] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.521313] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.521522] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.521580] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.521702] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.521746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.521790] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.521834] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.521876] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.521920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.521963] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.522006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.522049] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.522092] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.522134] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.522140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.522184] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.522189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.522233] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.522276] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.522318] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.522361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.522403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.522482] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.522529] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.522577] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.522622] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.522668] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.522714] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.522779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.522832] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.522878] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.523028] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.523066] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.523357] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.523411] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.523475] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.523533] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.523820] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.524141] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.524186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.524230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.524273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.524317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.524360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.524404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.524478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.524522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.524566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.524613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.524659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.524734] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.524778] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.526216] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.526259] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.526303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.527074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.527117] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.527860] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.527904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.532145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.533490] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.534512] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.551425] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.551506] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.551678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.551995] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.552123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.568052] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.585755] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.585868] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.585956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.586276] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.586321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.586364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.586407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.586516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.586564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.586612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.586655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.586699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.586743] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.586792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.586837] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.586883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.586948] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.586992] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.587047] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.587111] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.587164] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.587208] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.587248] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.587832] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.588011] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.588061] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.588177] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.588221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.588266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.588310] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.588352] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.588396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.588474] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.588518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.588563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.588606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.588649] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.588656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.588698] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.588705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.588749] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.588792] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.588836] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.588879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.588922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.588967] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.589010] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.589053] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.589097] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.589140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.589184] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.589247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.589301] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.589345] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.589525] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.589564] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.589853] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.589908] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.589950] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.590007] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.590299] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.590630] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.590676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.590725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.590770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.590816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.590863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.590909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.590955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.591001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.591047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.591097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.591144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.591220] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.591265] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.592716] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.592760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.592804] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.593570] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.593613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.594329] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.594373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.595419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.597532] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.598597] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.615532] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.615588] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.615758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.616103] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.616244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.632145] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.650694] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.650807] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.650895] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.651220] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.651264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.651307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.651350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.651393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.651494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.651544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.651590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.651636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.651679] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.651729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.651775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.651820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.651885] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.651927] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.651981] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.652045] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.652096] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.652140] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.652179] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.652759] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.652936] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.652990] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.653109] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.653156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.653202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.653248] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.653294] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.653340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.653386] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.653431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.653502] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.653547] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.653591] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.653598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.653640] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.653646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.653689] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.653732] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.653775] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.653818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.653860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.653907] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.653949] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.653993] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.654036] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.654080] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.654124] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.654188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.654241] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.654286] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.654470] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.654508] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.654798] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.654853] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.654896] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.654953] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.655245] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.655572] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.655620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.655665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.655711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.655758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.655803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.655849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.655894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.655940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.655985] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.656034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.656081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.656156] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.656199] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.657710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.657754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.657799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.658562] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.658605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.659319] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.659362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.660405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.662513] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.663582] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.680560] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.680616] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.680785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.681125] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.681393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.697143] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.715704] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.715817] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.715905] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.716229] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.716273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.716317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.716361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.716404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.716503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.716555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.716601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.716647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.716693] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.716743] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.716791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.716839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.716905] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.716948] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.717002] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.717066] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.717119] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.717163] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.717202] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.717790] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.717967] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.718023] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.718142] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.718185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.718230] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.718274] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.718316] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.718360] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.718403] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.718481] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.718526] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.718571] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.718616] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.718626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.718669] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.718678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.718724] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.718769] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.718812] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.718855] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.718898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.718944] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.718987] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.719030] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.719074] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.719117] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.719161] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.719224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.719277] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.719321] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.719497] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.719537] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.719830] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.719885] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.719927] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.719983] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.720272] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.720614] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.720659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.720702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.720745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.720788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.720831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.720874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.720917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.720959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.721004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.721051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.721096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.721169] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.721212] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.722701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.722745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.722790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.723555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.723598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.724312] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.724356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.725396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.727618] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.728666] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.745582] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.745638] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.745809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.746158] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.746305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.762224] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.780898] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.781011] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.781101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.781422] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.781620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.781664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.781708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.781752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.781795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.781844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.781888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.781931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.781975] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.782024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.782072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.782117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.782183] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.782227] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.782282] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.782346] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.782399] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.782468] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.782509] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.783056] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.783233] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.783284] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.783402] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.783588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.783634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.783679] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.783722] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.783766] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.783811] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.783855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.783899] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.783942] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.783985] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.783993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.784035] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.784042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.784086] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.784130] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.784173] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.784217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.784259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.784305] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.784348] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.784391] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.784459] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.784503] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.784546] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.784613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.784668] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.784712] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.784868] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.784907] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.785197] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.785252] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.785294] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.785351] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.785670] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.785991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.786034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.786078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.786124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.786170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.786216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.786261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.786307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.786352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.786398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.786514] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.786560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.786636] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.786680] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.788130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.788175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.788219] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.789048] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.789090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.789825] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.789869] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.790917] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.793012] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.794058] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.811041] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.811141] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.811365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.811884] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.812125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.827606] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.846117] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.846230] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.846319] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.846644] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.846689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.846733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.846777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.846820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.846864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.846911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.846955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.846998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.847042] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.847090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.847136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.847182] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.847248] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.847291] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.847345] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.847408] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.847485] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.847528] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.847572] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.848121] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.848301] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.848355] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.848516] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.848561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.848606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.848651] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.848694] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.848738] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.848782] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.848825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.848869] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.848912] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.848955] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.848962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.849005] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.849011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.849055] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.849098] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.849142] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.849185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.849228] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.849274] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.849317] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.849360] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.849404] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.849475] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.849523] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.849587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.849642] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.849687] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.849837] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.849875] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.850165] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.850220] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.850262] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.850319] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.850649] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.850975] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.851019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.851062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.851105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.851148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.851191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.851234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.851276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.851319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.851362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.851409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.851487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.851563] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.851607] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.853015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.853059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.853103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.853883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.853927] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.854648] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.854692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.855730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.857820] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.858846] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.875756] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.875812] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.875983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.876328] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.877128] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.892376] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.910939] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.911051] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.911138] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.911710] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.911756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.911800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.911843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.911886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.911929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.911977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.912020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.912063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.912106] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.912155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.912200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.912245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.912305] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.912348] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.912401] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.913107] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.913165] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.913208] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.913246] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.914413] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.914614] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.914667] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.914787] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.914830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.914874] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.914918] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.914960] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.915003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.915046] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.915089] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.915132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.915174] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.915216] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.915222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.915264] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.915269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.915312] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.915355] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.915398] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.916217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.916260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.916305] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.916347] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.916427] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.916754] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.916797] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.916841] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.916910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.916968] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.917012] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.917162] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.917200] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.917887] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.918194] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.918237] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.918293] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.918700] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.919028] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.919072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.919115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.919158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.919201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.919244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.919287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.919329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.919372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.919415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.919974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.920018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.920094] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.920137] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.922148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.922194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.922239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.923513] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.923561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.924645] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.926745] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.927837] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.944739] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.944797] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.944968] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.945309] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.945724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.961364] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.979778] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.979891] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.979979] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.980298] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.980342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.980386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.980429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.980891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.980935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.980984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.981026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.981069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.981112] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.981160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.981205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.981249] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.981311] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.981354] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.981408] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.982084] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.982142] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.982185] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 566.982224] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 566.983395] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.983601] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 566.983637] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 566.983759] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 566.983802] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 566.983847] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 566.983891] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 566.983933] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 566.983977] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.984020] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 566.984063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.984106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 566.984148] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.984190] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 566.984196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.984238] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 566.984244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.984287] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 566.984330] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 566.984373] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 566.984415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 566.985289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 566.985334] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 566.985377] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 566.985420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.985678] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.985721] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.985764] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 566.985833] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.985886] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.985929] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 566.986075] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 566.986113] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 566.986401] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 566.987089] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.987131] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 566.987187] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 566.987745] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.988075] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 566.988120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 566.988163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.988206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.988249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.988292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 566.988335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 566.988378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 566.988421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 566.988915] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 566.988964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 566.989009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.989083] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 566.989126] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 566.990762] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.990807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.990852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 566.991770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.991814] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 566.992637] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 566.992682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 566.993839] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 566.995953] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 566.997007] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.013927] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.013984] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.014154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.014773] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.014923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.030544] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.049061] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.049174] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.049261] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.049846] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.049892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.049935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.049978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.050021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.050064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.050111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.050154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.050197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.050240] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.050287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.050332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.050377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.050972] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.051018] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.051072] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.051135] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.051189] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.051232] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 567.051271] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 567.052476] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.053154] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.053203] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.053325] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 567.053368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 567.053412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 567.053787] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 567.053829] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 567.053874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.053918] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 567.053961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.054004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 567.054046] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.054088] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 567.054095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.054137] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 567.054143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.054186] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.054229] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 567.054271] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 567.054314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 567.054356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.054401] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 567.055103] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 567.055146] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.055189] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.055232] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.055275] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.055345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.055399] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.055820] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.055989] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.056027] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.056316] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 567.056370] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.056411] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.056809] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.057060] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.057382] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.057426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.057525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.057570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.057613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.057656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.057700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.057744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.057787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.057831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.057879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.057924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.057999] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.058042] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.059526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.059569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.059614] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 567.060368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.060411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.061170] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 567.061213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 567.062290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 567.064383] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 567.065425] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.082399] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.082479] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.082648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.082984] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.083125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.098975] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.117488] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.117600] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.117688] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.118010] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.118054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.118098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.118141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.118184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.118226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.118273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.118316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.118358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.118402] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.118500] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.118550] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.118597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.118661] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.118704] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.118760] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.118829] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.118885] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.118929] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 567.118968] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 567.119549] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.119733] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.119788] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.119906] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 567.119950] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 567.119996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 567.120041] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 567.120084] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 567.120129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.120172] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 567.120215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.120259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 567.120303] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.120346] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 567.120353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.120396] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 567.120457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.120505] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.120549] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 567.120592] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 567.120636] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 567.120679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.120725] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 567.120768] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 567.120811] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.120855] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.120898] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.120942] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.121006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.121059] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.121103] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.121254] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.121293] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.121606] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 567.121662] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.121706] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.121763] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.122249] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.122585] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.122631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.122675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.122718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.122761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.122805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.122848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.122892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.122936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.122984] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.123032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.123079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.123154] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.123199] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.124782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.124826] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.124871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 567.125641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.125685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.126395] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 567.126561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 567.127615] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 567.129710] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 567.130755] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.147654] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.147711] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.147882] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.148221] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.148366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.164289] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.182736] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.182849] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.182937] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.183254] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.183298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.183341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.183384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.183427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.183655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.183704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.183747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.183791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.183835] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.183884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.183932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.183977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.184037] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.184081] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.184136] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.184199] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.184253] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.184297] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 567.184336] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 567.185521] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.185696] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.185731] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.185850] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 567.185894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 567.185939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 567.185982] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 567.186025] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 567.186068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.186112] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 567.186154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.186198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 567.186240] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.186282] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 567.186289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.186330] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 567.186336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.186379] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.186422] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 567.186659] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 567.186703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 567.186746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.186791] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 567.186834] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 567.186878] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.186922] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.186965] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.187009] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.187075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.187127] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.187172] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.187314] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.187352] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.187787] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 567.188264] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.188305] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.188360] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.188742] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.189064] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.189108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.189151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.189194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.189236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.189279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.189322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.189365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.189408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.189593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.189642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.189687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.189762] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.189806] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.191225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.191269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.191314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 567.192098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.192141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.192948] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 567.192993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 567.194043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 567.196146] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 567.197180] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.214085] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.214141] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.214311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.214956] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.215100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.230722] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.249234] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.249347] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.249775] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.250098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.250143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.250186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.250229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.250272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.250315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.250363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.250406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.250776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.250821] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.250872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.250920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.250966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.251026] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.251069] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.251124] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.251188] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.251240] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.251284] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 567.251324] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 567.252514] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.252705] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.252754] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.252875] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 567.252918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 567.252963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 567.253008] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 567.253050] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 567.253094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.253138] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 567.253181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.253225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 567.253268] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.253311] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 567.253317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.253359] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 567.253365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.253409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.253818] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 567.253863] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 567.253909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 567.253951] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.253998] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 567.254042] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 567.254087] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.254132] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.254176] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.254221] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.254289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.254343] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.254388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.254918] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.254959] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.255252] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 567.255308] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.255352] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.255408] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.255997] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.256322] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.256367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.256410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.256732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.256777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.256821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.256864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.256908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.256952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.256996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.257046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.257092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.257166] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.257210] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.258936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.258981] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.259026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 567.260018] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 567.260064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 567.261127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 567.263230] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 567.264250] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.281171] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.281227] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.281398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.282149] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.282294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.297818] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.316330] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.316795] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.316888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.317213] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.317257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.317301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.317344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.317387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.317430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.317775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.317819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.317862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.317907] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.317956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.318004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.318050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.318110] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.318154] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.318210] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.318274] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.318328] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.318372] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:21 BXT-2 kernel: [ 567.318411] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:21 BXT-2 kernel: [ 567.319275] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.319713] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.319768] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.319896] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:21 BXT-2 kernel: [ 567.319939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:21 BXT-2 kernel: [ 567.319984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:21 BXT-2 kernel: [ 567.320028] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:21 BXT-2 kernel: [ 567.320070] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:21 BXT-2 kernel: [ 567.320114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.320157] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:21 BXT-2 kernel: [ 567.320200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.320244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:21 BXT-2 kernel: [ 567.320286] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.320328] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:21 BXT-2 kernel: [ 567.320334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.320376] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:21 BXT-2 kernel: [ 567.320382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.320425] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:21 BXT-2 kernel: [ 567.320947] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:21 BXT-2 kernel: [ 567.320991] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:21 BXT-2 kernel: [ 567.321034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:21 BXT-2 kernel: [ 567.321077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:21 BXT-2 kernel: [ 567.321123] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:21 BXT-2 kernel: [ 567.321166] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:21 BXT-2 kernel: [ 567.321210] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.321254] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.321298] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.321341] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:21 BXT-2 kernel: [ 567.321411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.321780] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.321824] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.321979] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:21 BXT-2 kernel: [ 567.322018] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:21 BXT-2 kernel: [ 567.322307] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:21 BXT-2 kernel: [ 567.322362] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.322402] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:21 BXT-2 kernel: [ 567.322879] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:21 BXT-2 kernel: [ 567.323141] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.323749] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:21 BXT-2 kernel: [ 567.323796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:21 BXT-2 kernel: [ 567.323839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.323883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.323926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.323969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:21 BXT-2 kernel: [ 567.324012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:21 BXT-2 kernel: [ 567.324055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:21 BXT-2 kernel: [ 567.324098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:21 BXT-2 kernel: [ 567.324141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:21 BXT-2 kernel: [ 567.324189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:21 BXT-2 kernel: [ 567.324234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.324308] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:21 BXT-2 kernel: [ 567.324351] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.326158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.326203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:21 BXT-2 kernel: [ 567.326248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:21 BXT-2 kernel: [ 567.327281] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:21 BXT-2 kernel: [ 567.327327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:21 BXT-2 kernel: [ 567.328396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:21 BXT-2 kernel: [ 567.330530] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:21 BXT-2 kernel: [ 567.331562] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:21 BXT-2 kernel: [ 567.348528] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:21 BXT-2 kernel: [ 567.348584] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.348755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:21 BXT-2 kernel: [ 567.349095] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:21 BXT-2 kernel: [ 567.349238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.365119] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.383191] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.383304] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.383392] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.383877] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.383922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.383966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.384009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.384052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.384094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.384142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.384185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.384228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.384271] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.384318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.384364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.384408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.384622] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.384664] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.384718] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.384781] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.384833] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.384875] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.384914] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.385565] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.386193] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.386246] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.386365] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.386409] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.386580] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.386624] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.386666] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.386710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.386753] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.386797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.386841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.386884] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.386926] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.386934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.386976] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.386982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.387026] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.387070] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.387113] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.387156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.387199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.387244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.387287] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.387330] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.387374] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.387417] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.387598] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.387661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.387712] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.387756] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.387898] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.387936] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.388226] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.388281] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.388322] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.388379] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.388780] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.389098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.389142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.389186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.389228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.389271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.389313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.389356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.389399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.389568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.389611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.389657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.389703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.389780] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.389824] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.391242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.391285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.391329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.392109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.392152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.392932] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.392976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.394030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.396123] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.397190] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.414122] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.414179] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.414350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.414835] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.414968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.430751] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.449247] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.449360] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.449618] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.449946] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.449990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.450033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.450076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.450119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.450162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.450209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.450252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.450295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.450338] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.450386] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.450431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.450598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.450657] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.450700] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.450753] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.450815] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.450868] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.450912] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.450951] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.451596] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.452227] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.452276] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.452397] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.452569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.452614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.452657] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.452700] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.452745] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.452789] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.452833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.452877] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.452920] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.452962] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.452970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.453012] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.453018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.453062] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.453105] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.453149] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.453192] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.453235] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.453281] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.453324] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.453367] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.453410] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.453598] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.453641] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.453704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.453757] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.453800] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.453947] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.453985] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.454275] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.454330] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.454373] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.454591] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.454846] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.455168] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.455213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.455257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.455300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.455343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.455385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.455429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.455607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.455650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.455693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.455740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.455785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.455860] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.455904] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.457319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.457363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.457408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.457692] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x10001918, pins 0x00000040 >May 24 03:31:22 BXT-2 kernel: [ 567.457737] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short >May 24 03:31:22 BXT-2 kernel: [ 567.457831] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short >May 24 03:31:22 BXT-2 kernel: [ 567.458412] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:22 BXT-2 kernel: [ 567.458839] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.458884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.460602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.462706] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.463762] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.480691] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.480748] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.480919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.481340] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.481752] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.497378] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.516014] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.516127] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.516215] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.516615] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.516660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.516704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.516747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.516790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.516834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.516883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.516926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.516970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.517014] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.517062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.517108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.517153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.517214] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.517258] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.517313] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.517376] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.517555] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.517650] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.517689] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.518236] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.518517] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.518568] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.518689] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.518733] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.518777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.518821] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.518863] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.518908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.518951] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.518993] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.519036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.519079] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.519121] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.519127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.519169] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.519175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.519218] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.519260] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.519303] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.519346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.519388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.519433] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.519661] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.519705] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.519748] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.519791] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.519834] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.519898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.519951] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.519995] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.520139] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.520178] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.520584] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.521089] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.521131] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.521189] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.521590] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.521915] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.521959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.522003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.522045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.522089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.522132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.522175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.522217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.522260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.522303] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.522349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.522394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.522622] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.522666] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.524089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.524133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.524177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.524974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.525018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.525775] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.525820] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.526932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.529037] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.530095] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.547022] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.547080] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.547250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.547795] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.547944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.563707] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.582229] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.582341] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.582430] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.582914] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.582959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.583003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.583045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.583088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.583131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.583178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.583221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.583389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.583432] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.583597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.583642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.583687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.583748] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.583791] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.583846] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.583910] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.583963] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.584007] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.584046] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.585219] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.585514] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.585568] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.585691] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.585735] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.585781] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.585825] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.585868] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.585913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.585956] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.586000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.586044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.586086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.586129] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.586136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.586179] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.586185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.586229] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.586272] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.586316] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.586359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.586402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.586601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.586643] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.586686] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.586729] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.586772] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.586815] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.586881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.586935] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.586978] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.587121] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.587159] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.587566] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.588071] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.588112] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.588168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.588560] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.588879] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.588923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.588966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.589008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.589051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.589094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.589136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.589179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.589222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.589264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.589310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.589355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.589428] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.589613] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.591030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.591074] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.591118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.591947] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.591991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.593036] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.595148] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.596252] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.613168] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.613224] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.613394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.613925] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.614051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.629877] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.648389] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.648554] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.648644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.648965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.649009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.649052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.649095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.649138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.649181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.649228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.649271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.649314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.649357] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.649404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.649644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.649690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.649748] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.649791] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.649844] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.649908] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.649961] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.650005] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.650044] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.651208] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.651387] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.651565] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.651690] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.651734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.651780] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.651824] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.651867] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.651912] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.651956] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.651999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.652043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.652086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.652129] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.652136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.652178] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.652185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.652228] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.652272] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.652315] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.652358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.652401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.652622] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.652664] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.652707] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.652750] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.652793] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.652835] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.652902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.652955] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.652999] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.653143] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.653181] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.653592] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.654092] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.654133] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.654189] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.654592] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.654917] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.654961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.655005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.655048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.655090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.655133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.655176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.655219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.655262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.655305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.655351] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.655396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.655595] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.655639] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.657058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.657102] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.657147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.657953] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.657997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.659047] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.661150] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.662190] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.679104] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.679161] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.679333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.679874] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.680018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.695798] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.714288] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.714402] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.714641] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.714963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.715007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.715051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.715093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.715136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.715179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.715226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.715269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.715311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.715354] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.715401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.715584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.715629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.715689] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.715731] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.715785] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.715848] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.715901] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.715945] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.715984] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.717151] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.717332] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.717382] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.717613] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.717657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.717703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.717747] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.717790] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.717834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.717878] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.717921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.717965] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.718008] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.718051] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.718059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.718101] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.718107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.718152] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.718195] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.718239] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.718281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.718323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.718368] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.718411] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.718629] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.718673] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.718715] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.718758] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.718823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.718875] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.718919] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.719064] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.719102] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.719392] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.720022] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.720063] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.720118] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.720405] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.720839] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.720884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.720927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.720969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.721012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.721055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.721097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.721140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.721183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.721226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.721272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.721317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.721390] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.721549] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.723019] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.723065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.723110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.723979] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.724025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.725072] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.727181] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.728246] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.745155] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.745213] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.745383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.745919] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.746062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.761841] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.780341] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.780619] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.780709] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.781031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.781075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.781118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.781161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.781204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.781247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.781294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.781339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.781382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.781425] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.781595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.781640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.781685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.781743] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.781786] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.781841] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.781905] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.781958] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.782002] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.782041] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.783205] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.783384] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.783530] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.783652] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.783814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.783859] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.783903] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.783945] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.783990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.784034] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.784077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.784120] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.784163] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.784205] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.784212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.784254] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.784260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.784303] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.784346] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.784389] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.784431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.784664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.784710] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.784752] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.784795] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.784838] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.784881] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.784924] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.784990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.785044] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.785088] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.785238] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.785276] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.785699] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.786193] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.786234] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.786291] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.786691] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.787013] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.787058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.787101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.787144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.787187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.787230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.787273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.787315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.787358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.787401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.787592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.787637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.787711] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.787754] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.789168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.789212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.789256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.790070] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.790114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.791166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.793270] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.794302] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.811225] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.811282] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.811614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.812005] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.812154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.827914] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.846421] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.846581] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.846671] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.846996] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.847040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.847083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.847126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.847169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.847211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.847258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.847301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.847344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.847387] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.847589] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.847685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.847730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.847789] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.847832] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.847888] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.847952] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.848005] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.848049] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.848088] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.849252] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.849511] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.849558] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.849679] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.849723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.849769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.849813] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.849856] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.849900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.849944] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.849988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.850032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.850074] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.850117] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.850124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.850167] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.850173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.850217] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.850260] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.850303] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.850347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.850390] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.850569] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.850669] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.850712] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.850755] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.850797] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.850841] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.850905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.850958] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.851002] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.851146] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.851183] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.851595] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.852112] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.852154] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.852210] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.852613] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.852932] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.852976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.853019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.853061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.853104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.853148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.853191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.853234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.853276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.853319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.853366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.853410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.853619] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.853662] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.855081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.855125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.855170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.855951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.855994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.856786] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.856830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.857933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.860036] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.861068] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.877993] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.878049] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.878220] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.878762] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.878907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.894674] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.913181] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.913294] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.913382] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.913753] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.913798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.913842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.913885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.913928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.913971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.914018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.914061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.914105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.914148] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.914196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.914241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.914286] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.914346] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.914388] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.914596] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.914661] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.914714] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.914757] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.914796] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.915344] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.915617] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.915669] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.915791] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.915835] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.915879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.915923] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.915965] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.916009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.916052] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.916095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.916138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.916180] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.916222] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.916229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.916271] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.916277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.916320] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.916363] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.916405] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.916613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.916655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.916701] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.916743] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.916786] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.916829] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.916872] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.916916] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.916982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.917035] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.917079] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.917225] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.917263] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.917675] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.918181] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.918223] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.918280] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.918689] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.919008] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.919052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.919095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.919138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.919181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.919224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.919267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.919309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.919352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.919395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.919577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.919622] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.919697] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.919740] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.921150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.921194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.921239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.922047] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.922091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.923148] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.925242] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.926278] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.943207] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.943264] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.943598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.943992] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.944135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.959897] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.977753] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.977866] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.977955] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.978279] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.978323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.978367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.978409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.978632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.978676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.978724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.978767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.978810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.978854] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.978903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.978949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.978995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.979055] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.979098] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.979153] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.979216] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.979269] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.979313] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 567.979353] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 567.980574] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.981240] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 567.981293] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 567.981416] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 567.981586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 567.981632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 567.981675] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 567.981718] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 567.981763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.981808] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 567.981852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.981895] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 567.981939] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.981981] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 567.981989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.982031] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 567.982037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.982081] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 567.982125] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 567.982169] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 567.982212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 567.982255] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 567.982300] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 567.982343] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 567.982387] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.982431] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.982637] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.982680] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 567.982744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.982796] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.982840] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 567.982985] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 567.983024] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 567.983314] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 567.983369] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.983411] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 567.983631] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 567.983885] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.984225] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 567.984270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 567.984313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.984356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.984399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.984597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 567.984641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 567.984684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 567.984727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 567.984771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 567.984821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 567.984866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.984941] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 567.984985] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 567.986405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.986482] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.986527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 567.987284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.987326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 567.988084] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 567.988129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 567.989180] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 567.991282] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 567.992290] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.009209] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.009266] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.009595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.009992] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.010142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.025899] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.044408] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.044573] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.044663] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.044981] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.045026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.045069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.045112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.045155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.045198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.045245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.045288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.045330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.045373] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.045421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.045657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.045702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.045760] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.045803] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.045856] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.045920] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.045972] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.046016] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 568.046055] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 568.046711] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.047330] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.047363] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.047578] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 568.047622] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 568.047667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 568.047711] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 568.047755] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 568.047799] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.047843] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 568.047886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.047930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 568.047973] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.048015] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 568.048023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.048066] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 568.048072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.048116] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.048159] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 568.048203] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 568.048245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 568.048288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.048334] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 568.048377] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 568.048420] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.048608] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.048651] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.048693] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.048760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.048812] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.048856] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.049004] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.049043] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.049333] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 568.049388] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.049557] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.049615] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.049898] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.050221] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.050264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.050307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.050350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.050393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.050602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.050645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.050688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.050730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.050773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.050823] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.050868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.050943] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.050987] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.052402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.052479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.052523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 568.053278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.053320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.054088] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 568.054136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 568.055191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 568.057301] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 568.058343] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.075245] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.075302] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.075631] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.076026] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.076167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.091933] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.110433] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.110590] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.110679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.110996] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.111040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.111083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.111126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.111169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.111212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.111258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.111301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.111344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.111387] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.111586] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.111633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.111678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.111736] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.111779] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.111833] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.111896] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.111949] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.111993] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 568.112032] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 568.113196] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.113369] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.113503] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.113623] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 568.113666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 568.113712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 568.113757] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 568.113800] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 568.113844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.113888] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 568.113931] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.113975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 568.114018] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.114060] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 568.114067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.114111] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 568.114118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.114162] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.114205] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 568.114249] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 568.114292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 568.114336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.114382] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 568.114426] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 568.114700] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.114744] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.114787] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.114830] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.114901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.114955] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.114999] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.115149] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.115187] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.115602] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 568.116099] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.116139] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.116194] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.116585] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.116905] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.116949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.116992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.117035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.117077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.117120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.117163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.117205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.117248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.117291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.117338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.117382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.117588] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.117632] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.119051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.119095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.119140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 568.119969] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.120012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.120784] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 568.120828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 568.121954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 568.124056] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 568.125113] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.142039] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.142096] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.142267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.142805] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.142949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.158722] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.177231] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.177344] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.177432] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.177910] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.177954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.177997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.178040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.178083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.178126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.178172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.178215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.178258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.178301] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.178348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.178393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.178556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.178615] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.178657] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.178710] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.178774] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.178827] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.178871] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 568.178910] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 568.180082] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.180264] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.180316] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.180432] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 568.180599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 568.180645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 568.180688] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 568.180731] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 568.180777] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.180821] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 568.180864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.180908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 568.180952] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.180995] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 568.181003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.181045] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 568.181051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.181095] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.181138] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 568.181182] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 568.181225] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 568.181268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.181314] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 568.181356] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 568.181400] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.181586] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.181629] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.181672] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.181737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.181789] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.181833] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.181979] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.182017] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.182307] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 568.182361] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.182403] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.182629] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.182881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.183210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.183254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.183298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.183341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.183383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.183426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.183610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.183654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.183697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.183740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.183789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.183835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.183910] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.183956] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.185373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.185417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.185571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 568.186334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.186378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.187223] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 568.187267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 568.188373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 568.190478] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 568.191550] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.208505] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.208562] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.208733] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.209134] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.209281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.225140] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.243680] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.243793] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.243881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.244201] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.244246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.244290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.244333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.244376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.244418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.244634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.244678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.244721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.244764] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.244813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.244861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.244907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.244966] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.245010] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.245064] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.245127] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.245181] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.245225] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 568.245264] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 568.246430] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.246624] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.246660] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.246780] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 568.246823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 568.246868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 568.246912] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 568.246955] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 568.246998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.247041] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 568.247084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.247128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 568.247170] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.247212] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 568.247219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.247260] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 568.247266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.247309] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.247352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 568.247395] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 568.247616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 568.247658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.247703] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 568.247746] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 568.247789] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.247832] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.247874] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.247918] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.247985] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.248038] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.248082] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.248228] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.248266] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.248690] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 568.249177] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.249219] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.249277] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.249690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.250011] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.250055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.250098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.250141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.250184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.250227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.250270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.250313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.250355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.250398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.250585] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.250630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.250704] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.250748] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.252165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.252209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.252254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 568.253083] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 568.253128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 568.254179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 568.256277] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 568.257311] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.274242] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.274299] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.274636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.275033] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.275174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.290925] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.309418] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.309576] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.309665] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.309991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.310035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.310078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.310121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.310165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.310208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.310255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.310298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.310341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.310384] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.310432] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.310674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.310719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.310779] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.310821] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.310876] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.310939] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.310992] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.311036] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:22 BXT-2 kernel: [ 568.311075] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:22 BXT-2 kernel: [ 568.312241] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.312504] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.312553] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.312677] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:22 BXT-2 kernel: [ 568.312722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:22 BXT-2 kernel: [ 568.312768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:22 BXT-2 kernel: [ 568.312812] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:22 BXT-2 kernel: [ 568.312855] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:22 BXT-2 kernel: [ 568.312900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.312944] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:22 BXT-2 kernel: [ 568.312987] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.313032] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:22 BXT-2 kernel: [ 568.313074] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.313117] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:22 BXT-2 kernel: [ 568.313124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.313167] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:22 BXT-2 kernel: [ 568.313174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.313217] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:22 BXT-2 kernel: [ 568.313261] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:22 BXT-2 kernel: [ 568.313305] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:22 BXT-2 kernel: [ 568.313348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:22 BXT-2 kernel: [ 568.313391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:22 BXT-2 kernel: [ 568.313578] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:22 BXT-2 kernel: [ 568.313679] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:22 BXT-2 kernel: [ 568.313722] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.313766] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.313808] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.313851] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:22 BXT-2 kernel: [ 568.313918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.313971] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.314016] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.314160] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:22 BXT-2 kernel: [ 568.314198] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:22 BXT-2 kernel: [ 568.314606] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:22 BXT-2 kernel: [ 568.315109] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.315150] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:22 BXT-2 kernel: [ 568.315206] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:22 BXT-2 kernel: [ 568.315596] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.315914] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:22 BXT-2 kernel: [ 568.315959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:22 BXT-2 kernel: [ 568.316002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.316045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.316088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.316131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:22 BXT-2 kernel: [ 568.316174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:22 BXT-2 kernel: [ 568.316217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:22 BXT-2 kernel: [ 568.316259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:22 BXT-2 kernel: [ 568.316302] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:22 BXT-2 kernel: [ 568.316349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:22 BXT-2 kernel: [ 568.316393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.316612] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:22 BXT-2 kernel: [ 568.316656] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.318076] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.318121] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.318165] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:22 BXT-2 kernel: [ 568.319000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.319044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:22 BXT-2 kernel: [ 568.319792] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:22 BXT-2 kernel: [ 568.319837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:22 BXT-2 kernel: [ 568.320933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:22 BXT-2 kernel: [ 568.323039] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:22 BXT-2 kernel: [ 568.324107] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:22 BXT-2 kernel: [ 568.341021] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:22 BXT-2 kernel: [ 568.341079] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.341249] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:22 BXT-2 kernel: [ 568.341793] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:22 BXT-2 kernel: [ 568.341938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.357702] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.375503] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.375617] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.375706] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.376030] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.376074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.376117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.376160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.376203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.376245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.376292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.376334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.376377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.376420] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.376623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.376670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.376716] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.376777] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.376820] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.376875] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.376938] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.376994] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.377040] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.377079] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.378252] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.378515] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.378568] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.378689] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.378734] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.378779] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.378824] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.378867] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.378912] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.378956] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.378999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.379044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.379087] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.379129] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.379137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.379179] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.379186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.379230] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.379273] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.379317] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.379360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.379403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.379611] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.379654] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.379698] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.379741] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.379784] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.379826] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.379891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.379945] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.379989] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.380137] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.380175] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.380588] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.381088] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.381129] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.381185] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.381586] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.381909] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.381953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.381996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.382039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.382082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.382125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.382168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.382211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.382254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.382297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.382343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.382388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.382617] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.382662] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.384092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.384136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.384181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.384986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.385030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.385799] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.385844] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.386946] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.389044] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.390100] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.407039] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.407096] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.407267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.407810] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.407960] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.423720] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.442242] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.442355] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.442599] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.442921] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.442965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.443009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.443051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.443094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.443137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.443185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.443228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.443270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.443313] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.443361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.443406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.443601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.443659] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.443702] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.443755] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.443816] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.443869] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.443913] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.443952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.444603] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.445229] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.445283] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.445403] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.445560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.445605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.445648] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.445691] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.445736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.445781] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.445824] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.445868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.445911] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.445953] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.445960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.446003] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.446009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.446053] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.446096] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.446140] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.446183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.446226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.446272] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.446315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.446358] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.446402] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.446649] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.446692] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.446759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.446811] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.446855] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.446998] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.447036] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.447326] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.447382] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.447424] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.447645] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.447888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.448210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.448254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.448297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.448340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.448382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.448425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.448588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.448631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.448674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.448717] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.448765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.448811] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.448885] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.448929] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.450343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.450386] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.450431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.451304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.451349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.452127] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.452172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.453224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.455320] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.456357] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.473284] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.473341] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.473676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.474069] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.474196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.489972] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.508512] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.508625] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.508714] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.509036] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.509080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.509123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.509166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.509209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.509252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.509298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.509341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.509386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.509429] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.509668] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.509714] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.509759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.509818] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.509862] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.509917] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.509980] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.510033] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.510077] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.510117] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.511282] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.511535] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.511584] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.511707] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.511751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.511796] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.511841] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.511884] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.511929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.511972] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.512016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.512060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.512103] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.512146] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.512153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.512195] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.512202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.512246] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.512289] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.512333] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.512376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.512419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.512628] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.512671] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.512713] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.512756] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.512799] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.512841] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.512906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.512959] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.513003] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.513150] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.513188] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.513600] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.514099] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.514139] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.514194] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.514595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.514921] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.514966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.515009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.515052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.515095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.515137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.515180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.515223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.515266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.515309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.515355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.515400] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.515624] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.515668] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.517097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.517142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.517187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.517976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.518019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.518788] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.518833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.519945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.522047] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.523100] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.540038] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.540095] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.540265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.540808] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.540958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.556720] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.575215] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.575328] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.575416] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.575909] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.575954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.575998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.576041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.576083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.576126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.576174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.576217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.576260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.576303] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.576351] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.576396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.576554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.576614] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.576656] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.576710] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.576772] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.576825] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.576869] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.576908] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.578070] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.578249] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.578301] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.578420] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.578588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.578633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.578677] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.578720] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.578765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.578810] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.578853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.578897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.578940] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.578983] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.578991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.579033] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.579040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.579084] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.579127] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.579170] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.579213] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.579257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.579303] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.579346] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.579390] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.579583] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.579627] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.579670] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.579734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.579786] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.579830] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.579977] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.580015] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.580305] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.580360] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.580402] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.580641] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.580891] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.581216] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.581260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.581303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.581346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.581389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.581432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.581614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.581658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.581701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.581744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.581793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.581838] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.581914] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.581958] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.583375] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.583420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.583551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.584313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.584356] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.585092] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.585136] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.586191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.588295] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.589331] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.606257] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.606314] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.606648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.607043] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.607190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.622940] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.641438] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.641600] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.641690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.642011] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.642054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.642099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.642142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.642185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.642228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.642275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.642318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.642361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.642404] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.642645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.642690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.642735] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.642794] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.642837] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.642891] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.642954] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.643008] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.643052] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.643091] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.644257] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.644510] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.644564] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.644687] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.644731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.644777] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.644821] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.644864] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.644909] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.644953] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.644996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.645040] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.645083] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.645125] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.645133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.645175] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.645182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.645226] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.645270] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.645313] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.645356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.645399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.645627] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.645669] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.645712] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.645755] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.645798] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.645840] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.645907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.645960] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.646004] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.646148] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.646186] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.646592] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.647103] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.647144] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.647199] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.647602] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.647923] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.647967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.648010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.648052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.648095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.648138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.648181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.648223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.648266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.648309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.648355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.648399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.648594] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.648637] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.650052] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.650095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.650139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.650963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.651007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.651803] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.651848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.652941] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.655045] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.656087] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.673006] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.673062] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.673233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.673780] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.673915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.689687] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.708186] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.708299] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.708386] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.708741] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.708787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.708831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.708874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.708918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.708961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.709009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.709052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.709096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.709139] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.709187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.709235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.709280] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.709339] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.709382] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.709581] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.709645] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.709697] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.709740] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.709778] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.710335] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.710632] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.710680] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.710800] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.710843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.710888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.710931] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.710974] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.711017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.711060] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.711103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.711146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.711188] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.711230] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.711237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.711278] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.711284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.711327] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.711370] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.711412] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.711621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.711663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.711708] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.711750] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.711792] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.711835] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.711878] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.711922] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.711987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.712040] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.712083] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.712226] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.712264] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.712668] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.713177] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.713220] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.713277] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.713675] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.713998] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.714041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.714084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.714127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.714170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.714212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.714255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.714297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.714340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.714383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.714429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.714609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.714685] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.714728] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.716160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.716205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.716250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.717075] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.717119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.718169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.720265] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.721265] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.738192] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.738249] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.738420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.738958] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.739101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.754868] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.773389] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.773552] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.773642] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.773965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.774010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.774053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.774096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.774139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.774182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.774229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.774271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.774314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.774357] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.774405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.774616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.774661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.774721] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.774763] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.774818] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.774882] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.774936] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.774980] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.775020] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.776187] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.776367] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.776519] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.776642] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.776686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.776732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.776776] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.776820] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.776864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.776907] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.776951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.776995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.777038] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.777081] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.777088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.777131] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.777138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.777182] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.777225] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.777268] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.777312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.777355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.777400] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.777598] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.777642] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.777685] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.777727] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.777770] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.777834] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.777887] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.777932] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.778076] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.778114] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.778404] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.779037] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.779078] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.779134] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.779425] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.779878] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.779923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.779967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.780010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.780052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.780095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.780138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.780183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.780225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.780269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.780315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.780360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.780433] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.780619] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.782042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.782087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.782132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.782951] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.782996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.784046] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.786152] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.787223] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.804129] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.804186] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.804356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.804890] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.805035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.820805] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.839297] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.839408] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.839656] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.839980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.840025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.840068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.840111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.840154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.840198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.840246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.840289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.840332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.840375] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.840423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.840675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.840721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.840780] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.840822] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.840874] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.840939] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.840991] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.841035] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.841074] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.842235] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.842507] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.842560] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.842683] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.842727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.842773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.842818] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.842861] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.842906] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.842950] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.842993] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.843037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.843080] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.843123] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.843130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.843173] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.843180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.843224] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.843267] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.843311] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.843354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.843397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.843624] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.843666] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.843710] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.843753] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.843796] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.843839] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.843902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.843955] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.843999] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.844143] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.844182] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.844592] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.845092] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.845132] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.845187] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.845591] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.845916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.845960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.846004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.846047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.846089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.846132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.846175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.846218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.846261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.846304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.846350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.846395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.846598] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.846642] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.848063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.848107] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.848152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.848976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.849019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.849793] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.849838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.850949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.853052] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.854121] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.871033] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.871091] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.871260] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.871801] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.871954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.887718] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.906252] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.906364] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.906621] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.906945] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.906989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.907032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.907075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.907118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.907161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.907209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.907252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.907295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.907338] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.907386] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.907431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.907599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.907658] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.907700] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.907754] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.907817] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.907869] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.907914] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.907953] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.909126] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.909305] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.909352] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.909578] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.909623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.909667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.909711] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.909754] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.909800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.909843] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.909887] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.909931] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.909974] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.910016] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.910024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.910066] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.910072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.910116] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.910159] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.910203] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.910246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.910289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.910335] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.910378] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.910421] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.910632] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.910675] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.910718] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.910781] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.910833] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.910877] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.911018] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.911056] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.911346] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.911401] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.911559] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.911614] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.911897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.912224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.912268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.912312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.912354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.912397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.912603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.912646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.912689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.912734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.912777] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.912826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.912872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.912947] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.912991] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.914408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.914488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.914534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.915291] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.915334] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.916082] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.916130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.917208] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.919317] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.920362] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.937301] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.937358] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.937693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.938091] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.938237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.954575] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.970700] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.970813] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.970901] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.971226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.971270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.971313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.971356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.971398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.971524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.971573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.971616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.971659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.971703] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.971751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.971797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.971843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.971904] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.971947] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.972002] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.972065] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.972117] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.972160] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 568.972199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 568.972823] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.973530] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 568.973583] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 568.973707] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 568.973751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 568.973796] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 568.973840] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 568.973883] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 568.973928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.973972] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 568.974015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.974059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 568.974101] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.974144] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 568.974151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.974194] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 568.974200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.974243] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 568.974286] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 568.974330] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 568.974372] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 568.974415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 568.974502] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 568.974545] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 568.974589] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.974633] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.974676] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.974719] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 568.974782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.974834] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.974878] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 568.975027] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 568.975065] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 568.975355] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 568.975409] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.975471] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 568.975529] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 568.976147] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.976549] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 568.976595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 568.976639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.976682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.976725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.976769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 568.976812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 568.976855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 568.976899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 568.976942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 568.976992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 568.977036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.977112] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 568.977155] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 568.979186] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.979232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.979277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 568.980093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.980138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 568.980958] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 568.981006] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 568.982062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 568.983521] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 568.984597] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.001534] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.001591] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.001762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.002090] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.002230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.018184] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.036713] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.036826] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.036914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.037238] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.037283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.037326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.037369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.037412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.037532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.037580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.037626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.037670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.037714] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.037761] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.037807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.037852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.037917] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.037960] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.038016] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.038079] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.038131] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.038175] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 569.038215] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 569.038793] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.038972] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.039030] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.039151] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 569.039195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 569.039239] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 569.039283] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 569.039326] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 569.039369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.039413] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 569.039496] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.039542] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 569.039584] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.039627] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 569.039634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.039676] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 569.039682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.039727] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.039770] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 569.039814] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 569.039857] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 569.039901] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.039946] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 569.039989] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 569.040033] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.040077] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.040120] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.040164] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.040228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.040282] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.040326] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.040497] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.040535] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.040825] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 569.040880] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.040922] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.040979] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.041269] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.041615] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.041660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.041704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.041747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.041790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.041833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.041876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.041919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.041961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.042005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.042051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.042096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.042170] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.042213] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.043638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.043683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.043727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 569.044526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.044570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.045281] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 569.045324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 569.046382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 569.048512] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 569.049551] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.066507] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.066564] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.066734] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.067126] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.067273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.083159] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.101688] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.101801] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.101888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.102215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.102259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.102302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.102345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.102388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.102431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.102542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.102589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.102632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.102676] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.102724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.102770] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.102815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.102881] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.102925] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.102980] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.103043] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.103096] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.103140] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 569.103179] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 569.103764] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.103941] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.103979] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.104094] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 569.104138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 569.104182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 569.104226] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 569.104268] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 569.104312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.104355] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 569.104398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.104478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 569.104521] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.104564] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 569.104571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.104613] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 569.104619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.104663] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.104707] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 569.104750] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 569.104794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 569.104837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.104882] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 569.104925] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 569.104969] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.105013] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.105056] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.105099] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.105164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.105217] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.105261] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.105413] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.105473] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.105764] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 569.105818] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.105860] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.105917] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.106210] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.106536] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.106582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.106628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.106672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.106715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.106758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.106801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.106844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.106886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.106929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.106976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.107021] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.107094] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.107137] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.108587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.108631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.108675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 569.109426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.109495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.110207] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 569.110250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 569.111291] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 569.113385] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 569.114428] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.131355] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.131412] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.131638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.132032] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.132169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.148064] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.166740] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.166853] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.166941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.167265] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.167309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.167353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.167396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.167530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.167573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.167622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.167666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.167710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.167754] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.167802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.167850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.167895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.167959] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.168002] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.168057] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.168120] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.168173] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.168216] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 569.168256] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 569.168836] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.169008] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.169060] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.169173] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 569.169217] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 569.169261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 569.169305] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 569.169348] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 569.169391] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.169465] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 569.169509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.169556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 569.169599] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.169642] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 569.169649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.169691] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 569.169698] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.169742] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.169785] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 569.169829] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 569.169872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 569.169915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.169961] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 569.170003] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 569.170047] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.170090] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.170134] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.170177] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.170242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.170295] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.170339] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.170537] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.170576] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.170865] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 569.170919] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.170962] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.171019] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.171309] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.171633] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.171679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.171726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.171769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.171812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.171856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.171899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.171942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.171984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.172027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.172075] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.172120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.172193] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.172236] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.173689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.173732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.173777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 569.174539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.174583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.175295] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 569.175338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 569.176378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 569.178470] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 569.179491] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.196382] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.196477] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.196652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.197043] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.197184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.213061] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.231573] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.231686] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.231774] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.232093] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.232137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.232180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.232223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.232266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.232309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.232355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.232398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.232507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.232553] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.232601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.232647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.232693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.232754] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.232797] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.232851] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.232914] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.232967] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.233011] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 569.233050] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 569.233627] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.233801] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.233853] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.233973] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 569.234016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 569.234061] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 569.234104] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 569.234147] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 569.234190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.234233] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 569.234275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.234319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 569.234361] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.234403] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 569.234438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.234482] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 569.234491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.234535] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.234581] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 569.234627] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 569.234672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 569.234717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.234764] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 569.234809] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 569.234855] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.234900] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.234943] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.234986] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.235053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.235105] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.235149] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.235304] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.235342] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.235659] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 569.235715] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.235756] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.235812] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.236098] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.236419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.236502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.236548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.236593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.236636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.236679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.236722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.236765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.236808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.236852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.236900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.236945] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.237019] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.237063] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.238519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.238563] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.238607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 569.239360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.239403] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.240163] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 569.240207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 569.241282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 569.243376] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 569.244439] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.261366] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.261424] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.261653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.262045] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.262189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.278038] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.296545] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.296658] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.296748] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.297068] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.297113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.297156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.297199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.297242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.297288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.297334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.297377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.297420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.297527] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.297577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.297624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.297672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.297738] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.297780] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.297834] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.297897] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.297950] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.297994] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:23 BXT-2 kernel: [ 569.298033] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:23 BXT-2 kernel: [ 569.298608] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.298784] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.298822] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.298937] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:23 BXT-2 kernel: [ 569.298980] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:23 BXT-2 kernel: [ 569.299025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:23 BXT-2 kernel: [ 569.299069] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:23 BXT-2 kernel: [ 569.299112] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:23 BXT-2 kernel: [ 569.299156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.299200] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:23 BXT-2 kernel: [ 569.299243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.299286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:23 BXT-2 kernel: [ 569.299328] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.299370] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:23 BXT-2 kernel: [ 569.299376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.299418] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:23 BXT-2 kernel: [ 569.299453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.299503] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:23 BXT-2 kernel: [ 569.299549] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:23 BXT-2 kernel: [ 569.299594] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:23 BXT-2 kernel: [ 569.299639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:23 BXT-2 kernel: [ 569.299684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:23 BXT-2 kernel: [ 569.299732] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:23 BXT-2 kernel: [ 569.299777] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:23 BXT-2 kernel: [ 569.299824] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.299869] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.299915] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.299958] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:23 BXT-2 kernel: [ 569.300021] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.300074] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.300117] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.300266] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:23 BXT-2 kernel: [ 569.300304] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:23 BXT-2 kernel: [ 569.300617] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:23 BXT-2 kernel: [ 569.300675] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.300716] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:23 BXT-2 kernel: [ 569.300771] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:23 BXT-2 kernel: [ 569.301054] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.301377] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.301421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:23 BXT-2 kernel: [ 569.301503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.301550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.301596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.301639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:23 BXT-2 kernel: [ 569.301682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:23 BXT-2 kernel: [ 569.301725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:23 BXT-2 kernel: [ 569.301768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:23 BXT-2 kernel: [ 569.301813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:23 BXT-2 kernel: [ 569.301860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:23 BXT-2 kernel: [ 569.301906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.301981] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:23 BXT-2 kernel: [ 569.302025] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.303508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.303552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.303597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:23 BXT-2 kernel: [ 569.304359] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.304401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:23 BXT-2 kernel: [ 569.305167] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:23 BXT-2 kernel: [ 569.305211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:23 BXT-2 kernel: [ 569.306285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:23 BXT-2 kernel: [ 569.308378] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:23 BXT-2 kernel: [ 569.309412] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:23 BXT-2 kernel: [ 569.326347] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:23 BXT-2 kernel: [ 569.326405] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.326632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:23 BXT-2 kernel: [ 569.327026] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:23 BXT-2 kernel: [ 569.327166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:23 BXT-2 kernel: [ 569.343029] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.361534] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.361648] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.361736] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.362057] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.362100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.362145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.362188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.362231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.362274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.362320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.362363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.362406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.362519] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.362572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.362619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.362664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.362727] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.362770] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.362823] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.362886] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.362937] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.362982] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.363021] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.363603] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.363780] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.363830] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.363948] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.363992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.364037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.364082] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.364125] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.364169] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.364212] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.364256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.364300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.364343] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.364385] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.364392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.364465] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.364474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.364521] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.364565] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.364612] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.364656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.364701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.364748] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.364792] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.364837] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.364883] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.364926] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.364969] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.365035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.365088] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.365132] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.365293] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.365332] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.365672] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.365735] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.365777] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.365835] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.366143] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.366487] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.366533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.366577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.366619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.366662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.366705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.366748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.366791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.366834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.366877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.366925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.366970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.367043] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.367087] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.368538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.368582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.368626] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.369390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.369461] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.370187] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.370231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.371298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.373392] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.374469] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.391391] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.391494] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.391667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.392062] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.392205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.408074] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.426567] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.426680] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.426771] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.427095] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.427139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.427183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.427225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.427268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.427311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.427358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.427401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.427507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.427551] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.427602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.427647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.427692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.427758] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.427802] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.427857] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.427921] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.427973] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.428017] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.428056] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.428632] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.428808] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.428862] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.428981] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.429024] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.429069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.429113] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.429155] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.429199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.429242] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.429284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.429327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.429370] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.429412] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.429448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.429496] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.429507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.429552] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.429597] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.429643] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.429689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.429734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.429781] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.429825] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.429868] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.429914] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.429958] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.430000] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.430062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.430114] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.430158] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.430308] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.430346] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.430661] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.430719] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.430759] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.430815] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.431101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.431427] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.431510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.431557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.431601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.431645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.431688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.431732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.431775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.431819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.431863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.431911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.431956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.432031] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.432075] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.433532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.433577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.433621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.434374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.434416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.435156] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.435200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.436262] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.438356] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.439383] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.456295] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.456352] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.456582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.456977] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.457122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.472969] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.491501] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.491615] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.491703] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.492026] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.492070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.492113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.492156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.492198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.492241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.492287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.492330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.492373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.492416] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.492531] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.492577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.492624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.492683] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.492725] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.492779] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.492842] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.492895] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.492939] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.492978] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.493574] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.494266] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.494321] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.494443] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.494518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.494565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.494612] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.494654] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.494698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.494742] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.494786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.494830] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.494873] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.494915] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.494923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.494965] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.494972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.495015] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.495058] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.495102] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.495145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.495188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.495233] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.495276] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.495319] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.495363] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.495406] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.495472] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.495539] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.495593] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.495638] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.495788] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.495826] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.496118] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.496173] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.496215] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.496272] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.496609] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.496935] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.496979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.497023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.497066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.497110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.497153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.497196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.497240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.497283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.497327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.497374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.497419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.497530] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.497574] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.499011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.499054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.499099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.499905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.499949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.500707] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.500752] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.501807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.503911] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.504936] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.521864] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.521921] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.522092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.522552] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.522686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.538586] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.557086] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.557201] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.557290] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.557631] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.557676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.557720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.557765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.557807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.557853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.557901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.557944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.557987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.558031] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.558078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.558124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.558169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.558231] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.558274] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.558328] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.558392] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.558491] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.558534] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.558573] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.559129] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.559308] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.559360] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.559533] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.559577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.559623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.559669] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.559711] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.559755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.559799] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.559844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.559888] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.559931] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.559973] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.559980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.560023] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.560029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.560073] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.560116] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.560160] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.560202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.560245] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.560291] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.560333] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.560377] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.560420] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.560484] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.560528] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.560590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.560643] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.560686] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.560832] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.560870] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.561160] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.561214] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.561255] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.561312] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.561819] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.562150] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.562195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.562239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.562281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.562326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.562369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.562411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.562523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.562566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.562609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.562658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.562703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.562778] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.562821] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.564355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.564400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.564484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.565262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.565309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.566114] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.566158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.567223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.569325] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.570350] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.587234] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.587287] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.587753] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.588096] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.588236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.603892] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.621725] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.621836] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.621926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.622246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.622292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.622338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.622383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.622425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.622973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.623025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.623068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.623112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.623157] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.623204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.623250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.623294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.623359] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.623402] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.623521] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.623587] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.623640] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.623683] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.623721] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.624279] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.624509] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.624562] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.624684] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.624728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.624773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.624817] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.624859] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.624904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.624946] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.624991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.625034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.625076] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.625117] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.625124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.625165] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.625171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.625214] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.625258] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.625301] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.625343] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.625385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.625432] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.625514] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.625558] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.625602] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.625645] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.625688] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.625754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.625806] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.625852] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.625997] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.626035] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.626323] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.626377] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.626419] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.626499] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.627220] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.627548] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.627595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.627790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.627833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.627877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.627922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.627966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.628009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.628051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.628094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.628141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.628186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.628259] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.628304] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.630265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.630312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.630357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.631133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.631176] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.631909] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.631953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.633006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.635101] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.636109] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.653028] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.653085] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.653258] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.653714] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.653859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.669714] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.688221] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.688334] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.688422] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.688804] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.688849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.688892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.688935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.688978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.689022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.689068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.689111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.689154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.689198] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.689245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.689290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.689335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.689400] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.689471] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.689530] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.689594] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.689647] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.689692] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.689731] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.690278] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.690478] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.690536] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.690658] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.690702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.690747] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.690790] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.690832] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.690876] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.690919] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.690962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.691005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.691047] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.691089] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.691096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.691138] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.691143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.691187] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.691229] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.691272] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.691314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.691357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.691401] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.691474] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.691520] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.691567] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.691612] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.691658] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.691723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.691777] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.691822] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.691969] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.692007] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.692296] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.692350] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.692392] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.692472] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.692758] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.693082] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.693127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.693172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.693215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.693258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.693302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.693346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.693390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.693472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.693518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.693567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.693613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.693688] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.693732] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.695173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.695217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.695262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.696042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.696086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.696817] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.696861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.697898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.699988] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.701052] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.717988] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.718045] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.718215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.718670] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.718799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.734668] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.753175] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.753288] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.753377] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.753705] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.753750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.753794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.753838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.753881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.753925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.753973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.754017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.754061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.754105] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.754153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.754198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.754244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.754310] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.754353] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.754408] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.754504] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.754559] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.754603] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.754642] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.755189] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.755364] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.755453] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.755573] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.755617] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.755662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.755707] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.755750] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.755794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.755838] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.755882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.755926] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.755969] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.756012] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.756019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.756061] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.756068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.756112] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.756155] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.756199] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.756241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.756285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.756330] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.756373] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.756416] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.756485] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.756531] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.756578] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.756643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.756697] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.756741] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.756894] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.756932] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.757221] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.757276] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.757318] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.757375] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.757698] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.758018] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.758063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.758106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.758149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.758192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.758234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.758277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.758320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.758363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.758406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.758495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.758542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.758619] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.758663] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.760112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.760157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.760201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.761020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.761063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.761798] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.761843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.762885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.764981] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.766033] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.782930] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.782988] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.783159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.783641] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.783783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.799629] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.818120] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.818232] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.818320] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.818652] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.818698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.818742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.818785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.818829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.818873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.818921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.818965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.819008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.819052] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.819100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.819145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.819191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.819251] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.819294] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.819348] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.819411] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.819488] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.819535] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.819577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.820127] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.820303] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.820353] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.820506] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.820550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.820594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.820638] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.820680] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.820725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.820768] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.820812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.820856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.820898] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.820941] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.820948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.820990] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.820996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.821040] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.821083] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.821126] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.821169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.821212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.821257] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.821300] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.821344] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.821388] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.821431] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.821497] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.821561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.821614] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.821661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.821809] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.821847] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.822136] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.822190] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.822232] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.822288] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.822611] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.822934] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.822979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.823023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.823066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.823110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.823153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.823197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.823240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.823284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.823327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.823374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.823419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.823528] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.823573] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.824991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.825034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.825078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.825858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.825902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.826625] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.826669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.827711] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.829822] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.830889] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.847801] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.847858] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.848029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.848477] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.848628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.864538] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.883024] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.883137] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.883226] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.883549] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.883594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.883638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.883681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.883725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.883768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.883817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.883860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.883904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.883948] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.883995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.884043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.884090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.884149] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.884193] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.884249] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.884313] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.884367] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.884411] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.884480] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.885040] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.885224] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.885278] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.885397] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 569.885482] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 569.885531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 569.885577] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 569.885622] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 569.885666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.885709] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:24 BXT-2 kernel: [ 569.885753] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.885797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 569.885840] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.885882] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 569.885890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.885932] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 569.885938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.885982] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 569.886025] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 569.886068] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 569.886111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 569.886154] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 569.886200] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 569.886243] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 569.886286] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.886329] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.886372] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.886415] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 569.886503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.886557] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.886602] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.886755] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.886792] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.887081] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 569.887137] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.887178] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.887235] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.887515] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.887846] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.887891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.887934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.887978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.888021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.888064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.888108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.888151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.888195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.888238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.888285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.888330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.888404] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.888473] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.889889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.889933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.889978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 569.890757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.890800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 569.891520] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 569.891564] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 569.892601] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 569.894712] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 569.895782] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.912723] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.912780] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.912951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.913339] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.913556] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.929407] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:24 BXT-2 kernel: [ 569.947943] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:24 BXT-2 kernel: [ 569.948057] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.948145] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.948501] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 569.948546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 569.948590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.948634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.948678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.948721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 569.948770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 569.948813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 569.948857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 569.948901] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 569.948949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 569.948997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 569.949044] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 569.949110] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 569.949153] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.949208] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 569.949271] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 569.949324] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 569.949368] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 569.949407] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 569.949983] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 569.950365] [drm:drm_mode_addfb2] [FB:76] >May 24 03:31:24 BXT-2 kernel: [ 569.950479] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:24 BXT-2 kernel: [ 570.007285] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:24 BXT-2 kernel: [ 570.007775] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.008370] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:24 BXT-2 kernel: [ 570.008978] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.009024] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.009141] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 570.009185] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 570.009231] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 570.009275] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 570.009317] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 570.009361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.009404] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:24 BXT-2 kernel: [ 570.009485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.009531] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 570.009576] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.009619] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 570.009628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.009671] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 570.009678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.009723] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.009766] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 570.009809] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 570.009854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 570.009897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.009942] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 570.009985] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 570.010028] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.010071] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.010114] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.010158] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.010224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.010278] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.010323] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.010956] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.010999] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.011288] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 570.011342] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.011384] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.011479] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.011740] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.012067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.012112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.012156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.012198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.012241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.012285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.012328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.012371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.012414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.012505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.012554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.012599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.012675] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.012718] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.014179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.014225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.014271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 570.015054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.015097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.015864] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 570.015909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 570.016951] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 570.019053] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 570.020079] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.037012] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.037070] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.037242] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.053662] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.053726] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.070549] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.070692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.087025] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.105526] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.105639] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.105728] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.106054] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.106099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.106142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.106185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.106228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.106271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.106317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.106360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.106403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.106507] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.106558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.106606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.106653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.106720] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.106763] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.106818] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.106881] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.106927] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.106971] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 570.107010] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 570.107594] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.107768] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.107823] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.107940] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 570.107983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 570.108031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 570.108075] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 570.108117] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 570.108160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.108203] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:24 BXT-2 kernel: [ 570.108247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.108290] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 570.108332] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.108374] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 570.108380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.108422] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 570.108457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.108504] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.108550] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 570.108595] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 570.108641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 570.108685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.108734] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 570.108779] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 570.108825] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.108871] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.108917] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.108961] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.109025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.109078] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.109123] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.109273] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.109311] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.109624] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 570.109682] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.109724] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.109782] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.110067] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.110390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.110473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.110520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.110565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.110611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.110654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.110698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.110741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.110785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.110829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.110876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.110921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.110996] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.111040] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.112471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.112515] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.112560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 570.113318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.113360] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.114098] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 570.114142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 570.115188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 570.117280] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 570.118295] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.135220] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.135278] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.135511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.135904] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.136050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.151900] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.170398] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.170617] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.170713] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.171041] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.171085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.171128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.171171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.171213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.171256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.171304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.171347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.171389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.171432] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.171514] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.171562] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.171607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.171669] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.171712] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.171766] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.171829] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.171874] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.171917] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 570.171956] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 570.173127] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.173306] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.173340] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.173505] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 570.173550] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 570.173594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 570.173638] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 570.173681] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 570.173727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.173770] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:24 BXT-2 kernel: [ 570.173814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.173858] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 570.173900] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.173942] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 570.173952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.173994] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 570.174000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.174044] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.174087] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 570.174130] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 570.174173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 570.174215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.174261] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 570.174304] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 570.174347] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.174391] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.174478] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.174522] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.174587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.174641] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.174684] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.174831] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.174868] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.175158] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 570.175212] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.175254] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.175311] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.175788] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.176114] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.176158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.176201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.176243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.176286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.176329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.176372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.176414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.176522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.176566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.176613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.176658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.176734] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.176778] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.178217] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.178261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.178307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 570.179162] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 570.179207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 570.180415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 570.182544] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 570.183602] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.200534] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.200589] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.200760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.201085] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.201220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.217154] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.235677] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.235788] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.235875] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.236192] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.236235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.236278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.236321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.236364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.236406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.236856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.236899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.236941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.236985] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.237032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.237076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.237121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.237182] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.237225] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.237278] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.237340] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.237383] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.237426] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 570.237942] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 570.238582] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.239212] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.239261] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.239381] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 570.239424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 570.239722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 570.239767] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 570.239809] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 570.239855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.239899] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:24 BXT-2 kernel: [ 570.239941] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.239984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 570.240026] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.240068] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 570.240076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.240117] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 570.240123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.240166] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.240209] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 570.240251] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 570.240293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 570.240335] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.240380] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 570.240422] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 570.241114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.241157] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.241200] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.241242] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.241308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.241362] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.241405] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.241841] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.241878] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.242167] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 570.242221] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.242261] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.242318] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.242837] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.243164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.243207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.243250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.243293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.243335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.243378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.243421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.243808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.243851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.243894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.243942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.243987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.244062] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.244104] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.245778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.245822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.245866] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 570.246672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.246715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.247589] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 570.247634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 570.248828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 570.250922] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 570.251981] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.268872] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.268926] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.269095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.269653] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.269814] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.285525] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.304065] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.304179] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.304267] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.304642] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.304686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.304730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.304773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.304816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.304859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.304906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.304949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.304992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.305035] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.305082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.305128] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.305172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.305239] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.305281] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.305335] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.305398] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.305472] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.305520] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:24 BXT-2 kernel: [ 570.305560] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:24 BXT-2 kernel: [ 570.306109] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.306283] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.306338] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.306489] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:24 BXT-2 kernel: [ 570.306536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:24 BXT-2 kernel: [ 570.306583] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:24 BXT-2 kernel: [ 570.306627] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:24 BXT-2 kernel: [ 570.306670] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:24 BXT-2 kernel: [ 570.306715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.306758] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:24 BXT-2 kernel: [ 570.306802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.306846] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:24 BXT-2 kernel: [ 570.306889] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.306931] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:24 BXT-2 kernel: [ 570.306939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.306981] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:24 BXT-2 kernel: [ 570.306987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.307031] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:24 BXT-2 kernel: [ 570.307074] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:24 BXT-2 kernel: [ 570.307118] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:24 BXT-2 kernel: [ 570.307161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:24 BXT-2 kernel: [ 570.307204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:24 BXT-2 kernel: [ 570.307251] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:24 BXT-2 kernel: [ 570.307293] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:24 BXT-2 kernel: [ 570.307337] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.307380] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.307424] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.307489] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:24 BXT-2 kernel: [ 570.307553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.307608] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.307654] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.307805] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:24 BXT-2 kernel: [ 570.307844] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:24 BXT-2 kernel: [ 570.308133] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:24 BXT-2 kernel: [ 570.308187] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.308229] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:24 BXT-2 kernel: [ 570.308286] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:24 BXT-2 kernel: [ 570.308616] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.308943] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:24 BXT-2 kernel: [ 570.308987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:24 BXT-2 kernel: [ 570.309030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.309073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.309116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.309159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:24 BXT-2 kernel: [ 570.309202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:24 BXT-2 kernel: [ 570.309244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:24 BXT-2 kernel: [ 570.309287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:24 BXT-2 kernel: [ 570.309330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:24 BXT-2 kernel: [ 570.309376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:24 BXT-2 kernel: [ 570.309421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.309539] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:24 BXT-2 kernel: [ 570.309583] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.311025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.311069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.311114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:24 BXT-2 kernel: [ 570.311900] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.311944] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:24 BXT-2 kernel: [ 570.312703] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:24 BXT-2 kernel: [ 570.312747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:24 BXT-2 kernel: [ 570.313798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:24 BXT-2 kernel: [ 570.315899] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:24 BXT-2 kernel: [ 570.316901] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:24 BXT-2 kernel: [ 570.333832] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:24 BXT-2 kernel: [ 570.333889] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.334060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:24 BXT-2 kernel: [ 570.334514] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:24 BXT-2 kernel: [ 570.334661] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.350552] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.369041] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.369154] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.369241] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.369567] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.369613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.369657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.369701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.369745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.369789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.369837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.369880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.369924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.369968] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.370016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.370063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.370108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.370176] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.370220] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.370274] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.370337] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.370382] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.370427] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.370491] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.371039] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.371212] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.371269] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.371385] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.371428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.371507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.371555] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.371601] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.371647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.371691] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.371734] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.371777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.371820] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.371863] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.371870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.371913] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.371919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.371963] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.372007] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.372051] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.372094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.372137] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.372182] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.372225] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.372269] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.372312] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.372355] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.372399] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.372490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.372544] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.372591] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.372743] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.372781] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.373071] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.373126] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.373167] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.373225] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.373522] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.373843] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.373887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.373931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.373975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.374018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.374062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.374105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.374149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.374192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.374236] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.374283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.374328] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.374402] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.374471] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.375885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.375929] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.375973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.376751] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.376794] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.377514] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.377558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.378594] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.380685] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.381740] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.398654] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.398711] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.398884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.399272] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.399395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.415336] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.433829] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.433941] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.434029] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.434351] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.434395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.434500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.434543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.434586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.434629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.434679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.434723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.434767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.434810] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.434859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.434906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.434952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.435021] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.435065] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.435120] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.435183] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.435229] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.435272] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.435311] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.435897] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.436079] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.436132] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.436249] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.436292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.436336] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.436380] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.436422] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.436497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.436544] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.436591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.436637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.436682] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.436726] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.436733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.436775] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.436781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.436824] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.436867] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.436910] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.436952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.436994] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.437040] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.437083] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.437126] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.437170] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.437213] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.437257] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.437320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.437374] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.437418] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.437590] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.437629] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.437918] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.437973] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.438015] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.438072] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.438359] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.438687] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.438732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.438777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.438821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.438865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.438909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.438952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.438996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.439039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.439083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.439130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.439175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.439250] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.439294] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.440731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.440774] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.440819] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.441585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.441628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.442344] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.442387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.443466] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.445558] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.446637] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.463559] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.463617] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.463789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.464180] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.464320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.480245] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.498755] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.498868] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.498955] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.499280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.499324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.499367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.499410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.499512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.499556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.499604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.499647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.499690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.499734] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.499782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.499830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.499875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.499943] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.499986] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.500041] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.500104] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.500150] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.500194] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.500233] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.500820] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.500992] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.501047] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.501165] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.501208] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.501252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.501296] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.501338] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.501382] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.501425] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.501497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.501544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.501589] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.501633] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.501643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.501687] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.501696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.501742] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.501786] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.501830] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.501873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.501915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.501960] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.502002] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.502045] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.502089] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.502132] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.502176] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.502240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.502293] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.502337] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.502506] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.502545] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.502837] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.502891] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.502933] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.502990] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.503277] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.503614] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.503659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.503704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.503747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.503790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.503836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.503879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.503923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.503966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.504011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.504059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.504104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.504179] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.504222] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.505701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.505745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.505791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.506557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.506600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.507314] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.507357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.508402] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.510508] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.511554] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.528523] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.528580] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.528751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.529144] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.529291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.545158] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.563703] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.563816] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.563904] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.564231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.564275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.564318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.564361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.564404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.564498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.564548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.564591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.564634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.564677] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.564726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.564772] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.564817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.564886] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.564930] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.564984] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.565047] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.565093] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.565137] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.565176] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.565761] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.565937] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.565995] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.566113] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.566156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.566201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.566245] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.566287] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.566331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.566374] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.566417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.566489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.566534] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.566579] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.566588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.566633] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.566640] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.566686] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.566731] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.566778] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.566822] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.566865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.566910] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.566953] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.566996] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.567039] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.567082] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.567126] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.567190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.567243] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.567288] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.567466] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.567507] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.567801] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.567855] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.567895] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.567952] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.568238] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.568559] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.568605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.568648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.568692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.568736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.568780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.568823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.568867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.568910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.568954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.569001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.569049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.569123] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.569167] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.570584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.570629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.570673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.571431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.571503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.572219] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.572263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.573307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.575401] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.576408] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.593369] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.593427] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.593658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.594049] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.594176] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.610049] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.628563] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.628676] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.628764] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.629081] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.629125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.629168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.629211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.629254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.629297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.629344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.629387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.629430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.629537] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.629586] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.629634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.629679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.629746] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.629789] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.629842] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.629905] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.629950] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.629994] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.630033] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.630610] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.630784] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.630836] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.630951] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.630995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.631040] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.631085] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.631128] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.631173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.631216] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.631260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.631304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.631347] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.631389] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.631427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.631472] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.631482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.631528] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.631573] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.631620] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.631665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.631710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.631759] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.631804] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.631848] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.631892] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.631938] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.631981] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.632043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.632095] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.632139] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.632289] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.632327] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.632643] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.632699] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.632740] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.632797] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.633082] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.633403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.633493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.633540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.633585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.633631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.633674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.633718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.633762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.633805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.633849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.633897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.633943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.634018] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.634061] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.635513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.635557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.635602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.636356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.636399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.637159] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.637202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.638278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.640372] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.641428] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.658330] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.658385] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.658595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.658924] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.659064] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.674944] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.693401] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.693538] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.693621] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.693940] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.693984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.694029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.694071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.694115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.694158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.694206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.694248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.694292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.694337] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.694383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.694428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.694502] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.694562] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.694607] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.694659] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.694720] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.694763] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.694807] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.694846] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.695395] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.695563] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.695612] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.695724] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.695767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.695811] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.695855] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.695897] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.695940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.695983] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.696025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.696069] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.696111] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.696153] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.696159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.696201] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.696206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.696249] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.696292] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.696335] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.696377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.696419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.696496] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.696542] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.696591] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.696637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.696684] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.696730] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.696793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.696845] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.696889] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.697015] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.697053] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.697341] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.697394] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.697454] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.697510] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.697828] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.698154] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.698198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.698241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.698284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.698326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.698369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.698411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.698513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.698557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.698601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.698648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.698694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.698769] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.698813] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.700257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.700300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.700345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.701137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.701180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.702020] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.702065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.703112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.705195] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.706221] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.723087] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.723142] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.723311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.723859] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.724005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.739729] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.758226] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.758336] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.758421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.758863] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.758908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.758951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.758995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.759038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.759081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.759128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.759171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.759213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.759256] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.759303] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.759348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.759393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.759490] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.759736] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.759791] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.759854] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.759900] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.759944] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.759983] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.760567] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.760856] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.760908] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.761025] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.761068] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.761113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.761157] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.761199] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.761242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.761285] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.761328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.761371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.761413] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.761497] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.761506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.761549] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.761557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.761602] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.761648] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.761694] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.761739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.761784] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.761830] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.762186] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.762230] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.762273] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.762317] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.762360] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.762425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.762512] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.762559] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.762843] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.762882] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.763171] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.763224] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.763264] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.763320] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.763720] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.764047] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.764091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.764134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.764176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.764219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.764261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.764304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.764346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.764389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.764431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.764511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.764557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.764905] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.764949] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.766369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.766413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.766488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.767257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.767300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.768044] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.768089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.769150] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.771239] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.772217] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.789097] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.789151] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.789321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.789689] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.789835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.805738] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.824224] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.824334] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.824418] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.824797] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.824841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.824885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.824927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.824970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.825012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.825059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.825102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.825144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.825188] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.825234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.825279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.825324] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.825382] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.825424] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.825512] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.825575] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.825628] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.825672] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.825711] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.826261] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.826469] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.826517] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.826636] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.826679] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.826724] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.826767] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.826809] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.826853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.826896] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.826939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.826982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.827024] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.827066] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.827073] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.827114] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.827120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.827163] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.827206] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.827248] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.827291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.827333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.827378] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.827419] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.827496] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.827543] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.827590] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.827635] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.827697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.827750] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.827794] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.827938] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.827977] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.828268] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.828323] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.828364] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.828422] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.828770] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.829091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.829135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.829178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.829221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.829263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.829307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.829350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.829392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.829483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.829528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.829576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.829621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.829699] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.829742] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.831183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.831227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.831271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.832147] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.832192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.833241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.835327] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.836304] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.853186] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.853241] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.853410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.853903] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.854045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.869826] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.888319] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.888429] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.888741] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.889068] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.889111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.889155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.889197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.889240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.889282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.889329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.889372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.889415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.889493] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.889544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.889592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.889639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.889842] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.889885] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.889939] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.890000] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.890045] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.890088] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.890127] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.890710] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.891003] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.891051] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.891171] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.891214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.891258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.891302] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.891344] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.891387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.891430] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.891510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.891557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.891603] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.891646] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.891655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.891698] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.891707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.891752] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.891796] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.892150] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.892193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.892236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.892282] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.892325] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.892369] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.892412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.892486] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.892534] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.892600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.892659] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.892703] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.892845] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.892883] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.893173] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.893227] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.893269] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.893326] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.893736] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.894058] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.894102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.894145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.894187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.894230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.894272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.894315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.894357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.894399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.894477] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.894526] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.894573] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.894948] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.894993] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.896417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.896478] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.896524] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.897275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.897317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.898060] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.898104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.899159] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.901248] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.902267] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.919133] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.919187] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.919357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.919724] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.919866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.935775] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.954263] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.954372] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.954632] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.954955] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.954998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.955042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.955084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.955127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.955169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.955216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.955259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.955302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.955344] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.955391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.955471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.955518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.955579] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.955859] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.955915] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.955979] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.956025] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.956069] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 570.956108] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 570.956696] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.956987] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.957039] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.957158] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 570.957201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 570.957246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 570.957290] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 570.957332] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 570.957375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.957418] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 570.957498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.957544] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 570.957589] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.957633] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 570.957646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.957688] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 570.957900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.957952] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 570.957996] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 570.958039] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 570.958082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 570.958125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 570.958170] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 570.958213] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 570.958256] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.958300] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.958343] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.958387] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 570.958479] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.958532] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.958577] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.958945] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 570.958982] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 570.959272] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 570.959325] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.959365] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 570.959421] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 570.959871] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.960187] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 570.960231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 570.960274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.960316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.960359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.960402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 570.960488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 570.960534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 570.960577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 570.960762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 570.960810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 570.960856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.960931] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 570.960974] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.962432] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.962506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.962551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 570.963301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.963343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 570.964087] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 570.964131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 570.965177] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 570.967265] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 570.968261] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 570.985097] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 570.985151] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.985322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 570.985679] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 570.985825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.001753] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.020241] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.020351] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.020481] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.020812] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.020856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.020900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.020942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.020987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.021029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.021076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.021119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.021161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.021204] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.021251] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.021296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.021341] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.021398] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.021471] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.021527] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.021591] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.021636] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.021680] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 571.021720] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 571.022268] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.022461] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.022497] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.022616] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 571.022660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 571.022704] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 571.022748] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 571.022790] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 571.022834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.022876] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 571.022919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.022962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 571.023004] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.023045] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 571.023052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.023094] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 571.023099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.023142] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.023186] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 571.023229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 571.023271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 571.023313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.023359] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 571.023401] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 571.023478] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.023526] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.023573] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.023618] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.023681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.023734] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.023779] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.023921] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.023960] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.024252] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 571.024306] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.024348] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.024405] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.024888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.025207] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.025251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.025295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.025337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.025380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.025423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.025511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.025556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.025602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.025646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.025694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.025739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.025816] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.025860] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.027320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.027364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.027409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 571.028209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.028252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.028989] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 571.029032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 571.030075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 571.032165] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 571.033169] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.050047] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.050102] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.050271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.050699] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.050842] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.066683] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.085168] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.085278] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.085363] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.085692] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.085736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.085780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.085822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.085865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.085908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.085955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.085997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.086040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.086083] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.086130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.086174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.086219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.086277] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.086320] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.086373] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.086432] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.086509] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.086555] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 571.086595] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 571.087154] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.087324] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.087373] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.087528] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 571.087572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 571.087618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 571.087662] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 571.087705] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 571.087749] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.087793] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 571.087836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.087880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 571.087922] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.087965] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 571.087973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.088015] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 571.088021] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.088065] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.088109] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 571.088152] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 571.088195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 571.088238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.088283] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 571.088325] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 571.088368] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.088412] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.088483] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.088530] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.088593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.088646] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.088691] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.088834] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.088873] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.089167] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 571.089222] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.089263] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.089321] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.089635] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.089955] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.089999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.090042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.090084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.090127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.090169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.090212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.090254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.090297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.090340] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.090385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.090430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.090550] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.090594] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.092036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.092080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.092125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 571.092909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.092952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.093712] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 571.093756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 571.094809] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 571.096898] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 571.097934] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.114812] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.114866] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.115035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.115354] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.115551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.131488] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.149966] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.150076] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.150160] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.150485] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.150533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.150577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.150621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.150664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.150707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.150755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.150798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.150842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.150886] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.150933] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.150979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.151024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.151082] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.151125] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.151179] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.151242] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.151286] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.151330] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 571.151369] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 571.151948] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.152109] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.152160] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.152277] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 571.152321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 571.152366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 571.152409] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 571.152492] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 571.152538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.152584] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 571.152629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.152675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 571.152718] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.152765] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 571.152773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.152816] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 571.152823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.152867] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.152910] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 571.152954] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 571.152997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 571.153041] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.153087] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 571.153129] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 571.153173] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.153216] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.153261] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.153305] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.153368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.153420] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.153490] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.153639] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.153677] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.153970] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 571.154024] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.154066] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.154123] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.154431] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.154805] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.154850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.154893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.154935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.154978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.155020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.155063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.155106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.155150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.155193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.155239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.155283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.155357] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.155400] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.156872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.156915] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.156961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 571.157748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.157791] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.158643] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 571.158687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 571.159850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 571.161935] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 571.162958] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.179823] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.179878] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.180048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.180364] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.180791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.196493] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.214969] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.215079] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.215164] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.215486] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.215536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.215580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.215624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.215667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.215711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.215758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.215801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.215845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.215888] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.215936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.215983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.216028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.216088] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.216130] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.216184] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.216245] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.216289] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.216333] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 571.216371] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 571.216955] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.217116] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.217150] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.217271] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 571.217316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 571.217360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 571.217404] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 571.217485] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 571.217531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.217577] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 571.217621] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.217668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 571.217712] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.217754] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 571.217763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.217806] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 571.217814] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.217860] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.217903] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 571.217947] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 571.217990] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 571.218034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.218080] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 571.218122] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 571.218166] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.218210] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.218253] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.218296] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.218360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.218413] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.218485] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.218631] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.218669] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.218962] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 571.219016] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.219058] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.219116] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.219390] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.219754] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.219798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.219841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.219884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.219928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.219970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.220013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.220055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.220098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.220140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.220186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.220231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.220303] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.220346] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.221979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.222022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.222066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 571.222855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.222900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.223629] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 571.223674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 571.224853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 571.226946] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 571.228002] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.244860] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.244915] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.245086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.245457] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.245755] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.261498] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.279740] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.279852] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.279939] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.280260] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.280304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.280347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.280390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.280471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.280519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.280572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.280618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.280661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.280705] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.281156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.281202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.281247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.281311] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.281353] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.281408] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.281786] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.281836] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.281880] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:25 BXT-2 kernel: [ 571.281918] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:25 BXT-2 kernel: [ 571.283129] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.283319] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.283370] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.283832] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:25 BXT-2 kernel: [ 571.283880] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:25 BXT-2 kernel: [ 571.283925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:25 BXT-2 kernel: [ 571.283970] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:25 BXT-2 kernel: [ 571.284012] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:25 BXT-2 kernel: [ 571.284057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.284101] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:25 BXT-2 kernel: [ 571.284144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.284187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:25 BXT-2 kernel: [ 571.284229] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.284272] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:25 BXT-2 kernel: [ 571.284280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.284322] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:25 BXT-2 kernel: [ 571.284328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.284371] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:25 BXT-2 kernel: [ 571.284414] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:25 BXT-2 kernel: [ 571.284828] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:25 BXT-2 kernel: [ 571.284872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:25 BXT-2 kernel: [ 571.284916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:25 BXT-2 kernel: [ 571.284963] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:25 BXT-2 kernel: [ 571.285006] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:25 BXT-2 kernel: [ 571.285051] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.285096] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.285139] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.285183] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:25 BXT-2 kernel: [ 571.285257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.285314] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.285358] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.285939] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:25 BXT-2 kernel: [ 571.285981] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:25 BXT-2 kernel: [ 571.286275] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:25 BXT-2 kernel: [ 571.286330] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.286370] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:25 BXT-2 kernel: [ 571.286782] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:25 BXT-2 kernel: [ 571.287064] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.287396] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.287783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.287828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.287871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.287914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.287957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.288000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.288043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.288087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.288130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:25 BXT-2 kernel: [ 571.288181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:25 BXT-2 kernel: [ 571.288226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.288302] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.288345] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.290137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.290184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:25 BXT-2 kernel: [ 571.290229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:25 BXT-2 kernel: [ 571.291310] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:25 BXT-2 kernel: [ 571.291360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:25 BXT-2 kernel: [ 571.292619] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:25 BXT-2 kernel: [ 571.294736] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:25 BXT-2 kernel: [ 571.295853] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.312775] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:25 BXT-2 kernel: [ 571.312834] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.313007] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.313368] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:25 BXT-2 kernel: [ 571.313866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.329520] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:25 BXT-2 kernel: [ 571.348159] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:25 BXT-2 kernel: [ 571.348275] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:25 BXT-2 kernel: [ 571.348367] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.349005] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:25 BXT-2 kernel: [ 571.349053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:25 BXT-2 kernel: [ 571.349097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.349140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.349183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.349227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:25 BXT-2 kernel: [ 571.349277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:25 BXT-2 kernel: [ 571.349320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:25 BXT-2 kernel: [ 571.349363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:25 BXT-2 kernel: [ 571.349406] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.349825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.349874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.349922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.349990] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.350034] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.350089] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.350157] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.350205] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.350249] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.350288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.351485] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.351684] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.351739] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.351860] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.351904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.351950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.351994] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.352037] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.352081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.352125] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.352168] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.352212] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.352254] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.352297] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.352303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.352346] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.352351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.352395] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.352937] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.352982] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.353026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.353070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.353116] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.353159] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.353205] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.353249] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.353294] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.353337] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.353411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.353812] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.353856] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.354012] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.354050] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.354342] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.354396] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.354762] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.354822] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.355131] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.355772] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.355820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.355865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.355908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.355951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.355995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.356038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.356081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.356124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.356168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.356218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.356263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.356339] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.356382] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.358260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.358308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.358353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.359318] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.359367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.360621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.362740] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.363829] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.380753] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.380814] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.380986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.381392] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.381882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.397507] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.414186] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.414298] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.414386] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.414927] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.414975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.415018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.415061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.415104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.415147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.415195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.415237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.415280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.415323] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.415370] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.415416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.415851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.415918] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.415962] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.416018] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.416085] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.416132] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.416177] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.416216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.417446] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.418177] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.418236] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.418357] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.418402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.418788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.418834] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.418876] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.418921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.418967] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.419011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.419054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.419097] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.419139] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.419148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.419190] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.419196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.419240] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.419283] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.419326] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.419369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.419412] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.419869] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.419913] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.419960] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.420004] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.420049] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.420093] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.420174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.420232] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.420278] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.420855] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.420895] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.421183] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.421238] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.421278] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.421334] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.421865] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.422182] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.422226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.422269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.422312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.422355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.422397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.422731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.422774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.422818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.422862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.422912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.422958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.423033] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.423077] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.424767] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.424812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.424856] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.425781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.425825] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.426708] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.426753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.427981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.430126] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.431233] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.448185] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.448244] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.448418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.449191] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.449322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.464861] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.481569] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.481681] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.481769] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.482092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.482136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.482180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.482222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.482265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.482308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.482355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.482397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.482805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.482849] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.482902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.482949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.482996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.483060] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.483104] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.483158] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.483222] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.483268] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.483313] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.483351] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.484544] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.484737] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.484788] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.484908] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.484952] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.484997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.485041] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.485083] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.485128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.485171] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.485214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.485257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.485300] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.485341] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.485349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.485391] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.485851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.485913] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.485957] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.486001] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.486044] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.486087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.486133] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.486176] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.486220] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.486264] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.486308] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.486351] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.486419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.486783] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.486827] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.486984] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.487022] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.487311] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.487364] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.487404] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.487805] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.488069] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.488390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.488790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.488835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.488878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.488921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.488964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.489007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.489050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.489092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.489136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.489186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.489230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.489305] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.489348] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.491162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.491209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.491254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.492264] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.492310] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.493585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.495709] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.496814] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.513736] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.513794] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.513964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.514370] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.514850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.530426] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.549103] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.549216] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.549306] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.549915] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.549962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.550006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.550049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.550092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.550135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.550184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.550227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.550271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.550314] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.550361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.550407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.550813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.550879] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.550923] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.550978] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.551042] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.551088] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.551132] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.551171] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.552345] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.552761] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.552813] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.552934] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.552978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.553023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.553067] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.553109] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.553153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.553196] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.553239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.553282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.553324] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.553366] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.553373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.553415] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.553751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.553811] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.553856] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.553899] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.553943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.553986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.554032] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.554075] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.554119] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.554162] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.554206] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.554250] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.554319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.554374] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.554418] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.554969] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.555008] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.555299] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.555352] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.555393] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.555787] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.556042] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.556365] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.556408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.556745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.556788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.556831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.556874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.556917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.556960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.557003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.557047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.557096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.557140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.557215] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.557258] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.559000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.559047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.559092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.560154] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.560202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.561730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.563854] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.564972] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.581880] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.581939] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.582118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.582864] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.583029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.598615] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.617265] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.617381] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.617808] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.618143] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.618187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.618231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.618273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.618316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.618359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.618409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.618750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.618794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.618839] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.618892] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.618940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.618987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.619056] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.619100] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.619156] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.619222] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.619270] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.619315] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.619355] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.620552] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.620741] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.620795] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.620915] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.620958] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.621003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.621047] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.621089] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.621134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.621177] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.621220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.621263] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.621306] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.621348] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.621356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.621398] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.621863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.621924] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.621968] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.622012] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.622055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.622098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.622145] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.622187] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.622232] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.622275] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.622319] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.622362] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.622432] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.622814] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.622864] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.623088] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.623138] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.623834] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.624157] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.624199] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.624257] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.624869] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.625196] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.625240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.625284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.625327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.625369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.625412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.625509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.625553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.625842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.625887] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.625935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.625980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.626055] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.626099] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.627700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.627745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.627789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.628698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.628743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.629753] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.629800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.631155] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.633258] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.634248] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.651149] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.651206] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.651380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.651934] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.652065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.667745] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.685832] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.685944] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.686032] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.686355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.686399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.686487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.686533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.686577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.686623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.686671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.686714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.686759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.686803] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.686851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.686898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.686943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.687007] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.687049] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.687104] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.687167] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.687212] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.687256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.687295] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.687884] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.688062] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.688113] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.688241] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.688285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.688330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.688374] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.688416] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.688510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.688555] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.688598] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.688644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.688686] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.688729] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.688737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.688779] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.688785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.688828] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.688872] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.688915] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.688958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.689001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.689046] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.689089] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.689132] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.689176] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.689219] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.689263] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.689329] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.689384] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.689428] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.689656] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.689694] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.689987] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.690043] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.690083] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.690140] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.692690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.693017] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.693062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.693106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.693149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.693192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.693236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.693279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.693323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.693366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.693410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.693497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.693542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.693617] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.693661] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.695159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.695206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.695251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.696102] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.696151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.697230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.698514] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.699673] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.716623] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.716681] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.716853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.717180] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.717321] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.733189] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.750731] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.750846] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.750937] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.751268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.751313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.751357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.751400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.751490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.751534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.751587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.751629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.751673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.751717] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.751766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.751814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.751860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.751926] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.751969] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.752025] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.752089] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.752137] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.752181] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.752221] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.752816] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.753532] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.753584] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.753708] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.753752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.753797] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.753841] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.753884] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.753928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.753972] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.754015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.754058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.754100] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.754142] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.754151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.754192] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.754198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.754241] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.754284] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.754327] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.754369] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.754412] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.754508] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.754551] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.754594] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.754637] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.754680] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.754723] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.754791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.754847] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.754891] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.755757] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.755798] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.756089] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.756144] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.756184] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.756241] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.756725] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.757054] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.757098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.757141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.757184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.757227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.757269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.757312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.757355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.757398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.757614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.757663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.757708] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.757783] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.757828] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.759276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.759323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.759367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.760233] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.760280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.761395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.763551] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.764659] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.781555] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.781612] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.781784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.782118] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.783315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.798268] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.816609] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.816721] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.816810] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.817142] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.817187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.817230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.817273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.817315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.817358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.817406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.817644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.817687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.817732] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.817783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.817830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.817877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.817942] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.817986] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.818041] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.818104] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.818150] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.818194] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.818233] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.819631] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.819826] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.819882] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.820006] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.820050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.820094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.820138] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.820180] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.820225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.820268] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.820311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.820354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.820396] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.820600] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.820610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.820653] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.820659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.820703] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.820747] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.820790] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.820834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.820876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.820922] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.820966] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.821010] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.821053] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.821097] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.821140] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.821212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.821267] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.821312] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.821689] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.821729] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.822025] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.822080] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.822122] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.822180] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.823008] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.823343] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.823388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.823431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.824059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.824103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.824146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.824189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.824232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.824275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.824318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.824368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.824413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.825287] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.825331] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.829004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.829051] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.829096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.830026] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.830074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.831143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.832550] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.833635] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.850607] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.850665] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.850835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.851162] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.851315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.867158] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.884793] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.884906] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.884994] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.885316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.885360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.885403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.885503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.885547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.885590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.885639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.885682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.885725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.885768] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.885816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.885861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.885906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.885978] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.886022] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.886076] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.886143] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.886190] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.886233] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.886271] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.886868] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.887574] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.887624] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.887745] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.887788] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.887833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.887877] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.887919] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.887963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.888009] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.888053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.888096] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.888139] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.888180] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.888187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.888229] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.888235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.888278] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.888320] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.888363] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.888406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.888486] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.888532] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.888574] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.888618] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.888661] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.888704] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.888749] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.888811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.888864] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.888908] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.889051] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.889089] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.889378] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.889458] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.889499] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.889555] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.889957] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.890283] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.890326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.890369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.890412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.890509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.890553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.890596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.890639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.890682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.890726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.890773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.890818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.890893] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.890937] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.892430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.892500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.892545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.893300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.893342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.894089] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.894134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.895207] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.897293] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.898310] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.915183] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.915238] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.915407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.915782] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.915926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.931820] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.950289] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.950398] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.950531] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.950854] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.950898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.950941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.950984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.951027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.951069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.951116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.951159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.951201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.951244] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.951291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.951337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.951381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.951473] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.951516] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.951569] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.951630] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.951675] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.951719] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 571.951757] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 571.952310] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.952512] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.952563] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.952682] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 571.952726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 571.952770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 571.952814] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 571.952855] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 571.952899] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.952942] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 571.952984] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.953028] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 571.953070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.953112] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 571.953118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.953160] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 571.953166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.953209] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 571.953252] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 571.953295] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 571.953337] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 571.953379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 571.953424] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 571.953501] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 571.953545] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.953587] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.953631] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.953673] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 571.953735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.953786] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.953830] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.953968] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 571.954005] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 571.954295] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 571.954347] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.954389] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 571.954468] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 571.954900] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.955223] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.955267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 571.955310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.955352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.955395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.955487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 571.955530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 571.955574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 571.955616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 571.955660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 571.955707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 571.955752] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.955825] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 571.955869] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.957346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.957389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.957472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 571.958242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.958284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 571.959033] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 571.959078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 571.960124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 571.962210] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 571.963251] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 571.980130] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 571.980184] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.980353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 571.980841] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 571.980988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 571.996766] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.015237] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.015347] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.015431] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.015927] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.015970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.016014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.016056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.016099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.016142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.016189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.016231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.016274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.016317] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.016364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.016409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.016892] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.016952] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.016995] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.017048] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.017108] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.017151] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.017194] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 572.017235] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 572.018395] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.018575] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.018629] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.018748] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 572.018791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 572.018835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 572.018879] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 572.018921] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 572.018964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.019007] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 572.019050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.019093] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 572.019135] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.019177] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 572.019183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.019225] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 572.019231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.019274] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.019316] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 572.019359] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 572.019401] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 572.020166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.020212] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 572.020254] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 572.020297] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.020340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.020383] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.020425] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.020769] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.020822] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.020865] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.021009] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.021046] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.021334] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 572.021387] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.021749] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.021808] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.022035] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.022357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.022400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.022692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.022736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.022779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.022822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.022866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.022908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.022953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.022997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.023044] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.023089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.023163] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.023208] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.024625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.024671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.024716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 572.025542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.025586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.026307] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 572.026350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 572.027401] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 572.029499] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 572.030576] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.047527] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.047585] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.047756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.048095] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.048235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.064104] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.081690] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.081802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.081888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.082216] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.082260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.082303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.082346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.082388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.082431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.082519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.082562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.082607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.082650] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.082699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.082744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.082789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.082851] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.082893] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.082947] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.083008] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.083053] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.083096] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 572.083135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 572.083740] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.084479] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.084516] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.084640] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 572.084687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 572.084734] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 572.084777] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 572.084822] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 572.084867] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.084910] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 572.084953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.084996] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 572.085039] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.085081] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 572.085088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.085129] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 572.085135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.085178] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.085220] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 572.085263] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 572.085305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 572.085347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.085392] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 572.085484] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 572.085529] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.085572] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.085615] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.085659] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.085725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.085777] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.085821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.085964] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.086002] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.086291] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 572.086345] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.086386] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.086463] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.086868] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.087198] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.087243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.087286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.087329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.087372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.087415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.087609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.087652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.087696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.087740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.087789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.087833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.087909] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.087952] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.089959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.090005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.090049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 572.090908] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 572.090955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 572.092027] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 572.094123] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 572.095144] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.112021] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.112077] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.112248] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.112781] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.112924] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.128636] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.146797] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.146909] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.146999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.147327] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.147371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.147414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.147818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.147862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.147906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.147956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.147999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.148042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.148085] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.148132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.148178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.148223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.148286] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.148329] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.148383] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.149026] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.149082] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.149127] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 572.149166] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 572.150337] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.150683] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.150734] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.150857] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 572.150901] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 572.150946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 572.150989] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 572.151031] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 572.151076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.151119] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 572.151162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.151205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 572.151247] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.151289] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 572.151295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.151337] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 572.151343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.151386] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.151429] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 572.152162] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 572.152205] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 572.152247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.152292] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 572.152334] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 572.152378] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.152421] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.152748] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.152791] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.152860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.152914] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.152958] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.153103] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.153141] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.153794] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 572.154103] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.154144] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.154200] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.154691] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.155020] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.155063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.155107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.155149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.155192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.155234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.155277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.155320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.155362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.155405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.155905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.155950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.156025] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.156068] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.157738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.157784] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.157828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 572.158678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.158722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.159580] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 572.159625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 572.160804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 572.162903] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 572.163960] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.180875] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.180933] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.181108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.181705] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.181859] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.197503] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.216005] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.216121] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.216209] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.216778] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.216825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.216871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.216914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.216957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.217001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.217050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.217093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.217137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.217180] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.217228] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.217276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.217321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.217384] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.217701] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.217758] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.217822] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.217869] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.217912] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 572.217951] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 572.219124] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.219309] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.219363] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.219780] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 572.219825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 572.219871] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 572.219914] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 572.219956] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 572.220001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.220044] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 572.220087] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.220130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 572.220173] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.220215] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 572.220223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.220265] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 572.220271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.220314] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.220357] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 572.220400] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 572.220902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 572.220946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.220992] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 572.221034] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 572.221079] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.221123] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.221166] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.221210] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.221276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.221331] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.221375] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.221790] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.221829] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.222125] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 572.222181] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.222222] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.222280] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.222906] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.223233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.223278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.223321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.223364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.223407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.223878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.223922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.223965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.224007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.224051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.224101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.224146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.224221] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.224264] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.226201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.226256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.226302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 572.227336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:26 BXT-2 kernel: [ 572.227381] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:26 BXT-2 kernel: [ 572.228243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:26 BXT-2 kernel: [ 572.228287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:26 BXT-2 kernel: [ 572.229145] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 572.229190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 572.230244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 572.232334] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 572.233327] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.250210] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.250268] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.250654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.250989] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.251136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.266826] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.284744] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.284858] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.284946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.285264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.285308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.285351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.285394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.285479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.285525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.285574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.285619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.285663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.285706] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.285756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.285801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.285846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.285909] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.285951] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.286004] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.286066] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.286111] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.286154] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 572.286193] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:26 BXT-2 kernel: [ 572.286778] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.286953] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.286991] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.287110] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:26 BXT-2 kernel: [ 572.287156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:26 BXT-2 kernel: [ 572.287202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:26 BXT-2 kernel: [ 572.287247] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:26 BXT-2 kernel: [ 572.287292] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:26 BXT-2 kernel: [ 572.287337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.287382] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:26 BXT-2 kernel: [ 572.287426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.287646] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:26 BXT-2 kernel: [ 572.287690] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.287732] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:26 BXT-2 kernel: [ 572.287740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.287781] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:26 BXT-2 kernel: [ 572.287788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.287831] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:26 BXT-2 kernel: [ 572.287874] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:26 BXT-2 kernel: [ 572.287917] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:26 BXT-2 kernel: [ 572.287960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:26 BXT-2 kernel: [ 572.288003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:26 BXT-2 kernel: [ 572.288048] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:26 BXT-2 kernel: [ 572.288091] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:26 BXT-2 kernel: [ 572.288136] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.288179] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.288223] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.288266] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:26 BXT-2 kernel: [ 572.288332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.288387] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.288430] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.288652] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:26 BXT-2 kernel: [ 572.288690] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.288980] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:26 BXT-2 kernel: [ 572.289033] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.289075] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.289132] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.289407] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.289764] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.289808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.289852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.289895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.289937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.289980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.290023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.290065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.290108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.290151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.290200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.290245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.290320] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.290363] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.291986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.292032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:26 BXT-2 kernel: [ 572.292076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:26 BXT-2 kernel: [ 572.292979] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:26 BXT-2 kernel: [ 572.293024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:26 BXT-2 kernel: [ 572.294164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:26 BXT-2 kernel: [ 572.295660] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:26 BXT-2 kernel: [ 572.296706] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.313648] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.313706] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.313880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.314231] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.314373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.330204] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:26 BXT-2 kernel: [ 572.347882] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:26 BXT-2 kernel: [ 572.347995] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.348086] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.348405] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:26 BXT-2 kernel: [ 572.348503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:26 BXT-2 kernel: [ 572.348808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.348851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.348894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.348938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:26 BXT-2 kernel: [ 572.348987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:26 BXT-2 kernel: [ 572.349030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:26 BXT-2 kernel: [ 572.349074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:26 BXT-2 kernel: [ 572.349117] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:26 BXT-2 kernel: [ 572.349165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:26 BXT-2 kernel: [ 572.349210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:26 BXT-2 kernel: [ 572.349256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:26 BXT-2 kernel: [ 572.349318] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:26 BXT-2 kernel: [ 572.349360] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.349415] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:26 BXT-2 kernel: [ 572.349526] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:26 BXT-2 kernel: [ 572.349572] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:26 BXT-2 kernel: [ 572.349615] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:26 BXT-2 kernel: [ 572.349654] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.350863] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.351712] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.351764] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.351886] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.351930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.351974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.352018] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.352060] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.352103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.352146] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.352189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.352232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.352274] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.352316] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.352323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.352364] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.352370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.352413] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.352515] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.352560] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.352605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.352649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.352697] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.352742] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.352789] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.352835] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.352879] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.353373] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.353655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.353711] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.353754] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.353911] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.353948] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.354238] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.354292] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.354332] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.354390] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.355083] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.355410] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.355761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.355805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.355848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.355890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.355934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.355977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.356020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.356062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.356105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.356155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.356200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.356275] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.356318] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.360094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.360140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.360184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.362816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:27 BXT-2 kernel: [ 572.362863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:27 BXT-2 kernel: [ 572.363784] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:27 BXT-2 kernel: [ 572.363829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:27 BXT-2 kernel: [ 572.364662] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.364707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.365873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.367970] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.368979] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.385860] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.385918] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.386089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.386470] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.386611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.402592] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.420819] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.420930] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.421018] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.421338] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.421382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.421425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.421825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.421869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.421912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.421961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.422004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.422047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.422090] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.422137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.422182] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.422227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.422290] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.422332] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.422385] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.422955] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.423007] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.423052] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.423090] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.424262] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.424565] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.424619] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.424746] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.424789] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.424833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.424877] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.424919] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.424962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.425005] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.425048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.425091] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.425133] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.425175] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.425182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.425223] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.425229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.425272] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.425315] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.425357] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.425400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.426193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.426240] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.426282] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.426328] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.426372] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.426415] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.426714] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.426787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.426843] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.426886] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.427036] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.427073] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.427362] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.427415] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.427817] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.427876] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.428157] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.428779] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.428825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.428869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.428911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.428954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.428997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.429040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.429083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.429125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.429168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.429216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.429261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.429336] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.429379] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.431350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.431394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.431610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.432385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.432428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.433357] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.433401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.434622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.436716] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.437779] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.454670] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.454725] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.454895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.455227] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.455369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.471419] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.489827] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.489939] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.490027] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.490345] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.490389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.490432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.490841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.490885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.490928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.490977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.491020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.491063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.491106] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.491153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.491198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.491243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.491306] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.491349] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.491402] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.491979] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.492027] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.492071] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.492109] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.493274] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.493557] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.493614] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.493736] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.493779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.493825] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.493868] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.493910] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.493954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.493997] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.494039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.494082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.494125] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.494166] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.494176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.494218] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.494223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.494266] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.494310] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.494353] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.494395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.495162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.495207] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.495249] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.495293] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.495336] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.495379] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.495421] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.495773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.495828] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.495872] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.496019] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.496056] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.496345] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.496398] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.496778] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.496839] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.497119] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.497642] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.497688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.497732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.497774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.497817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.497860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.497903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.497946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.497988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.498031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.498078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.498122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.498196] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.498239] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.500187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.500232] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.500276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.501141] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.501186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.502243] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.504338] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.505363] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.522253] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.522311] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.522727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.523138] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.523269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.538876] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.556795] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.556908] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.556998] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.557328] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.557373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.557416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.557836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.557880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.557923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.557974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.558017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.558060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.558103] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.558150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.558196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.558240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.558308] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.558351] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.558406] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.559036] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.559086] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.559130] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.559169] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.560339] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.560685] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.560735] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.560898] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.560963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.561013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.561060] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.561104] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.561150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.561197] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.561240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.561283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.561325] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.561367] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.561376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.561418] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.562058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.562127] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.562170] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.562213] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.562256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.562298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.562343] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.562386] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.562430] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.562886] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.562930] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.562972] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.563042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.563096] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.563140] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.563293] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.563331] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.564047] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.564366] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.564407] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.564702] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.564960] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.565292] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.565337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.565380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.565423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.565814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.565857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.565900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.565943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.565986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.566029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.566079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.566124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.566200] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.566243] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.568156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.568202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.568247] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.569314] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.569359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.570549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.572474] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.573514] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.590406] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.590509] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.590680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.591011] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.591152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.607117] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.624769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.624882] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.624970] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.625289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.625333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.625376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.625419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.625501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.625546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.625593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.625639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.625684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.625727] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.625774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.625821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.625866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.625925] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.625967] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.626020] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.626083] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.626128] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.626173] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.626212] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.626793] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.626966] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.627021] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.627140] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.627186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.627233] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.627278] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.627322] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.627368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.627412] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.627516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.627559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.627602] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.627644] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.627652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.627693] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.627702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.627746] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.627790] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.627834] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.627877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.627920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.627966] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.628008] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.628055] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.628098] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.628143] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.628188] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.628252] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.628305] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.628349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.628514] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.628551] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.628842] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.628895] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.628936] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.628992] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.629332] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.629825] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.629871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.629915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.629958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.630001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.630044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.630087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.630131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.630174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.630219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.630267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.630312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.630387] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.630430] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.632042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.632086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.632130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.632922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.632967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.633768] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.633816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.634902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.637005] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.638037] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.654940] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.654998] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.655169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.655820] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.655983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.671547] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.689845] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.689958] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.690045] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.690368] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.690412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.690774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.690817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.690860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.690903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.690952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.690995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.691037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.691630] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.691684] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.691730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.691774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.691840] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.691883] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.691936] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.691997] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.692041] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.692084] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.692123] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.693417] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.693625] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.693679] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.693800] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.693844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.693889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.693933] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.693975] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.694019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.694063] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.694105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.694148] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.694191] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.694232] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.694241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.694282] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.694288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.694332] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.694374] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.694417] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.695246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.695289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.695335] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.695377] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.695421] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.695742] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.695785] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.695828] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.695899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.695953] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.695997] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.696147] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.696185] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.696957] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.697331] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.697393] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.697736] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.698268] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.698858] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.698904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.698948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.698991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.699034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.699077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.699120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.699162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.699205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.699248] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.699296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.699340] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.699415] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.699944] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.701386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.701430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.701659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.702426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.702635] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.703385] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.703430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.704735] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.706827] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.707872] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.724751] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.724808] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.724978] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.725308] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.725431] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.741540] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.759769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.759881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.759968] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.760295] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.760339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.760382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.760425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.760854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.760897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.760948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.760990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.761033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.761076] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.761123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.761168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.761213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.761276] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.761318] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.761371] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.761431] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.761991] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.762035] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.762073] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.763241] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.763533] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.763584] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.763706] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.763749] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.763794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.763837] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.763879] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.763923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.763966] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.764008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.764052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.764094] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.764136] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.764142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.764184] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.764190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.764233] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.764275] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.764318] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.764360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.764402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.765191] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.765233] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.765279] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.765322] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.765367] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.765409] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.765745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.765799] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.765843] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.765998] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.766036] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.766324] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.766378] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.766418] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.766827] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.767066] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.767385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.767429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.767709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.767752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.767795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.767838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.767880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.767923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.767965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.768008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.768056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.768100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.768174] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.768217] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.770103] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.770148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.770191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.771021] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.771065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.772126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.774225] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.775257] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.792161] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.792219] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.792389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.792949] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.793092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.808770] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.827299] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.827411] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.827570] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.827898] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.827943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.827986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.828029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.828071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.828114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.828161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.828204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.828247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.828290] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.828337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.828383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.828428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.828519] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.828562] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.828616] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.828678] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.828722] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.828765] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.828803] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.829355] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.829563] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.829620] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.829740] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.829784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.829829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.829873] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.829916] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.829961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.830004] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.830048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.830092] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.830134] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.830177] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.830184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.830226] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.830233] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.830276] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.830319] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.830362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.830405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.830474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.830519] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.830562] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.830605] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.830648] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.830692] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.830735] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.830796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.830848] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.830892] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.831709] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.831748] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.832038] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.832093] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.832135] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.832193] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.833041] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.833417] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.834112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.834157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.834200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.834244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.834288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.834332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.834375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.834419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.834824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.834876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.834920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.834997] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.835040] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.836795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.836840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.836885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.837848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.837898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.838778] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.838825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.840134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.842254] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.843299] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.860226] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.860310] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.860813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.861172] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.861319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.876814] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.894892] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.895006] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.895094] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.895417] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.895542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.895830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.895873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.895915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.895959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.896008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.896050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.896093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.896136] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.896183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.896230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.896275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.896340] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.896383] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.896482] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.896549] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.896596] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.896985] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.897025] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.897631] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.898519] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.898576] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.898696] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.898740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.898785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.898829] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.898871] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.898915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.898958] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.899001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.899044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.899086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.899128] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.899136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.899178] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.899184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.899227] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.899269] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.899312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.899355] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.899397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.899501] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.899547] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.899592] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.899638] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.899683] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.899729] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.899797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.900233] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.900279] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.900473] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.900514] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.900962] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.903614] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.903659] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.903717] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.903986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.904315] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.904358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.904401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.904495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.904539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.904587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.904632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.904676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.904721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.904765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.905089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.905134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.905210] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.905254] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.906812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.906858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.906903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.907887] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.907941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.909034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.910531] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.911613] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.928539] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.928597] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.928769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.929096] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.929235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.945248] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.962686] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.962798] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.962886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.963204] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.963248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.963292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.963334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.963377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.963420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.963506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.963552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.963602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.963647] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.963696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.963744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.963792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.963854] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.963898] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.963952] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.964015] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.964063] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.964107] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 572.964147] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 572.964779] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.966188] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.966245] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.966373] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 572.966417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 572.966542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 572.966590] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 572.966633] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 572.966679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.966723] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 572.966769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.966813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 572.966855] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.966897] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 572.966905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.966947] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 572.966953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.966996] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 572.967041] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 572.967084] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 572.967128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 572.967170] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 572.967216] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 572.967259] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 572.967303] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.967346] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.967389] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.967469] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 572.967536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.967591] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.967635] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.967783] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 572.967822] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 572.968113] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 572.968167] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.968208] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 572.968266] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 572.968568] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.968893] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 572.968937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 572.968980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.969022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.969066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.969109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 572.969152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 572.969194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 572.969238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 572.969281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 572.969327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 572.969371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.969528] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 572.969573] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.971016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.971060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.971106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 572.971912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.971955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 572.972712] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 572.972756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 572.973817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 572.975908] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 572.976942] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 572.993836] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 572.993893] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.994064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 572.994374] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 572.994548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.010479] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.028909] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.029020] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.029106] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.029429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.029513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.029559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.029607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.029650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.029696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.029744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.029787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.029831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.029875] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.029923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.029969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.030014] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.030077] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.030120] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.030175] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.030236] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.030281] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.030325] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 573.030364] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 573.030950] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.031120] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.031171] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.031289] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 573.031333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 573.031378] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 573.031422] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 573.031528] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 573.031576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.031620] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 573.031663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.031707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 573.031750] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.031792] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 573.031800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.031843] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 573.031849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.031893] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.031936] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 573.031980] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 573.032023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 573.032066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.032112] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 573.032154] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 573.032198] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.032241] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.032284] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.032328] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.032393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.032475] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.032520] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.032670] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.032708] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.033010] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 573.033068] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.033110] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.033169] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.033422] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.033806] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.033852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.033895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.033938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.033981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.034024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.034067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.034110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.034153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.034196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.034246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.034291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.034367] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.034411] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.036566] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.036627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.036682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 573.037521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.037567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.038314] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 573.038358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 573.039439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 573.041570] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 573.042608] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.059518] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.059577] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.059751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.060063] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.060203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.076125] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.093707] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.093820] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.093909] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.094233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.094278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.094321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.094364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.094407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.094515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.094564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.094607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.094650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.094694] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.094741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.094786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.094831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.094895] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.094937] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.094991] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.095053] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.095097] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.095140] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 573.095179] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 573.095768] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.095964] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.096020] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.096143] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 573.096187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 573.096232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 573.096277] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 573.096319] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 573.096363] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.096406] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 573.096518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.096562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 573.096604] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.096645] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 573.096654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.096696] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 573.096702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.096745] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.096788] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 573.096831] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 573.096873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 573.096915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.096960] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 573.097002] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 573.097045] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.097088] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.097131] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.097173] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.097242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.097297] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.097340] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.100006] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.100046] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.100338] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 573.100393] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.100982] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.101042] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.101302] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.102128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.102177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.102221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.102263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.102306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.102350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.102392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.103053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.103096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.103139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.103189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.103234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.103309] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.103352] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.106512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.106560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.106604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 573.107380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.107423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.108336] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 573.108380] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 573.109943] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 573.111479] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 573.112536] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.129433] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.129535] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.129707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.130037] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.130180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.146052] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.163781] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.163894] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.163982] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.164315] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.164360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.164403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.164538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.164580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.164624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.164673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.164716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.164759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.164802] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.164849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.164895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.164940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.165004] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.165046] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.165100] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.165160] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.165204] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.165247] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 573.165286] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 573.165885] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.166595] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.166632] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.166754] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 573.166797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 573.166842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 573.166885] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 573.166928] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 573.166972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.167016] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 573.167058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.167102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 573.167144] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.167187] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 573.167196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.167238] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 573.167244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.167287] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.167330] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 573.167374] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 573.167417] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 573.167508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.167553] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 573.167596] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 573.167640] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.167683] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.167726] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.167770] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.167839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.167892] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.167936] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.168081] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.168119] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.168407] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 573.168483] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.168525] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.168583] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.168970] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.169296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.169340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.169384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.169427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.169569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.169612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.169656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.169699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.169742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.169785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.169833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.169878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.169952] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.169995] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.172091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.172137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.172182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 573.172984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.173028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.173826] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 573.173870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 573.174917] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 573.176684] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 573.177719] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.194630] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.194688] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.194858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.195169] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.195305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.211226] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.228716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.228829] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.228917] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.229245] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.229289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.229332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.229375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.229418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.229804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.229855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.229898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.229942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.229985] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.230033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.230081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.230126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.230188] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.230231] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.230285] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.230347] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.230392] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.230813] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 573.230852] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 573.231408] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.232184] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.232233] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.232354] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 573.232398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 573.232750] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 573.232794] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 573.232836] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 573.232880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.232926] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 573.232969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.233012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 573.233055] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.233097] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 573.233105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.233147] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 573.233153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.233196] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.233239] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 573.233789] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 573.233832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 573.233875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.233921] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 573.233963] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 573.234008] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.234052] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.234096] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.234139] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.234206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.234260] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.234304] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.234775] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.234814] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.235113] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 573.235169] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.235209] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.235266] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.235897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.236217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.236261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.236304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.236347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.236390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.236433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.236775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.236819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.236862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.236906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.236955] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.237000] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.237076] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.237119] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.240585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.240631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.240676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 573.241424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.241513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.242303] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 573.242348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 573.243429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 573.245562] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 573.246600] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.263517] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.263576] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.263749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.264079] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.264218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.280186] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.297001] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.297113] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.297201] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.297527] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.297572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.297615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.297659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.297702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.297746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.297795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.297838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.297881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.297925] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.297973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.298018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.298063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.298125] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.298167] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.298221] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.298282] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.298326] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.298370] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:27 BXT-2 kernel: [ 573.298408] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:27 BXT-2 kernel: [ 573.298986] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.299161] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.299214] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.299335] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:27 BXT-2 kernel: [ 573.299378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:27 BXT-2 kernel: [ 573.299423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:27 BXT-2 kernel: [ 573.299517] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:27 BXT-2 kernel: [ 573.299561] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:27 BXT-2 kernel: [ 573.299605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.299649] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:27 BXT-2 kernel: [ 573.299693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.299736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:27 BXT-2 kernel: [ 573.299779] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.299821] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:27 BXT-2 kernel: [ 573.299829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.299871] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:27 BXT-2 kernel: [ 573.299877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.299921] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:27 BXT-2 kernel: [ 573.299964] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:27 BXT-2 kernel: [ 573.300008] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:27 BXT-2 kernel: [ 573.300050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:27 BXT-2 kernel: [ 573.300093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:27 BXT-2 kernel: [ 573.300138] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:27 BXT-2 kernel: [ 573.300181] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:27 BXT-2 kernel: [ 573.300224] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.300268] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.300310] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.300354] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:27 BXT-2 kernel: [ 573.300416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.300491] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.300535] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.300680] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:27 BXT-2 kernel: [ 573.300717] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:27 BXT-2 kernel: [ 573.301007] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:27 BXT-2 kernel: [ 573.301060] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.301101] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:27 BXT-2 kernel: [ 573.301158] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:27 BXT-2 kernel: [ 573.301971] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.302296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.302340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:27 BXT-2 kernel: [ 573.302383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.302426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.302531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.302575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:27 BXT-2 kernel: [ 573.302618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:27 BXT-2 kernel: [ 573.302661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:27 BXT-2 kernel: [ 573.302705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:27 BXT-2 kernel: [ 573.302748] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:27 BXT-2 kernel: [ 573.302796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:27 BXT-2 kernel: [ 573.302841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.302916] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:27 BXT-2 kernel: [ 573.302959] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.304796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.304841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.304886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:27 BXT-2 kernel: [ 573.305719] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.305763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:27 BXT-2 kernel: [ 573.307077] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:27 BXT-2 kernel: [ 573.307126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:27 BXT-2 kernel: [ 573.308305] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:27 BXT-2 kernel: [ 573.309580] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:27 BXT-2 kernel: [ 573.310688] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:27 BXT-2 kernel: [ 573.327578] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:27 BXT-2 kernel: [ 573.327637] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.327809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:27 BXT-2 kernel: [ 573.328142] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:27 BXT-2 kernel: [ 573.328284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:27 BXT-2 kernel: [ 573.344206] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.361704] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.361818] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.361907] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.362234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.362278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.362321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.362364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.362407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.362887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.362939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.362982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.363025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.363068] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.363116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.363162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.363206] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.363269] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.363312] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.363366] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.363428] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.363907] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.363952] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.363991] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.365162] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.365355] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.365391] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.365809] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.365853] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.365898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.365943] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.365985] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.366030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.366073] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.366116] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.366159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.366201] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.366243] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.366252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.366294] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.366300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.366343] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.366386] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.366429] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.366925] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.366968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.367013] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.367056] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.367101] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.367144] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.367188] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.367231] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.367299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.367353] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.367396] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.367870] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.367908] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.368202] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.368256] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.368297] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.368354] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.368955] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.369284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.369328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.369371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.369414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.369774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.369818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.369861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.369904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.369947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.369990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.370041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.370086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.370162] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.370205] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.372035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.372081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.372126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.373028] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.373074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.374145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.376252] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.377248] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.394145] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.394204] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.394376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.394773] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.394917] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.410832] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.428854] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.428967] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.429055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.429379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.429422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.429523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.429566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.429612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.429655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.429701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.429744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.429787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.429830] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.429877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.429924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.429970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.430033] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.430076] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.430130] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.430191] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.430236] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.430279] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.430318] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.430899] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.431065] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.431114] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.431235] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.431278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.431323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.431367] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.431409] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.431495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.431540] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.431583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.431626] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.431669] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.431711] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.431720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.431761] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.431767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.431811] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.431854] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.431897] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.431940] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.431983] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.432028] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.432070] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.432114] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.432158] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.432201] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.432245] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.432309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.432362] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.432406] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.432576] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.432614] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.432904] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.432956] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.432997] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.433054] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.433888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.434211] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.434255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.434298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.434341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.434383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.434426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.434510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.434555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.434597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.434641] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.434688] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.434733] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.434808] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.434851] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.436605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.436650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.436695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.437479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.437523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.438255] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.438300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.439618] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.441737] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.442791] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.459670] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.459728] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.459900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.460231] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.460368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.476299] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.493702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.493817] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.493906] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.494230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.494274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.494317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.494360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.494403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.494634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.494685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.494729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.494773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.494816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.494865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.494913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.494960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.495027] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.495070] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.495125] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.495188] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.495235] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.495279] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.495318] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.496566] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.497212] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.497266] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.497389] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.497432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.497628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.497673] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.497716] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.497761] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.497807] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.497852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.497897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.497940] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.497983] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.497991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.498034] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.498041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.498085] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.498128] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.498172] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.498215] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.498258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.498304] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.498347] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.498391] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.498669] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.498716] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.498759] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.498828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.498884] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.498928] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.499084] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.499123] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.499414] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.500055] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.500096] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.500153] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.500752] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.501628] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.501677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.501721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.501763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.501806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.501850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.501893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.501936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.501979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.502022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.502071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.502116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.502192] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.502235] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.504097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.504143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.504187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.505050] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.505094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.506146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.508242] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.509252] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.526148] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.526206] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.526378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.526783] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.526934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.542828] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.561358] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.561520] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.561613] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.561932] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.561976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.562019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.562062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.562105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.562147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.562194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.562236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.562281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.562324] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.562371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.562416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.562492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.562554] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.562598] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.562652] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.562715] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.562761] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.562805] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.562844] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.563403] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.564125] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.564182] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.564307] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.564350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.564395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.564480] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.564526] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.564572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.564617] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.564662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.564706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.564752] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.564795] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.564803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.564845] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.564851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.564895] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.564939] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.564983] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.565027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.565070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.565115] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.565158] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.565201] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.565244] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.565287] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.565331] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.565396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.565477] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.565522] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.565666] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.565705] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.566002] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.566058] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.566100] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.566158] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.566889] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.567215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.567259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.567302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.567344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.567387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.567430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.567860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.567903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.567946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.567989] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.568039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.568084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.568160] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.568203] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.570109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.570154] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.570199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.571321] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.571383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.572912] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.574507] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.575571] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.592499] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.592557] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.592727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.593038] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.593158] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.609157] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.627108] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.627221] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.627309] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.627637] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.627682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.627726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.627768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.627811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.627856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.627904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.627947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.627990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.628034] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.628081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.628127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.628173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.628236] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.628279] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.628333] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.628395] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.628473] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.628517] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.628556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.629107] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.629279] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.629329] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.629495] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.629539] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.629585] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.629629] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.629672] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.629717] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.629760] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.629804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.629847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.629890] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.629932] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.629940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.629982] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.629988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.630032] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.630075] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.630118] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.630161] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.630204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.630249] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.630292] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.630335] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.630378] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.630421] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.630492] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.630557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.630609] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.630653] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.630801] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.630839] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.632385] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.632846] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.632888] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.632945] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.633236] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.633570] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.633616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.633659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.633702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.633745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.633790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.633832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.633875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.633918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.633961] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.634008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.634053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.634127] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.634170] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.636068] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.636114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.636158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.637033] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.637078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.638135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.640232] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.641269] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.658158] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.658215] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.658385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.659120] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.659347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.674862] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.692790] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.692902] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.692989] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.693314] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.693358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.693401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.693498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.693808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.693853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.693902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.693945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.693989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.694032] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.694080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.694126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.694173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.694235] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.694278] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.694333] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.694393] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.694516] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.694632] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.694674] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.695848] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.696036] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.696088] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.696201] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.696244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.696289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.696334] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.696376] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.696420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.696534] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.696577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.696623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.696665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.696707] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.696714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.696756] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.696762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.696805] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.696848] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.696891] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.696936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.696978] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.697024] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.697067] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.697110] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.697154] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.697197] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.697491] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.697561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.697617] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.697661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.697785] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.697822] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.698112] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.698166] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.698208] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.698265] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.698508] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.698832] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.698877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.698922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.698967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.699010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.699055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.699098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.699140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.699183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.699226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.699274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.699318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.699395] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.699485] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.702845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.702891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.702936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.703829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.703873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.704982] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.705048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.706379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.708629] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.709666] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.726559] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.726616] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.726787] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.727124] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.727263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.743243] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.760785] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.760897] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.760984] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.761307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.761353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.761396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.761487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.761530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.761575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.761622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.761665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.761708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.761751] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.761800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.761845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.761890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.761954] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.761996] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.762050] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.762112] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.762157] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.762200] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.762239] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.762855] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.763562] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.763618] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.763739] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.763783] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.763829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.763872] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.763914] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.763958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.764002] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.764044] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.764087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.764129] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.764171] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.764178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.764220] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.764225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.764268] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.764311] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.764353] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.764396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.764487] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.764534] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.764578] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.764625] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.764670] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.764715] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.764759] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.764823] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.764876] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.764922] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.765074] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.765112] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.765409] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.765503] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.765545] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.765602] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.766048] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.766370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.766414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.766709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.766752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.766796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.766839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.766883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.766926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.766969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.767013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.767060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.767105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.767179] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.767223] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.769113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.769157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.769202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.770068] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.770114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.771266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.772566] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.773624] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.790581] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.790640] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.790814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.791232] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.791362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.807136] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.824885] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.825000] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.825089] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.825409] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.825537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.825584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.825627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.825671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.825715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.825766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.825809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.825853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.825897] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.825946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.825994] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.826039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.826107] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.826152] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.826207] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.826269] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.826316] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.826360] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.826399] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.826991] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.827175] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.827226] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.827348] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.827391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.827668] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.827714] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.827758] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.827803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.827849] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.827893] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.827937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.827980] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.828022] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.828032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.828075] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.828081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.828125] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.828168] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.828212] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.828254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.828297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.828343] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.828386] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.828429] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.828500] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.828543] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.828586] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.828655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.828710] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.828754] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.829079] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.829119] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.829414] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.830049] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.830092] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.830147] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.830711] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.831052] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.831096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.831140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.831182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.831225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.831268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.831311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.831354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.831396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.831592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.831642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.831688] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.831766] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.831810] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.833341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.833386] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.833431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.834561] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.834606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.835370] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.835417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.836825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.838496] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.839561] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.856448] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.856553] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.856726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.857058] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.857197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.873088] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.890832] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.890946] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.891033] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.891353] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.891397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.891496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.891540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.891922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.891965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.892013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.892056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.892100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.892143] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.892190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.892235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.892279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.892341] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.892383] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.892481] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.892544] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.892740] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.892784] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.892823] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.893370] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.893691] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.893740] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.893856] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.893899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.893944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.893988] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.894030] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.894073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.894116] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.894159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.894202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.894244] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.894286] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.894293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.894334] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.894340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.894383] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.894426] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.894504] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.894549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.894597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.894643] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.894688] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.894734] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.894780] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.894826] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.894871] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.894935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.895344] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.895388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.895687] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.895727] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.896020] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.896074] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.896116] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.896174] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.896492] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.896969] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.897014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.897057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.897099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.897141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.897184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.897227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.897269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.897312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.897354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.897401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.897479] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.897554] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.897604] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.899018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.899064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.899108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.899920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.899965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.900850] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.900894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.902009] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.904110] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.905180] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.922067] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.922125] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.922298] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.922679] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.922825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.938831] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.956769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.956883] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.956972] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.957294] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.957339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.957383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.957426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.957524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.957574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.957623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.957668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.957713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.957757] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.957807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.957854] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.957902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.957964] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.958008] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.958062] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.958124] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.958169] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.958214] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 573.958253] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 573.958839] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.959019] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.959072] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.959193] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 573.959237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 573.959281] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 573.959324] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 573.959366] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 573.959410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.959489] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 573.959535] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.959582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 573.959626] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.959668] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 573.959678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.959721] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 573.959729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.959772] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 573.959817] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 573.959863] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 573.959906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 573.959950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 573.959995] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 573.960038] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 573.960082] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.960125] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.960168] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.960212] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 573.960275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.960329] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.960373] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.960546] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 573.960585] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 573.960884] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 573.960938] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.960980] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 573.961038] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 573.961404] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.961767] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 573.961812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 573.961855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.961898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.961940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.961983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 573.962026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 573.962068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 573.962110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 573.962153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 573.962200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 573.962244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.962319] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 573.962361] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.963873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.963917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.963962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 573.964770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.964813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 573.965544] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 573.965589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 573.966631] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 573.968524] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 573.969582] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 573.986501] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 573.986560] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.986732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 573.987052] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 573.987197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.003104] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.020791] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.020903] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.020990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.021310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.021354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.021397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.021478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.021523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.021569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.021617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.021661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.021704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.021750] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.021797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.021842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.021887] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.021948] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.021991] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.022046] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.022109] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.022155] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.022198] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 574.022237] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 574.022823] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.022994] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.023043] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.023166] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 574.023210] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 574.023255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 574.023299] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 574.023341] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 574.023385] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.023429] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 574.023519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.023563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 574.023606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.023648] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 574.023656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.023698] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 574.023704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.023748] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.023791] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 574.023834] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 574.023877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 574.023921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.023966] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 574.024008] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 574.024052] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.024095] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.024138] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.024181] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.024246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.024300] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.024344] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.024544] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.024582] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.024872] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 574.024926] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.024968] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.025025] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.025831] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.026159] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.026203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.026246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.026288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.026331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.026374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.026417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.026529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.026572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.026615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.026663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.026708] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.026784] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.026827] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.028568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.028613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.028657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 574.029410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.029502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.030380] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 574.030425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 574.031534] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 574.033627] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 574.034676] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.051562] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.051620] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.051792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.052100] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.052235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.068300] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.085898] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.086012] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.086103] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.086419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.086826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.086870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.086914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.086959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.087006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.087056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.087101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.087145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.087190] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.087238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.087283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.087328] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.087392] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.087475] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.087531] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.087595] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.087639] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.087682] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 574.087721] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 574.088278] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.088499] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.088554] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.088676] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 574.088719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 574.088765] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 574.088809] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 574.088852] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 574.088896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.088940] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 574.088983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.089027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 574.089069] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.089112] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 574.089119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.089162] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 574.089168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.089212] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.089255] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 574.089298] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 574.089341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 574.089383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.089428] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 574.089496] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 574.089540] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.089584] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.089627] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.089670] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.089732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.089784] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.089828] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.089976] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.090014] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.090303] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 574.090357] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.090396] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.090557] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.090969] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.091296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.091342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.091385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.091428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.091529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.091574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.091617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.091661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.091704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.091749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.091798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.091843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.091919] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.091962] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.093523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.093567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.093612] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 574.094366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.094408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.095214] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 574.095259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 574.096503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 574.098608] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 574.099680] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.116601] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.116658] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.116830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.117167] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.117307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.133191] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.151766] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.151881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.151971] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.152295] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.152339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.152382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.152425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.152955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.153024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.153084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.153129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.153172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.153216] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.153265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.153311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.153356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.153429] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.153998] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.154053] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.154119] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.154169] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.154211] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 574.154250] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 574.155421] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.156143] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.156199] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.156322] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 574.156366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 574.156411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 574.156787] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 574.156831] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 574.156877] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.156923] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 574.156966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.157009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 574.157052] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.157094] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 574.157103] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.157145] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 574.157151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.157194] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.157237] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 574.157280] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 574.157322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 574.157364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.157409] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 574.158130] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 574.158176] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.158220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.158263] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.158305] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.158374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.158428] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.158811] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.158970] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.159007] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.159304] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 574.159360] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.159400] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.159875] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.160112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.160599] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.160645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.160689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.160732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.160775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.160818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.160860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.160903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.160945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.160988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.161036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.161080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.161154] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.161197] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.163051] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.163095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.163139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 574.164048] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 574.164093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 574.165141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 574.167238] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 574.168253] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.185132] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.185189] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.185360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.185901] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.186047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.201828] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.219785] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.219899] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.219987] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.220311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.220355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.220398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.220810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.220853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.220897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.220946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.220989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.221032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.221075] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.221122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.221167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.221212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.221275] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.221317] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.221370] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.221430] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.222026] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.222070] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 574.222110] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 574.223276] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.223613] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.223652] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.223777] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 574.223821] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 574.223866] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 574.223910] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 574.223952] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 574.223995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.224038] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 574.224081] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.224124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 574.224166] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.224208] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 574.224214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.224256] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 574.224262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.224305] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.224348] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 574.224390] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 574.225119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 574.225163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.225209] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 574.225250] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 574.225294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.225339] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.225382] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.225745] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.225820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.225874] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.225917] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.226065] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.226102] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.226390] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 574.227028] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.227070] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.227126] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.227379] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.227817] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.227863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.227906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.227948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.227993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.228036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.228078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.228121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.228165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.228208] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.228255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.228299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.228373] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.228416] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.230345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.230391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.230496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 574.231270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.231313] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.237048] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 574.237097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 574.238175] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 574.239588] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 574.240692] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.257597] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.257654] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.257826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.258153] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.258288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.274224] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.291706] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.291821] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.291911] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.292234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.292279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.292323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.292366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.292408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.292488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.292542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.292587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.292635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.292680] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.292728] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.292776] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.292821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.292883] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.292926] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.292980] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.293042] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.293087] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.293132] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:28 BXT-2 kernel: [ 574.293171] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:28 BXT-2 kernel: [ 574.293807] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.294503] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.294557] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.294680] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:28 BXT-2 kernel: [ 574.294724] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:28 BXT-2 kernel: [ 574.294770] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:28 BXT-2 kernel: [ 574.294815] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:28 BXT-2 kernel: [ 574.294858] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:28 BXT-2 kernel: [ 574.294903] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.294947] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:28 BXT-2 kernel: [ 574.294991] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.295035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:28 BXT-2 kernel: [ 574.295078] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.295121] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:28 BXT-2 kernel: [ 574.295130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.295172] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:28 BXT-2 kernel: [ 574.295179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.295223] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:28 BXT-2 kernel: [ 574.295266] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:28 BXT-2 kernel: [ 574.295310] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:28 BXT-2 kernel: [ 574.295353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:28 BXT-2 kernel: [ 574.295396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:28 BXT-2 kernel: [ 574.295481] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:28 BXT-2 kernel: [ 574.295526] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:28 BXT-2 kernel: [ 574.295571] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.295616] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.295661] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.295707] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:28 BXT-2 kernel: [ 574.295775] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.295831] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.295878] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.296066] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:28 BXT-2 kernel: [ 574.296105] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:28 BXT-2 kernel: [ 574.296398] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:28 BXT-2 kernel: [ 574.297271] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.297313] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:28 BXT-2 kernel: [ 574.297370] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:28 BXT-2 kernel: [ 574.297733] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.298066] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.298111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:28 BXT-2 kernel: [ 574.298154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.298199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.298245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.298290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:28 BXT-2 kernel: [ 574.298333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:28 BXT-2 kernel: [ 574.298376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:28 BXT-2 kernel: [ 574.298419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:28 BXT-2 kernel: [ 574.298516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:28 BXT-2 kernel: [ 574.298565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:28 BXT-2 kernel: [ 574.298609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.298685] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:28 BXT-2 kernel: [ 574.298729] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.300129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.300172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.300216] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:28 BXT-2 kernel: [ 574.301017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.301061] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:28 BXT-2 kernel: [ 574.301794] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:28 BXT-2 kernel: [ 574.301838] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:28 BXT-2 kernel: [ 574.302875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:28 BXT-2 kernel: [ 574.304962] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:28 BXT-2 kernel: [ 574.305998] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:28 BXT-2 kernel: [ 574.322949] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:28 BXT-2 kernel: [ 574.323027] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.323219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:28 BXT-2 kernel: [ 574.323752] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:28 BXT-2 kernel: [ 574.323935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:28 BXT-2 kernel: [ 574.339601] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.357791] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.357905] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.357991] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.358312] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.358356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.358399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.358515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.358560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.358603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.358651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.358695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.358738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.358782] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.358829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.358875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.358920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.358983] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.359026] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.359080] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.359140] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.359185] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.359228] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.359267] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.359857] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.360036] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.360091] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.360215] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.360259] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.360304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.360347] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.360389] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.360482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.360527] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.360571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.360614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.360657] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.360699] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.360708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.360751] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.360757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.360800] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.360843] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.360887] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.360930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.360973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.361018] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.361060] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.361103] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.361147] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.361190] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.361233] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.361297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.361352] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.361396] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.361564] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.361602] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.361891] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.361945] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.361987] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.362044] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.365052] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.365388] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.365434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.365529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.365578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.365624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.365671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.365715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.365758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.365806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.365850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.365900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.365945] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.366021] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.366065] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.371081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.371128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.371173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.371960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.372005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.372915] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.372962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.374146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.375527] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.376614] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.393532] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.393590] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.393762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.394068] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.394207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.410166] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.427772] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.427885] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.427973] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.428304] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.428349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.428392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.428515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.428558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.428606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.428659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.428704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.428748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.428793] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.428841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.428888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.428932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.428995] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.429038] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.429091] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.429151] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.429196] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.429239] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.429277] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.429875] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.430581] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.430619] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.430738] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.430782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.430827] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.430871] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.430914] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.430959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.431003] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.431046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.431089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.431132] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.431175] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.431182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.431224] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.431230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.431274] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.431317] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.431360] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.431403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.431477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.431527] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.431571] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.431617] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.431663] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.431710] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.431756] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.431819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.431871] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.431917] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.432062] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.432100] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.432389] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.432468] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.432512] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.432568] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.432849] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.433174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.433218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.433261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.433304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.433347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.433390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.433467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.433511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.433558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.433603] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.433652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.433698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.433774] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.433817] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.435260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.435303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.435348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.436118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.436162] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.436883] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.436929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.437974] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.440061] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.441099] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.457991] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.458048] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.458218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.458592] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.458733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.474641] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.492716] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.492828] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.492916] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.493237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.493283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.493326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.493369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.493412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.493490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.493542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.493588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.493633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.493679] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.493729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.493775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.493824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.493886] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.493928] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.493982] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.494042] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.494087] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.494131] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.494170] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.494755] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.494928] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.494980] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.495097] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.495140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.495184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.495228] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.495270] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.495313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.495356] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.495399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.495500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.495543] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.495586] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.495593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.495635] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.495641] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.495685] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.495728] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.495772] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.495814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.495857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.495902] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.495945] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.495988] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.496032] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.496075] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.496118] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.496179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.496232] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.496276] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.496420] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.496481] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.496771] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.496825] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.496867] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.496924] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.497236] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.497593] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.497638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.497681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.497723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.497765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.497808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.497851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.497893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.497936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.497979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.498025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.498069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.498142] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.498186] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.499621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.499665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.499709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.500486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.500532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.501255] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.501299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.502325] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.503481] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.504501] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.521398] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.521490] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.521662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.521996] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.522136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.538006] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.556511] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.556622] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.556709] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.557028] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.557073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.557116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.557159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.557202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.557244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.557290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.557333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.557376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.557419] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.557513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.557561] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.557607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.557668] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.557711] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.557765] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.557826] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.557870] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.557913] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.557952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.558562] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.559227] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.559280] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.559402] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.559491] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.559539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.559586] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.559629] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.559674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.559718] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.559762] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.559807] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.559850] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.559893] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.559901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.559943] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.559949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.559994] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.560037] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.560081] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.560124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.560167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.560213] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.560256] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.560300] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.560343] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.560386] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.560430] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.560518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.560573] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.560616] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.561832] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.561872] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.562166] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.562222] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.562263] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.562321] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.562867] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.563203] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.563248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.563292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.563335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.563378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.563421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.563516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.563560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.563604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.563647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.563698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.563743] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.563820] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.563864] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.565645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.565691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.565736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.566824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.566870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.567637] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.567683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.568828] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.570509] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.571541] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.588425] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.588521] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.588693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.589027] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.589172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.605085] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.622699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.622810] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.622897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.623218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.623262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.623305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.623347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.623392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.623470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.623520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.623569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.623614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.623659] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.623708] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.623756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.623803] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.623864] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.623908] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.623962] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.624025] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.624071] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.624116] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.624155] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.624736] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.624912] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.624966] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.625085] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.625128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.625172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.625215] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.625257] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.625301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.625343] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.625386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.625429] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.625721] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.625764] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.625773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.625816] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.625823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.625867] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.625910] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.625954] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.625997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.626040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.626085] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.626127] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.626175] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.626218] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.626261] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.626305] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.626369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.626423] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.626500] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.626649] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.626687] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.626978] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.627034] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.627076] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.627134] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.627480] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.627811] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.627855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.627898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.627940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.627985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.628027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.628071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.628114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.628156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.628199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.628245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.628290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.628363] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.628406] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.629880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.629924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.629969] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.630749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.630792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.631507] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.631551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.632599] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.634692] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.635744] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.652613] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.652671] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.652843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.653166] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.653297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.669247] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.686718] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.686831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.686920] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.687266] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.687325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.687377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.687423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.687524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.687570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.687628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.687672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.687715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.687762] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.687810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.687858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.687904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.687968] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.688011] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.688073] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.688152] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.688217] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.688269] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.688316] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.689507] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.689701] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.689752] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.689872] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.689916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.689962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.690006] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.690049] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.690094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.690138] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.690181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.690225] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.690267] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.690309] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.690318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.690360] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.690366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.690409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.690497] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.690543] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.690587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.690630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.690676] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.690720] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.690765] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.690810] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.690855] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.690901] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.690968] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.691022] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.691068] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.691224] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.691263] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.691594] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.691652] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.691692] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.691751] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.692244] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.692680] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.692726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.692770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.692814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.692857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.692901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.692945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.692989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.693032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.693076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.693125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.693171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.693246] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.693289] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.695050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.695094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.695138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.695931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.695975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.696741] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.696786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.697888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.699980] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.700996] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.717874] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.717932] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.718104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.718508] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.718656] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.734627] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.752759] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.752873] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.752963] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.753303] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.753347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.753391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.753499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.753546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.753591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.753643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.753686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.753731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.753775] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.753822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.753868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.753912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.753975] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.754019] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.754073] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.754135] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.754181] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.754224] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.754263] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.754844] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.755013] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.755066] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.755188] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.755232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.755277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.755321] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.755364] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.755408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.755718] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.755762] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.755807] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.755849] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.755891] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.755901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.755942] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.755949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.755992] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.756036] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.756079] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.756122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.756165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.756210] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.756253] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.756296] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.756340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.756383] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.756426] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.756559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.756614] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.756658] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.756810] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.756848] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.757137] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.757191] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.757232] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.757290] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.757993] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.758320] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.758364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.758407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.758808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.758851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.758894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.758937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.758980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.759023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.759066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.759115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.761516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.761599] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.761642] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.763065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.763110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.763154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.764033] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.764079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.765239] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.766489] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.767536] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.784433] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.784587] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.784763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.785127] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.785272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.801151] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.818699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.818812] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.818900] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.819226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.819270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.819313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.819356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.819399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.819500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.819549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.819592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.819636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.819680] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.819728] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.819774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.819819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.819881] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.819924] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.819985] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.820047] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.820093] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.820136] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.820175] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.820788] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.821497] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.821555] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.821677] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.821722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.821771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.821815] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.821858] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.821903] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.821946] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.821990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.822034] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.822076] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.822118] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.822127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.822169] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.822175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.822220] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.822264] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.822307] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.822350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.822393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.822503] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.822548] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.822593] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.822638] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.822682] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.822726] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.822793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.822846] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.822890] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.823981] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.824021] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.824316] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.824372] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.824412] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.824575] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.824855] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.825184] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.825229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.825272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.825314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.825357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.825400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.825504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.825550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.825595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.825640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.825963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.826008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.826084] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.826127] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.827714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.827758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.827802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.828699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.828743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.829613] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.829658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.830861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.832957] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.834024] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.850981] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.851064] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.851281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.851926] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.852053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.867620] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.885882] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.885995] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.886083] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.886402] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.886501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.886550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.886595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.886638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.886686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.886735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.886778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.886822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.886865] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.886913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.886958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.887003] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.887068] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.887110] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.887163] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.887224] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.887269] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.887312] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.887351] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.887938] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.888112] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.888164] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.888278] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.888321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.888365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.888408] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.888484] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.888532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.888577] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.888622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.888668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.888711] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.888753] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.888760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.888802] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.888809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.888852] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.888895] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.888939] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.888981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.889025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.889070] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.889112] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.889156] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.889199] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.889242] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.889285] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.889345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.889398] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.889466] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.889614] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.889652] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.889941] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.889994] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.890034] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.890168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.890792] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.891117] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.891161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.891204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.891246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.891289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.891332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.891374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.891417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.891502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.891548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.891598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.891645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.891719] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.891763] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.893227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.893274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.893319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.894117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.894161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.894913] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.894959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.896028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.898159] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.899225] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.916121] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.916177] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.916349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.916755] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.916897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.932739] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.951401] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.951656] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.951761] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.952086] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.952131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.952175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.952219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.952262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.952305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.952354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.952397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.952959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.953003] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.953056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.953101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.953146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.953210] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.953253] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.953306] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.953367] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.953412] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.953924] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 574.953963] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 574.955132] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.955322] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.955375] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.955761] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 574.955806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 574.955851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 574.955895] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 574.955937] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 574.955981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.956024] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 574.956067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.956110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 574.956152] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.956194] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 574.956203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.956244] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 574.956250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.956293] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 574.956336] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 574.956378] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 574.956421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 574.957161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 574.957208] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 574.957250] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 574.957294] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.957337] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.957380] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.957423] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 574.957923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.957979] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.958023] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.958180] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 574.958218] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 574.958862] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 574.959170] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.959211] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 574.959267] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 574.959698] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.960025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 574.960068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 574.960111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.960154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.960197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.960239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 574.960282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 574.960324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 574.960367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 574.960410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 574.960901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 574.960946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.961021] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 574.961064] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.962725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.962769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.962813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 574.963674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.963717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 574.964610] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 574.964654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 574.965845] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 574.967939] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 574.968942] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 574.985835] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 574.985894] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.986066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 574.986390] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 574.986828] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.002628] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.020803] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.020917] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.021006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.021323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.021367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.021410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.021811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.021855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.021898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.021948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.021990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.022033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.022076] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.022124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.022169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.022214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.022276] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.022319] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.022372] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.022432] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.023011] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.023056] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 575.023094] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 575.024259] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.024573] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.024629] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.024757] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 575.024800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 575.024845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 575.024889] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 575.024931] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 575.024975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.025018] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 575.025060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.025104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 575.025146] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.025188] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 575.025194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.025236] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 575.025242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.025285] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.025327] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 575.025370] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 575.025412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 575.026149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.026196] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 575.026239] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 575.026283] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.026327] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.026370] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.026414] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.026552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.026608] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.026651] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.026778] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.026816] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.027116] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 575.027170] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.027211] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.027268] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.027535] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.027868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.027913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.027957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.028000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.028043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.028086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.028129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.028173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.028216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.028259] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.028306] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.028351] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.028425] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.028512] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.029937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.029980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.030025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 575.030868] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 575.030913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 575.031986] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 575.033494] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 575.034533] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.051590] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.051647] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.051819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.052166] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.052313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.068069] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.085900] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.086013] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.086101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.086421] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.086521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.086566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.086609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.086652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.086696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.086744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.086788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.086833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.086876] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.086924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.086969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.087015] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.087078] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.087120] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.087174] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.087235] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.087279] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.087322] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 575.087361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 575.087949] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.088125] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.088172] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.088295] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 575.088339] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 575.088384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 575.088428] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 575.088510] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 575.088555] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.088599] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 575.088642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.088686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 575.088729] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.088772] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 575.088779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.088822] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 575.088828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.088872] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.088915] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 575.088958] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 575.089001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 575.089044] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.089089] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 575.089132] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 575.089177] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.089220] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.089264] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.089308] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.089371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.089424] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.089486] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.089630] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.089668] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.089958] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 575.090012] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.090053] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.090110] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.090637] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.090971] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.091015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.091058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.091101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.091143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.091186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.091229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.091272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.091314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.091357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.091404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.091507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.091584] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.091627] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.093691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.093737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.093781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 575.094691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.094734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.095616] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 575.095661] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 575.096839] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 575.098934] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 575.099955] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.116874] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.116944] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.117154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.117901] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.118057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.133477] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.151902] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.152014] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.152102] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.152425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.152512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.152557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.152600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.152642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.152685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.152735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.152778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.152821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.152865] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.152913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.152958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.153004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.153070] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.153113] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.153166] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.153227] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.153272] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.153315] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 575.153354] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 575.153941] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.154918] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.154969] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.155089] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 575.155133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 575.155178] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 575.155221] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 575.155263] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 575.155308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.155350] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 575.155393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.155479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 575.155522] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.155564] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 575.155571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.155614] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 575.155620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.155664] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.155707] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 575.155750] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 575.155793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 575.155836] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.155881] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 575.155924] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 575.155967] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.156011] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.156054] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.156097] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.156160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.156213] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.156257] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.156401] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.156463] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.156775] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 575.156830] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.156872] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.156929] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.157804] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.158135] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.158179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.158222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.158265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.158308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.158351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.158393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.158541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.158585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.158629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.158678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.158723] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.158800] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.158843] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.160560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.160605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.160650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 575.161860] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 575.161908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 575.163169] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 575.164531] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 575.165714] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.182621] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.182679] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.182871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.183257] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.183400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.199260] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.217735] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.217848] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.217936] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.218266] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.218310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.218353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.218396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.218831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.218876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.218926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.218968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.219011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.219054] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.219101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.219147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.219192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.219256] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.219299] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.219353] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.219415] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.220050] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.220094] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 575.220133] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 575.221304] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.221628] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.221684] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.221808] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 575.221852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 575.221897] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 575.221940] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 575.221983] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 575.222028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.222071] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 575.222114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.222157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 575.222199] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.222241] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 575.222248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.222291] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 575.222297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.222340] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.222383] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 575.222426] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 575.223268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 575.223311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.223357] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 575.223399] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 575.223685] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.223728] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.223771] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.223814] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.223884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.223939] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.223982] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.224141] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.224179] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.224902] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 575.225220] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.225261] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.225319] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.225919] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.226250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.226294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.226337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.226380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.226423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.226863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.226906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.226949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.226991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.227035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.227085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.227130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.227207] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.227251] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.229118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.229164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.229209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 575.230260] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 575.230308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 575.231656] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 575.233477] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 575.234520] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.251409] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.251497] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.251670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.251995] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.252136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.268038] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.285752] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.285864] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.285952] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.286271] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.286316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.286359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.286402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.286514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.286557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.286606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.286649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.286693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.286736] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.286784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.286830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.286875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.286936] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.286979] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.287033] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.287094] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.287139] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.287182] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:29 BXT-2 kernel: [ 575.287221] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:29 BXT-2 kernel: [ 575.287825] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.288536] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.288575] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.288696] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:29 BXT-2 kernel: [ 575.288740] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:29 BXT-2 kernel: [ 575.288785] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:29 BXT-2 kernel: [ 575.288828] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:29 BXT-2 kernel: [ 575.288870] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:29 BXT-2 kernel: [ 575.288914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.288958] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:29 BXT-2 kernel: [ 575.289000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.289043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:29 BXT-2 kernel: [ 575.289086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.289127] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:29 BXT-2 kernel: [ 575.289134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.289176] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:29 BXT-2 kernel: [ 575.289182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.289224] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:29 BXT-2 kernel: [ 575.289267] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:29 BXT-2 kernel: [ 575.289309] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:29 BXT-2 kernel: [ 575.289352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:29 BXT-2 kernel: [ 575.289394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:29 BXT-2 kernel: [ 575.289485] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:29 BXT-2 kernel: [ 575.289530] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:29 BXT-2 kernel: [ 575.289575] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.289620] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.289665] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.289710] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:29 BXT-2 kernel: [ 575.289773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.289824] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.289869] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.290013] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:29 BXT-2 kernel: [ 575.290051] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:29 BXT-2 kernel: [ 575.290348] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:29 BXT-2 kernel: [ 575.290402] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.290480] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:29 BXT-2 kernel: [ 575.290538] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:29 BXT-2 kernel: [ 575.290858] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.291181] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.291225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:29 BXT-2 kernel: [ 575.291270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.291312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.291356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.291399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:29 BXT-2 kernel: [ 575.291495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:29 BXT-2 kernel: [ 575.291540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:29 BXT-2 kernel: [ 575.291584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:29 BXT-2 kernel: [ 575.291627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:29 BXT-2 kernel: [ 575.291676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:29 BXT-2 kernel: [ 575.291721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.291796] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:29 BXT-2 kernel: [ 575.291839] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.293258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.293304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.293349] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:29 BXT-2 kernel: [ 575.294400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.294740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:29 BXT-2 kernel: [ 575.295598] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:29 BXT-2 kernel: [ 575.295643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:29 BXT-2 kernel: [ 575.296785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:29 BXT-2 kernel: [ 575.298880] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:29 BXT-2 kernel: [ 575.299941] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:29 BXT-2 kernel: [ 575.316834] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:29 BXT-2 kernel: [ 575.316891] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.317061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:29 BXT-2 kernel: [ 575.317388] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:29 BXT-2 kernel: [ 575.317689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:29 BXT-2 kernel: [ 575.333640] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.350750] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.350862] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.350949] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.351271] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.351316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.351358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.351401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.351483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.351528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.351574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.351617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.351660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.351704] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.351752] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.351797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.351842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.351907] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.351949] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.352003] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.352065] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.352110] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.352153] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.352192] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.352806] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.353520] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.353571] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.353694] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.353738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.353783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.353828] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.353870] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.353915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.353959] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.354002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.354046] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.354089] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.354131] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.354139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.354182] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.354188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.354232] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.354275] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.354318] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.354361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.354404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.354476] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.354519] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.354562] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.354605] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.354648] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.354692] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.354754] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.354808] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.354851] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.355003] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.355040] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.355330] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.355383] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.355425] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.355502] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.355910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.356240] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.356284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.356327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.356370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.356413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.356607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.356650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.356693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.356736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.356779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.356828] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.356873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.356948] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.356991] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.359350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.359397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.359929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.361109] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.361157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.362373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.364499] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.365782] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.382673] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.382730] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.382900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.383224] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.383362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.399367] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.416793] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.416908] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.416996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.417328] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.417373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.417416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.417525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.417572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.417616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.417667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.417710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.417755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.417799] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.417846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.417892] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.417937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.418000] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.418043] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.418097] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.418160] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.418205] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.418248] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.418287] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.418906] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.419598] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.419653] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.419771] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.419814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.419859] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.419903] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.419945] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.419990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.420034] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.420079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.420130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.420181] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.420229] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.420240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.420292] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.420298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.420350] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.420399] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.420537] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.420584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.420629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.420676] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.420720] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.420765] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.420810] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.420855] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.420901] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.420970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.421024] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.421069] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.423371] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.423412] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.423915] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.423972] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.424013] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.424069] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.424347] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.424836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.424881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.424925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.424968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.425011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.425054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.425097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.425139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.425182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.425225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.425272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.425316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.425391] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.425943] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.427380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.427424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.427674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.428571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.428614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.429339] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.429382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.430710] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.432803] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.433794] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.450700] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.450758] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.450930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.451242] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.451383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.467321] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.484700] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.484812] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.484900] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.485218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.485262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.485305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.485348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.485390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.485488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.485536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.485580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.485623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.485668] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.485715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.485762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.485807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.485868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.485911] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.485965] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.486027] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.486072] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.486116] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.486155] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.486792] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.487483] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.487521] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.487643] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.487686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.487731] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.487775] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.487817] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.487861] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.487904] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.487947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.487990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.488032] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.488074] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.488081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.488122] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.488128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.488171] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.488214] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.488256] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.488298] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.488341] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.488385] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.488427] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.488503] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.488548] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.488591] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.488634] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.488697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.488751] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.488795] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.488944] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.488982] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.489272] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.489326] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.489369] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.489447] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.489848] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.490178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.490222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.490266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.490309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.490353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.490396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.490599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.490643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.490687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.490731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.490781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.490827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.490903] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.490947] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.492628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.492673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.492717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.493501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.493545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.494283] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.494327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.495523] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.497643] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.498760] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.515657] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.515716] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.515888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.516310] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.516802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.532268] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.549692] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.549805] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.549892] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.550214] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.550258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.550301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.550344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.550387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.550430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.550522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.550568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.550612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.550657] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.550706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.550754] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.550799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.550861] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.550903] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.550957] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.551017] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.551063] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.551106] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.551145] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.551730] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.551905] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.551959] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.552075] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.552119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.552164] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.552208] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.552251] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.552295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.552339] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.552382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.552426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.552494] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.552537] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.552545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.552587] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.552593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.552637] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.552680] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.552723] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.552766] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.552809] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.552854] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.552897] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.552940] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.552983] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.553026] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.553070] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.553131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.553183] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.553227] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.553399] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.553492] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.553782] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.553836] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.553878] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.553936] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.554962] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.555296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.555340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.555383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.555426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.555535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.555579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.555621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.555664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.555707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.555750] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.555799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.555844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.555919] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.555962] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.558008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.558054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.558099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.558964] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.559011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.560134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.562262] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.563324] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.580217] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.580274] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.580516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.580825] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.580971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.596849] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.614702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.614814] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.614901] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.615218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.615262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.615306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.615348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.615391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.615489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.615538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.615580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.615624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.615667] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.615715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.615760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.615805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.615870] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.615912] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.615966] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.616027] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.616071] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.616114] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.616154] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.616741] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.616916] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.616968] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.617090] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.617133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.617178] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.617222] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.617264] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.617308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.617351] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.617396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.617485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.617528] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.617571] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.617578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.617620] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.617627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.617670] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.617715] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.617758] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.617801] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.617844] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.617890] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.617933] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.617976] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.618020] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.618062] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.618106] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.618171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.618224] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.618268] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.618415] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.618475] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.618765] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.618819] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.618860] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.618918] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.619351] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.619793] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.619840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.619884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.619926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.619970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.620013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.620056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.620098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.620143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.620185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.620234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.620278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.620352] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.620395] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.622022] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.622067] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.622111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.622926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.622970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.623745] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.623789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.624903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.627004] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.628042] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.644939] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.644998] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.645168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.645886] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.646043] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.661555] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.679766] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.679880] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.679968] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.680291] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.680335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.680379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.680422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.680528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.680572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.680623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.680666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.680709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.680753] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.680801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.680849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.680894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.680961] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.681005] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.681059] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.681120] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.681165] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.681208] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.681247] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.681833] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.682009] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.682064] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.682186] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.682229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.682275] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.682319] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.682361] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.682405] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.682526] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.682569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.682613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.682655] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.682698] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.682705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.682746] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.682753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.682796] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.682839] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.682883] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.682926] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.682968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.683013] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.683056] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.683101] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.683145] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.683189] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.683233] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.683296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.683349] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.683393] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.683736] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.683774] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.684063] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.684117] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.684159] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.684216] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.686692] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.687014] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.687058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.687102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.687144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.687187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.687230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.687273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.687316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.687359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.687402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.687591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.687636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.687713] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.687756] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.689759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.689804] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.689849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.690663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.690707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.691426] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.691519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.692579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.694678] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.695718] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.712604] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.712662] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.712834] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.713152] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.713280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.731627] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.747796] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.747909] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.747997] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.748326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.748370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.748414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.748526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.748571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.748614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.748664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.748707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.748750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.748794] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.748842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.748889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.748934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.748997] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.749040] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.749094] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.749155] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.749200] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.749242] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.749281] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.749916] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.750602] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.750653] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.750774] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.750818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.750864] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.750909] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.750951] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.750996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.751040] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.751083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.751127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.751169] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.751212] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.751219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.751261] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.751268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.751311] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.751354] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.751398] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.751475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.751520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.751566] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.751611] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.751656] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.751701] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.751746] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.751791] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.751854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.751909] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.751952] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.752103] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.752141] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.752472] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.752530] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.752570] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.752627] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.752924] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.753251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.753297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.753342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.753385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.753428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.753555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.753598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.753641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.753683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.753727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.753775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.753821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.753896] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.753941] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.755374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.755418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.755512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.756285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.756328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.757116] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.757160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.758222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.760327] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.761361] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.778267] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.778324] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.778888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.779223] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.779358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.794873] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.812891] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.813004] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.813091] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.813411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.813767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.813811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.813853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.813896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.813939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.813988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.814031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.814073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.814117] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.814164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.814209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.814254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.814317] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.814360] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.814414] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.815115] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.815165] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.815208] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.815247] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.816415] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.816624] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.816679] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.816800] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.816843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.816888] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.816932] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.816974] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.817018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.817061] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.817104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.817147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.817190] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.817231] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.817239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.817281] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.817287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.817331] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.817373] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.817416] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.818308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.818351] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.818396] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.818663] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.818709] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.818752] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.818795] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.818838] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.818909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.818964] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.819008] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.819173] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.819211] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.819996] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.820314] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.820355] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.820412] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.820985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.821309] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.821353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.821396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.821742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.821785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.821828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.821871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.821914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.821957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.822004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.822068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.822122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.822215] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.822267] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.825891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.825937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.825982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.826982] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.827028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.828071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.829495] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.830534] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.847427] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.847521] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.847694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.848015] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.848156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.864065] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.881789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.881903] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.881991] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.882316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.882361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.882404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.882576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.882812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.882856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.882907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.882950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.882994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.883037] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.883085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.883133] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.883178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.883240] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.883283] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.883338] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.883399] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.883484] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.883527] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.883566] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.884776] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.885498] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.885553] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.885671] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.885717] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.885762] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.885806] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.885848] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.885896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.885941] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.885985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.886029] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.886291] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.886333] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.886343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.886385] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.886391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.886519] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.886563] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.886606] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.886651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.886693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.886741] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.886783] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.886827] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.886870] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.886914] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.886957] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.887025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.887080] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.887124] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.887266] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.887303] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.887620] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.887674] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.887715] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.887773] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.888442] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.889040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.889087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.889132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.889175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.889218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.889262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.889305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.889349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.889392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.889720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.889771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.889816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.889893] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.889936] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.891397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.891481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.891526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.892286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.892328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.893227] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.893273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.894415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.896564] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.897626] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.915323] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.915381] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.915630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.915968] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.916098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.931215] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.948762] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.948874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.948961] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.949283] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.949327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.949371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.949413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.949513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.949556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.949605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.949648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.949691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.949734] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.949782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.949827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.949874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.949937] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.949980] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.950034] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.950097] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.950143] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.950186] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 575.950226] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 575.950814] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.950984] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.951032] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.951154] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 575.951198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 575.951242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 575.951286] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 575.951329] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 575.951373] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.951417] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 575.951507] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.951551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 575.951593] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.951635] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 575.951643] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.951685] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 575.951691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.951734] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 575.951778] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 575.951821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 575.951864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 575.951907] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 575.951952] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 575.951995] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 575.952039] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.952082] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.952126] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.952168] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 575.952237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.952291] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.952334] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.952523] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 575.952560] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 575.952850] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 575.952904] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.952944] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 575.953001] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 575.953838] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.954173] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.954218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 575.954261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.954304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.954347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.954390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 575.954432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 575.954850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 575.954894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 575.954937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 575.954987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 575.955032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.955107] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 575.955150] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.957514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.957561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.957605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 575.958389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.958991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 575.960259] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 575.960322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 575.961832] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 575.963930] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 575.964977] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 575.981858] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 575.981916] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.982088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 575.982744] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 575.982900] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 575.998506] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.016686] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.016799] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.016886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.017207] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.017251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.017295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.017337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.017380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.017423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.017886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.017930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.017973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.018017] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.018065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.018110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.018156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.018218] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.018261] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.018315] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.018376] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.018422] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.018824] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 576.018863] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 576.019409] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.019631] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.019879] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.020001] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 576.020044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 576.020089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 576.020132] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 576.020174] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 576.020218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.020261] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 576.020304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.020347] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 576.020389] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.020431] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 576.020478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.020521] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 576.020527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.020570] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.020614] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 576.020656] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 576.020699] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 576.020742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.020788] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 576.020831] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 576.020874] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.020917] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.020960] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.021004] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.021066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.021119] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.021162] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.021320] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.021357] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.021672] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 576.021727] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.021769] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.021827] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.023013] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.023339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.023382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.023426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.023521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.023565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.023609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.023652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.023695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.023738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.023782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.023830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.023875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.023950] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.023993] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.025557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.025602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.025646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 576.026397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.026492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.027221] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 576.027266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 576.028484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 576.030579] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 576.031619] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.048545] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.048601] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.048775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.049107] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.049249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.065131] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.082795] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.082908] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.082996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.083318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.083362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.083406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.083492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.083538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.083584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.083633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.083676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.083719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.083765] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.083813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.083858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.083903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.083966] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.084009] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.084064] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.084126] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.084172] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.084216] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 576.084255] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 576.084863] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.085566] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.085623] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.085747] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 576.085791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 576.085835] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 576.085881] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 576.085923] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 576.085966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.086010] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 576.086052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.086095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 576.086138] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.086179] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 576.086189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.086231] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 576.086237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.086280] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.086324] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 576.086367] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 576.086409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 576.086626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.086671] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 576.086713] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 576.086756] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.086799] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.086842] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.086886] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.086953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.087007] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.087051] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.087201] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.087239] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.087566] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 576.087623] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.087663] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.087721] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.087985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.088318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.088362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.088406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.088504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.088548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.088591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.088636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.088679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.088722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.088765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.088815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.088859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.088935] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.088978] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.090408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.090577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.090622] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 576.091385] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.091427] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.092246] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 576.092291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 576.093396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 576.095541] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 576.096552] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.113435] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.113532] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.113704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.114015] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.114159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.130136] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.148615] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.148728] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.148816] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.149134] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.149178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.149221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.149264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.149306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.149349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.149395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.149493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.149538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.149581] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.149630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.149675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.149721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.149789] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.149831] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.149885] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.149946] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.149991] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.150034] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 576.150074] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 576.150665] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.150843] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.150896] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.151014] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 576.151057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 576.151103] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 576.151147] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 576.151189] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 576.151233] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.151277] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 576.151320] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.151363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 576.151405] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.151477] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 576.151485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.151527] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 576.151533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.151577] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.151620] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 576.151663] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 576.151706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 576.151749] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.151794] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 576.151837] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 576.151883] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.151927] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.151972] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.152019] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.152081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.152133] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.152177] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.152330] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.152368] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.152677] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 576.152731] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.152776] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.152834] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.153317] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.153647] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.153692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.153735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.153778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.153820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.153863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.153908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.153950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.153993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.154035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.154082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.154126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.154201] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.154245] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.156349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.156394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.156489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 576.157358] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 576.157403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 576.158604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 576.160712] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 576.161800] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.178691] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.178749] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.178921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.179246] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.179389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.195400] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.213763] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.213876] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.213965] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.214284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.214328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.214371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.214414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.214495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.214541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.214590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.214635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.214680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.214723] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.214772] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.214818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.214865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.214926] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.214970] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.215024] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.215086] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.215131] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.215175] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 576.215213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 576.215794] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.215963] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.216015] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.216138] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 576.216182] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 576.216228] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 576.216272] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 576.216314] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 576.216359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.216402] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 576.216519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.216564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 576.216607] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.216649] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 576.216657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.216699] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 576.216706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.216749] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.216792] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 576.216835] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 576.216878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 576.216921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.216967] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 576.217009] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 576.217053] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.217096] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.217139] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.217183] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.217251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.217305] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.217349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.217520] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.217558] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.217847] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 576.217901] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.217941] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.217999] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.218296] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.218622] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.218667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.218712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.218755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.218798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.218841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.218884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.218926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.218969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.219012] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.219060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.219105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.219180] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.219224] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.220717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.220763] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.220807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 576.221747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.221790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.222621] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 576.222666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 576.223834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 576.225494] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 576.226545] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.243428] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.243507] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.243679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.243987] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.244127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.260127] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.278702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.278814] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.278901] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.279218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.279262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.279305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.279348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.279391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.279487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.279535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.279577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.279622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.279666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.279713] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.279758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.279803] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.279864] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.279907] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.279961] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.280025] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.280071] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.280115] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 576.280153] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 576.280747] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.280921] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.280976] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.281097] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 576.281141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 576.281185] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 576.281229] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 576.281271] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 576.281316] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.281359] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 576.281402] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.281497] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 576.281539] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.281581] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 576.281589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.281631] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 576.281637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.281680] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.281724] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 576.281768] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 576.281811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 576.281853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.281899] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 576.281941] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 576.281985] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.282028] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.282071] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.282114] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.282181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.282236] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.282279] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.282475] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.282513] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.282803] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:30 BXT-2 kernel: [ 576.282856] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.282898] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.282956] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.283879] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.284206] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.284250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.284293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.284335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.284378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.284421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.284503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.284547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.284589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.284633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.284680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.284725] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.284800] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.284843] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.286607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.286651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.286695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:30 BXT-2 kernel: [ 576.287511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.287553] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:30 BXT-2 kernel: [ 576.288288] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:30 BXT-2 kernel: [ 576.288334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:30 BXT-2 kernel: [ 576.289447] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:30 BXT-2 kernel: [ 576.291565] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:30 BXT-2 kernel: [ 576.292580] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.309492] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.309551] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.309721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.310030] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.310168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.326085] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.344596] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:30 BXT-2 kernel: [ 576.344710] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.344797] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.345118] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.345162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:30 BXT-2 kernel: [ 576.345205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.345248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.345291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.345334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:30 BXT-2 kernel: [ 576.345381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:30 BXT-2 kernel: [ 576.345424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:30 BXT-2 kernel: [ 576.345510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:30 BXT-2 kernel: [ 576.345553] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.345601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:30 BXT-2 kernel: [ 576.345646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:30 BXT-2 kernel: [ 576.345691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.345753] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:30 BXT-2 kernel: [ 576.345796] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.345849] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:30 BXT-2 kernel: [ 576.345911] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.345955] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.345998] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:30 BXT-2 kernel: [ 576.346037] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:30 BXT-2 kernel: [ 576.346623] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.346804] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:30 BXT-2 kernel: [ 576.346840] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:30 BXT-2 kernel: [ 576.346960] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:30 BXT-2 kernel: [ 576.347004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:30 BXT-2 kernel: [ 576.347049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:30 BXT-2 kernel: [ 576.347092] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:30 BXT-2 kernel: [ 576.347135] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:30 BXT-2 kernel: [ 576.347179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.347222] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:30 BXT-2 kernel: [ 576.347265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.347308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:30 BXT-2 kernel: [ 576.347350] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.347392] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:30 BXT-2 kernel: [ 576.347441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.347484] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:30 BXT-2 kernel: [ 576.347490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.347533] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:30 BXT-2 kernel: [ 576.347576] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:30 BXT-2 kernel: [ 576.347618] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:30 BXT-2 kernel: [ 576.347661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:30 BXT-2 kernel: [ 576.347703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:30 BXT-2 kernel: [ 576.347748] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:30 BXT-2 kernel: [ 576.347790] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:30 BXT-2 kernel: [ 576.347833] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.347877] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.347920] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.347962] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:30 BXT-2 kernel: [ 576.348033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:30 BXT-2 kernel: [ 576.348089] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:30 BXT-2 kernel: [ 576.348133] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:30 BXT-2 kernel: [ 576.349079] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:30 BXT-2 kernel: [ 576.349119] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:30 BXT-2 kernel: [ 576.349409] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.350080] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.350138] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.350213] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.352890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.353210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.353254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.353297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.353340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.353383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.353426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.353821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.353865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.353908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.353951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.354000] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.354045] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.354120] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.354163] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.355791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.355836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.355881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.356675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.356718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.357634] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.357679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.358843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.360938] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.361975] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.378862] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.378920] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.379091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.379645] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.379796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.395504] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.413817] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.413928] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.414015] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.414340] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.414384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.414427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.414806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.414850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.414893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.414942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.414984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.415027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.415070] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.415117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.415162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.415207] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.415268] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.415312] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.415365] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.415425] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.416012] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.416056] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.416095] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.417263] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.417613] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.417667] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.417793] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.417836] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.417881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.417925] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.417966] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.418011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.418053] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.418096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.418139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.418181] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.418223] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.418229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.418271] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.418277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.418320] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.418362] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.418405] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.419041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.419084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.419130] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.419172] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.419217] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.419261] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.419304] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.419347] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.419415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.419504] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.419548] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.419673] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.419711] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.420002] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.420058] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.420100] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.420156] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.420508] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.420836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.420880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.420923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.420966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.421008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.421051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.421094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.421136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.421179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.421222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.421269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.421313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.421387] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.421430] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.422988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.423033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.423078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.423867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.423911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.424654] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.424699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.425840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.427938] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.428976] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.445864] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.445921] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.446092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.446438] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.446577] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.462523] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.481040] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.481151] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.481238] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.481565] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.481610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.481654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.481697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.481741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.481784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.481832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.481875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.481919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.481962] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.482011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.482056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.482102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.482165] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.482207] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.482261] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.482322] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.482367] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.482410] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.482502] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.483059] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.483233] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.483286] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.483409] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.483505] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.483551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.483595] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.483637] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.483683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.483726] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.483769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.483813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.483856] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.483899] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.483907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.483948] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.483955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.483998] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.484041] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.484085] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.484128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.484170] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.484216] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.484258] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.484302] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.484345] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.484388] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.484431] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.484514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.484567] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.484610] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.484756] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.484794] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.485083] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.485136] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.485178] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.485235] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.485771] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.486104] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.486147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.486191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.486233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.486276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.486319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.486362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.486405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.486608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.486652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.486700] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.486745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.486820] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.486863] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.489409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.489535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.489580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.493208] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.493256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.494339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.496427] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.497499] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.514398] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.514493] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.514665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.514988] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.515126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.531024] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.548753] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.548867] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.548956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.549275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.549319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.549362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.549404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.549489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.549535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.549583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.549628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.549672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.549716] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.549982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.550028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.550073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.550136] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.550180] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.550233] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.550295] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.550340] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.550383] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.550422] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.551014] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.551188] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.551223] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.551342] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.551385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.551430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.551574] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.551616] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.551661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.551705] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.551749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.551792] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.551835] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.551877] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.551885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.551927] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.551933] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.551977] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.552021] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.552064] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.552107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.552150] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.552195] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.552238] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.552281] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.552325] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.552368] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.552411] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.552511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.552564] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.552608] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.552756] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.552794] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.553084] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.553137] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.553177] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.553234] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.553652] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.553993] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.554038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.554081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.554124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.554167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.554209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.554252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.554295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.554337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.554380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.554427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.554523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.554601] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.554644] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.556288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.556333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.556377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.557212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.557257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.558027] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.558072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.559199] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.561303] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.562342] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.579215] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.579271] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.579631] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.579964] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.580105] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.595853] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.613733] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.613847] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.613935] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.614252] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.614297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.614340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.614383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.614426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.614551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.614602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.614646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.614688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.614733] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.614781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.614826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.614871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.614936] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.614979] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.615033] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.615095] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.615140] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.615184] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.615222] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.615808] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.615984] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.616036] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.616157] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.616201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.616246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.616290] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.616332] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.616376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.616419] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.616501] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.616545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.616588] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.616630] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.616639] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.616682] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.616688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.616731] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.616774] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.616817] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.616860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.616903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.616948] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.616991] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.617034] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.617077] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.617120] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.617164] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.617229] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.617282] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.617326] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.617503] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.617541] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.617831] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.617885] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.617926] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.617984] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.618238] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.618562] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.618607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.618650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.618692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.618735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.618777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.618820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.618863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.618906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.618949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.618998] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.619043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.619118] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.619161] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.620801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.620847] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.620891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.621756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.621803] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.622545] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.622592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.623623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.625462] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.626477] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.643386] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.643525] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.643699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.644032] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.644173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.660155] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.677949] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.678062] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.678150] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.678483] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.678532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.678577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.678621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.678668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.678712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.678759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.678803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.678846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.678890] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.678937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.678982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.679028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.679090] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.679133] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.679186] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.679247] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.679292] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.679335] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.679374] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.679954] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.680123] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.680178] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.680292] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.680334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.680380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.680424] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.680500] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.680548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.680593] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.680640] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.680684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.680727] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.680769] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.680777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.680818] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.680824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.680868] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.680911] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.680954] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.680997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.681040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.681085] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.681127] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.681171] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.681215] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.681257] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.681301] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.681362] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.681415] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.681482] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.681629] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.681667] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.681957] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.682009] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.682051] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.682107] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.682355] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.682739] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.682785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.682828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.682870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.682913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.682956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.682999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.683041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.683084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.683127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.683173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.683218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.683292] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.683335] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.684797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.684841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.684885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.685647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.685690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.686403] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.686474] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.687507] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.689460] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.690538] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.707435] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.707518] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.707692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.708009] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.708152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.724066] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:31 BXT-2 kernel: [ 576.742236] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:31 BXT-2 kernel: [ 576.742350] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.742486] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.742823] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.742868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.742912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.742954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.742997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.743040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.743088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.743131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.743173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.743216] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.743264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.743310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.743355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.743421] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.743508] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.743566] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.743630] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.743675] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.743719] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.743757] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.744304] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.744752] [drm:drm_mode_addfb2] [FB:76] >May 24 03:31:31 BXT-2 kernel: [ 576.744816] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:31 BXT-2 kernel: [ 576.802350] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:31 BXT-2 kernel: [ 576.803016] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:31 BXT-2 kernel: [ 576.803824] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.804236] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.804269] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.804392] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.804746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.804793] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.804836] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.804879] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.804923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.804968] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.805011] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.805054] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.805096] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.805138] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.805146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.805188] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.805194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.805237] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.805279] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.805322] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.805365] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.805408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.806152] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.806195] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.806240] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.806284] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.806326] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.806396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.806770] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.806814] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.807414] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.807685] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.807981] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.808039] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.808079] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.808136] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.808420] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.809074] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.809119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.809162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.809205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.809248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.809291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.809334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.809377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.809419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.809897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.809947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.809992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.810068] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 576.810111] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.811759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.811805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.811850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.812761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.812807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.813662] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.813708] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.814885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.816999] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.818065] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.834929] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.834987] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.835159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.851526] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.851585] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.868390] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.868563] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.885013] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.902809] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 576.903072] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.903155] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.903510] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.903556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.903600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.903644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.903687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.903730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.903779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.903822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.903866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.903909] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.903959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.904004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.904050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.904114] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.904157] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.904211] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.904272] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.904316] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.904359] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.904398] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.904992] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.905161] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.905212] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.905326] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.905369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.905413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.905496] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.905538] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.905582] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.905627] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.905670] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.905714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.905756] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.905798] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.905806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.905847] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.905854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.905897] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.905940] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.905984] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.906026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.906069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.906114] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.906157] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.906200] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.906244] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.906286] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.906348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.906400] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.906469] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.906611] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.906649] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.906938] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.906991] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.907031] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.907088] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.907556] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.907890] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.907934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.907977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.908020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.908062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.908105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.908148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.908190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.908233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.908275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.908321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.908366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.908475] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 576.908519] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.909934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.909977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.910021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.910798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.910841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.911575] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.911620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.912708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.914796] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.915798] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.932657] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.932715] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.932887] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.933197] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.933333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.949295] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.967831] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 576.967943] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.968022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.968341] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.968384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.968427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.968527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.968573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.968617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.968667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.968710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.968753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.968798] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.968845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.968890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.968935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.968999] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.969041] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.969094] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.969156] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.969199] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.969242] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 576.969281] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 576.969877] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.970589] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 576.970646] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 576.970767] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 576.970811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 576.970856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 576.970901] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 576.970943] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 576.970987] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.971031] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 576.971073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.971116] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 576.971159] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.971200] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 576.971207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.971249] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 576.971255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.971298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 576.971341] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 576.971383] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 576.971426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 576.971508] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 576.971555] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 576.971598] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 576.971644] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.971689] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.971734] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 576.971799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.971853] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.971897] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 576.972044] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 576.972082] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 576.972375] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 576.972468] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.972509] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 576.972569] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 576.974788] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.975123] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 576.975167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 576.975211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.975255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.975298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.975341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 576.975384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 576.975427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 576.975550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 576.975593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 576.975645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 576.975690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.975766] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 576.975809] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 576.980174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.980221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 576.980266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 576.981272] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 576.981318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 576.982569] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 576.984474] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 576.985428] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.002343] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.002403] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.002637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.003024] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.003177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.018984] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.036807] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.036921] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.037002] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.037318] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.037362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.037405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.037517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.037560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.037605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.037653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.037696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.037739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.037782] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.037829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.037874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.037919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.037984] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.038027] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.038081] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.038144] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.038187] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.038231] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 577.038270] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 577.038925] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.039649] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.039701] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.039824] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 577.039868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 577.039913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 577.039957] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 577.039999] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 577.040043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.040085] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 577.040128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.040171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 577.040213] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.040255] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 577.040261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.040303] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 577.040309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.040352] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.040395] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 577.040477] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 577.040522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 577.040567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.040614] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 577.040658] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 577.040703] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.040748] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.040794] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.040855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.040907] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.040953] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.041100] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.041138] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.041434] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 577.042058] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.042101] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.042158] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.042825] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.043156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.043200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.043243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.043286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.043328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.043371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.043414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.043503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.043548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.043591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.043640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.043687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.043996] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.044039] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.045522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.045566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.045611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 577.046362] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.046404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.048236] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 577.048280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 577.049501] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 577.051605] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 577.052660] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.069541] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.069598] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.069768] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.070097] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.070232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.086267] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.103713] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.103824] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.103905] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.104226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.104270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.104313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.104356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.104399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.104839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.104889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.104932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.104974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.105017] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.105065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.105110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.105155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.105219] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.105263] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.105316] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.105376] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.105419] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.105976] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 577.106014] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 577.107178] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.107350] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.107580] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.107709] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 577.107753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 577.107798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 577.107842] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 577.107883] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 577.107928] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.107971] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 577.108014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.108057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 577.108099] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.108141] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 577.108148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.108190] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 577.108195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.108238] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.108281] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 577.108324] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 577.108366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 577.108408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.109202] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 577.109244] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 577.109289] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.109332] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.109375] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.109678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.109734] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.109777] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.109925] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.109963] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.110260] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 577.110314] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.110354] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.110411] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.111124] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.111560] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.111606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.111651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.111693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.111736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.111779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.111822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.111864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.111907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.111950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.111997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.112041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.112115] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.112159] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.114174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.114219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.114264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 577.115360] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 577.115407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 577.116835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 577.121138] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 577.122166] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.139042] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.139101] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.139273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.139855] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.140001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.155684] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.173695] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.173807] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.173886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.174205] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.174249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.174291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.174334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.174377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.174419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.174532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.174576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.174619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.174944] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.174995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.175041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.175086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.175149] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.175192] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.175246] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.175308] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.175352] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.175395] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 577.175463] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 577.176024] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.176202] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.176256] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.176376] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 577.176419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 577.176520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 577.176565] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 577.176607] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 577.176652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.176696] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 577.176739] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.176783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 577.176825] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.176868] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 577.176875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.176918] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 577.176924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.176968] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.177011] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 577.177054] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 577.177097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 577.177140] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.177185] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 577.177228] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 577.177272] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.177315] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.177358] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.177420] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.177497] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.177541] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.177686] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.177724] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.178014] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 577.178067] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.178109] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.178165] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.178603] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.178934] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.178978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.179021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.179064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.179107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.179150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.179192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.179235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.179278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.179320] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.179368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.179413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.179578] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.179622] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.181128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.181172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.181217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 577.182066] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 577.182113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 577.183174] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 577.185274] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 577.186299] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.203165] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.203221] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.203392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.203906] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.204053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.219813] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.237706] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.237820] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.237900] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.238226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.238270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.238313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.238356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.238399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.238901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.238954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.238996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.239039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.239082] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.239130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.239176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.239221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.239286] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.239329] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.239383] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.239998] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.240052] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.240097] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 577.240135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 577.241305] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.241638] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.241676] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.241798] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 577.241842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 577.241887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 577.241931] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 577.241973] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 577.242017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.242060] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 577.242103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.242146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 577.242189] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.242231] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 577.242238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.242280] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 577.242285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.242329] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.242372] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 577.242415] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 577.243385] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 577.243428] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.243661] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 577.243703] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 577.243749] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.243792] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.243835] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.243904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.243958] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.244002] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.244157] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.244194] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.244930] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 577.245251] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.245292] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.245349] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.246175] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.246665] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.246711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.246754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.246797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.246840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.246883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.246926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.246968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.247011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.247053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.247101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.247145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.247221] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.247263] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.249232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.249277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.249321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 577.250133] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 577.250177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 577.251235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 577.253336] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 577.254360] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.271302] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.271364] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.271591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.271916] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.272055] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.287887] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.306398] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.306546] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.306626] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.306946] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.306989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.307033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.307076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.307119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.307161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.307207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.307250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.307293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.307336] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.307382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.307427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.308097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.308162] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.308205] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.308258] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.308321] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.308364] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.308408] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:31 BXT-2 kernel: [ 577.308773] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:31 BXT-2 kernel: [ 577.309320] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.309624] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.309677] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.309798] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:31 BXT-2 kernel: [ 577.309841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:31 BXT-2 kernel: [ 577.309885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:31 BXT-2 kernel: [ 577.309929] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:31 BXT-2 kernel: [ 577.309971] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:31 BXT-2 kernel: [ 577.310015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.310057] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:31 BXT-2 kernel: [ 577.310100] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.310143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:31 BXT-2 kernel: [ 577.310186] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.310227] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:31 BXT-2 kernel: [ 577.310234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.310276] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:31 BXT-2 kernel: [ 577.310281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.310324] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:31 BXT-2 kernel: [ 577.310367] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:31 BXT-2 kernel: [ 577.310410] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:31 BXT-2 kernel: [ 577.311159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:31 BXT-2 kernel: [ 577.311201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:31 BXT-2 kernel: [ 577.311247] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:31 BXT-2 kernel: [ 577.311289] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:31 BXT-2 kernel: [ 577.311334] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.311377] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.311419] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:31 BXT-2 kernel: [ 577.311797] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.311852] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.311896] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.312045] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:31 BXT-2 kernel: [ 577.312082] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:31 BXT-2 kernel: [ 577.312371] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:31 BXT-2 kernel: [ 577.312424] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.312789] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:31 BXT-2 kernel: [ 577.312848] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:31 BXT-2 kernel: [ 577.313085] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.313402] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:31 BXT-2 kernel: [ 577.313694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:31 BXT-2 kernel: [ 577.313738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.313781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.313823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.313867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:31 BXT-2 kernel: [ 577.313909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:31 BXT-2 kernel: [ 577.313952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:31 BXT-2 kernel: [ 577.313994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:31 BXT-2 kernel: [ 577.314037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:31 BXT-2 kernel: [ 577.314085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:31 BXT-2 kernel: [ 577.314129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.314203] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:31 BXT-2 kernel: [ 577.314246] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.316088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.316135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:31 BXT-2 kernel: [ 577.316179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:31 BXT-2 kernel: [ 577.317116] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:31 BXT-2 kernel: [ 577.317164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:31 BXT-2 kernel: [ 577.318247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:31 BXT-2 kernel: [ 577.320391] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:31 BXT-2 kernel: [ 577.321580] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:31 BXT-2 kernel: [ 577.338527] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:31 BXT-2 kernel: [ 577.338586] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.338759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:31 BXT-2 kernel: [ 577.339299] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:31 BXT-2 kernel: [ 577.339446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.355110] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.372698] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.372810] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.372889] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.373215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.373259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.373302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.373345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.373388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.373430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.373534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.373577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.373622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.373666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.373713] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.373760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.373805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.373868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.373910] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.373964] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.374025] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.374069] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.374112] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.374151] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.374730] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.374898] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.374952] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.375075] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.375118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.375163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.375206] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.375248] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.375293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.375335] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.375378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.375421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.375503] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.375546] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.375554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.375596] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.375602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.375645] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.375688] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.375731] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.375774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.375817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.375862] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.375905] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.375948] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.375992] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.376035] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.376099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.376153] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.376197] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.376340] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.376378] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.376689] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.376744] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.376786] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.376843] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.377718] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.378040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.378085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.378128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.378170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.378213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.378256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.378299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.378341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.378384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.378427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.378508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.378554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.378628] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.378672] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.380407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.380480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.380525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.381272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.381315] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.382261] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.382309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.383497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.385592] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.386623] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.403542] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.403599] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.403770] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.404212] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.404360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.420142] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.438722] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.438835] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.438914] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.439242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.439286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.439329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.439372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.439414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.439880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.439931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.439974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.440017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.440061] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.440108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.440154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.440199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.440264] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.440307] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.440361] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.440422] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.441028] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.441072] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.441111] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.442280] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.442603] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.442644] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.442766] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.442810] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.442854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.442898] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.442940] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.442984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.443028] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.443071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.443114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.443156] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.443198] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.443206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.443247] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.443253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.443296] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.443339] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.443381] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.443424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.444253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.444299] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.444341] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.444387] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.444431] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.444780] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.444850] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.444905] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.444948] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.445102] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.445140] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.445795] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.446114] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.446156] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.446214] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.446750] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.447083] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.447127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.447170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.447214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.447257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.447299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.447342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.447385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.447428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.447941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.447993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.448037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.448113] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.448156] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.450080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.450126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.450171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.451084] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.451129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.452184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.454283] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.455306] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.472177] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.472237] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.472407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.472982] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.473120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.488828] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.506596] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.506708] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.506789] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.507112] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.507156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.507199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.507242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.507285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.507327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.507373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.507416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.507524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.507569] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.507617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.507662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.507710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.507772] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.507814] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.507868] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.507929] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.507973] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.508016] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.508056] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.508653] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.509332] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.509382] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.509547] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.509591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.509635] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.509679] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.509722] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.509767] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.509812] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.509857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.509901] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.509944] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.509986] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.509994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.510037] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.510043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.510087] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.510130] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.510173] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.510216] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.510259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.510304] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.510347] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.510390] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.510470] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.510515] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.510582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.510638] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.510681] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.510831] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.510869] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.511166] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.511221] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.511263] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.511320] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.511610] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.511939] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.511984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.512027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.512071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.512114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.512158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.512201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.512244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.512287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.512332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.512379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.512424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.512562] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.512605] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.514038] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.514083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.514127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.514943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.514987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.515976] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.516021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.517073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.519169] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.520176] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.537085] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.537145] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.537317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.538259] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.538403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.553688] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.572196] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.572310] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.572390] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.572892] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.572938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.572982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.573024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.573067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.573110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.573158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.573200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.573243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.573286] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.573333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.573378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.573424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.573531] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.573837] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.573892] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.573955] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.574001] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.574044] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.574083] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.574687] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.575356] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.575593] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.575717] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.575761] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.575806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.575850] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.575892] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.575935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.575978] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.576021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.576064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.576106] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.576148] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.576154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.576196] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.576202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.576245] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.576288] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.576331] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.576373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.576415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.576520] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.576563] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.576609] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.576654] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.576699] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.576761] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.576816] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.577200] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.577353] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.577390] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.577718] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.577773] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.577815] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.577872] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.578368] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.578805] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.578851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.578894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.578937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.578980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.579023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.579065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.579108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.579151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.579193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.579241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.579285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.579359] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.579402] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.581118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.581161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.581206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.582074] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.582121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.583289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.585389] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.586479] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.603373] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.603430] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.603662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.603975] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.604121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.620005] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.637708] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.637822] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.637902] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.638229] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.638273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.638316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.638359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.638402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.638497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.638546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.638589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.638634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.638678] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.638725] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.638771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.638815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.638879] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.638922] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.638975] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.639039] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.639083] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.639126] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.639165] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.639745] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.639915] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.639972] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.640091] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.640134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.640180] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.640224] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.640266] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.640311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.640354] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.640396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.640515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.640558] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.640600] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.640609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.640652] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.640658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.640702] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.640745] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.640789] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.640832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.640875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.640920] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.640963] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.641006] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.641049] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.641092] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.641159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.641213] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.641256] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.641415] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.641476] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.641766] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.641819] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.641860] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.641917] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.642358] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.642692] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.642738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.642782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.642825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.642868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.642911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.642954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.642996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.643039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.643082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.643130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.643174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.643249] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.643291] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.644958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.645003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.645047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.645973] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.646019] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.647071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.649173] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.650198] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.667078] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.667136] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.667309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.667821] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.667948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.684140] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.701692] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.701804] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.701884] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.702205] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.702249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.702292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.702335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.702378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.702420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.702508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.702553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.702598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.702643] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.702690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.702737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.702782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.702844] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.702887] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.702940] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.703000] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.703044] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.703087] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.703127] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.703746] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.704651] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.704703] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.704827] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.704871] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.704916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.704960] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.705002] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.705046] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.705089] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.705132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.705175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.705217] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.705261] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.705268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.705309] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.705315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.705358] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.705401] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.705488] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.705532] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.705575] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.705622] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.705666] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.705711] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.705758] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.705802] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.705865] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.705918] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.705964] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.706115] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.706153] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.706483] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.706539] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.706582] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.706640] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.707097] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.707416] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.707518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.707569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.707614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.707658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.707703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.707749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.707792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.707836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.707879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.707927] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.707972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.708046] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.708089] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.709530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.709573] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.709618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.710373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.710415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.711187] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.711231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.712298] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.714384] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.715409] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.732339] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.732397] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.732645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.732959] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.733099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.748961] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.767485] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.767595] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.767672] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.767992] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.768036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.768079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.768122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.768164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.768207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.768253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.768296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.768338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.768382] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.768429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.768528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.768577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.768640] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.768682] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.768736] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.768798] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.768842] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.768886] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.768925] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.769500] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.769666] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.769719] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.769838] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.769882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.769927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.769971] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.770014] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.770058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.770101] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.770144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.770187] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.770229] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.770271] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.770279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.770322] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.770328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.770372] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.770415] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.770520] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.770564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.770608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.770654] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.770696] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.770741] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.770784] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.770829] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.770901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.770956] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.771000] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.771148] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.771187] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.771499] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.771554] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.771596] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.771653] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.772564] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.772890] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.772934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.772977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.773020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.773063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.773106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.773148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.773191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.773234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.773276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.773323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.773367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.773514] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.773558] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.774988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.775034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.775079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.776011] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.776060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.777154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.779513] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.780623] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.797535] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.797593] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.797764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.798100] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.798242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.814276] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.831691] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.831803] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.831882] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.832201] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.832245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.832288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.832331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.832373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.832416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.832501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.832550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.832598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.832644] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.832694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.832741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.832790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.832856] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.832898] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.832952] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.833012] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.833056] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.833100] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.833139] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.833719] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.833896] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.833951] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.834073] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.834116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.834162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.834206] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.834248] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.834293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.834336] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.834379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.834422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.834538] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.834581] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.834588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.834631] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.834636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.834679] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.834722] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.834765] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.834808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.834850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.834895] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.834938] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.834981] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.835024] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.835067] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.835134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.835189] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.835233] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.835398] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.835485] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.836353] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.836956] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.836998] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.837054] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.837357] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.837684] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.837729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.837771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.837814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.837856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.837899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.837942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.837984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.838027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.838069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.838116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.838160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.838234] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.838277] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.839744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.839787] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.839832] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.840600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.840643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.841356] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.841399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.842492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.844487] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.845517] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.864176] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.864235] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.864416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.864867] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.864999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.879106] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.897608] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.897720] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.897800] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.898117] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.898161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.898204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.898247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.898289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.898332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.898378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.898420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.898504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.898554] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.898606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.898654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.898700] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.898764] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.898809] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.898863] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.898923] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.898966] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.899010] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.899049] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.899657] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.900333] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.900384] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.900551] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.900595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.900641] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.900685] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.900728] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.900772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.900816] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.900859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.900903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.900945] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.900988] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.900996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.901038] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.901044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.901088] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.901131] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.901175] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.901217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.901260] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.901305] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.901348] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.901391] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.901469] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.901515] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.901579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.901634] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.901679] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.901826] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.901863] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.902153] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.902206] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.902248] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.902306] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.902797] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.903120] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.903164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.903207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.903250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.903293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.903336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.903378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.903421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.903633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.903677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.903726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.903770] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.903846] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.903889] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.906576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.906622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.906667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.907449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.907541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.910968] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.911016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.912073] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.913657] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.914651] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.931563] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.931623] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.931813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.932332] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.932871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.948250] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.965874] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.965988] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.966068] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.966390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.966721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.966766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.966808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.966852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.966895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.966944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.966986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.967031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.967074] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.967121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.967166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.967211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.967275] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.967318] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.967371] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.967431] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.968095] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.968139] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 577.968178] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 577.969349] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.969650] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 577.969703] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 577.969825] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 577.969868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 577.969913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 577.969956] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 577.969998] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 577.970042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.970085] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 577.970128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.970171] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 577.970213] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.970255] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 577.970261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.970303] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 577.970309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.970352] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 577.970395] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 577.971146] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 577.971190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 577.971232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 577.971278] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 577.971320] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 577.971364] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.971408] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.971783] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 577.971855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.971909] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.971952] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 577.972104] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 577.972142] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 577.972762] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 577.973070] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.973111] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 577.973168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 577.974096] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.974427] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 577.974957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 577.975002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.975044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.975087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.975130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 577.975173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 577.975216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 577.975259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 577.975302] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 577.975354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 577.975399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.976324] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 577.976368] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 577.978420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.978597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.978656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 577.979761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.979807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 577.980650] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 577.980696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 577.981776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 577.983472] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 577.984526] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.001394] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.001483] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.001653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.001959] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.002100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.018025] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.035752] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.035866] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.035947] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.036275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.036319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.036362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.036405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.036503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.036547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.036597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.036640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.036683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.036727] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.036775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.036821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.036866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.036935] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.036978] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.037032] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.037093] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.037137] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.037180] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 578.037221] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 578.037802] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.037979] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.038032] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.038155] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 578.038199] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 578.038244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 578.038288] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 578.038330] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 578.038375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.038418] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 578.038546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.038590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 578.038632] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.038675] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 578.038684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.038726] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 578.038733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.038776] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.038819] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 578.038863] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 578.038905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 578.038948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.038995] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 578.039037] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 578.039080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.039124] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.039167] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.039234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.039288] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.039332] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.039543] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.039582] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.039872] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 578.039926] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.039966] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.040024] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.040282] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.040608] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.040653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.040696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.040739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.040782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.040824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.040867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.040910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.040953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.040996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.041046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.041091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.041166] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.041208] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.043085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.043132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.043176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 578.044045] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 578.044092] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 578.045260] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 578.046528] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 578.047574] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.050140] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x10001918, pins 0x00000040 >May 24 03:31:32 BXT-2 kernel: [ 578.050185] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short >May 24 03:31:32 BXT-2 kernel: [ 578.050257] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short >May 24 03:31:32 BXT-2 kernel: [ 578.050934] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:32 BXT-2 kernel: [ 578.064442] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.064526] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.064698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.067622] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.068016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.081095] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.098856] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.098969] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.099047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.099367] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.099411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.099511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.099555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.099600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.099643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.099691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.099734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.099777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.099820] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.099868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.099913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.099958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.100023] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.100066] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.100120] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.100183] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.100226] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.100270] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 578.100309] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 578.100899] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.101066] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.101115] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.101235] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 578.101279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 578.101324] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 578.101368] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 578.101410] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 578.101502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.101547] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 578.101590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.101633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 578.101676] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.101718] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 578.101727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.101768] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 578.101774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.101818] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.101861] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 578.101905] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 578.101947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 578.101990] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.102035] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 578.102078] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 578.102121] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.102165] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.102208] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.102276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.102330] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.102374] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.102550] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.102588] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.102877] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 578.102931] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.102971] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.103030] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.103855] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.104178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.104223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.104265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.104308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.104351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.104395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.104474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.104517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.104562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.104605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.104653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.104698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.104772] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.104818] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.106617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.106662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.106706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 578.107501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.107543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.108366] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 578.108411] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 578.109532] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 578.111626] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 578.112636] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.129584] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.129643] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.129815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.130143] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.130285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.146168] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.163694] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.163807] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.163886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.164207] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.164251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.164294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.164336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.164379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.164422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.164518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.164563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.164607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.164652] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.164702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.164749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.164793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.164855] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.164898] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.164951] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.165012] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.165056] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.165100] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 578.165138] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 578.165733] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.165909] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.165962] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.166081] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 578.166125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 578.166170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 578.166214] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 578.166257] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 578.166301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.166344] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 578.166387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.166431] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 578.166502] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.166545] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 578.166552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.166594] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 578.166600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.166644] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.166688] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 578.166731] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 578.166774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 578.166818] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.166863] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 578.166906] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 578.166949] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.166992] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.167035] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.167097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.167150] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.167193] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.167343] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.167381] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.167689] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 578.167743] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.167783] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.167840] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.168298] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.168717] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.168763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.168807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.168850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.168893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.168936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.168979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.169023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.169066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.169109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.169158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.169203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.169278] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.169321] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.171030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.171075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.171119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 578.171939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.171982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.172844] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 578.172889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 578.173996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 578.176093] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 578.177110] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.193994] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.194055] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.194228] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.194804] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.194956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.210616] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.227554] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.227668] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.227748] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.228070] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.228114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.228157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.228200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.228243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.228285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.228332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.228374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.228417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.228510] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.228559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.228607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.228654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.228999] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.229043] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.229098] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.229160] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.229204] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.229248] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 578.229286] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 578.229889] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.230630] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.230685] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.230808] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 578.230851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 578.230896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 578.230939] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 578.230981] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 578.231025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.231068] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 578.231111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.231154] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 578.231196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.231238] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 578.231244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.231286] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 578.231292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.231335] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.231377] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 578.231420] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 578.231561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 578.231603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.231649] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 578.231691] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 578.231735] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.231779] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.231822] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.231886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.231940] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.231984] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.232133] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.232171] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.232490] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 578.232545] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.232585] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.232643] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.233363] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.233758] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.233804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.233847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.233890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.233933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.233976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.234018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.234061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.234104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.234146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.234194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.234239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.234312] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.234355] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.236149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.236193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.236238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 578.237036] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.237080] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.238001] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 578.238049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 578.239146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 578.241240] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 578.242277] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.259175] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.259233] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.259404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.259764] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.259912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.275797] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.293753] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.293867] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.293947] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.294273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.294317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.294360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.294403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.294816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.294860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.294911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.294954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.294997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.295040] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.295089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.295134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.295179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.295242] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.295284] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.295339] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.295402] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.295908] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.295953] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:32 BXT-2 kernel: [ 578.295992] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:32 BXT-2 kernel: [ 578.297164] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.297361] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.297674] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.297806] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:32 BXT-2 kernel: [ 578.297850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:32 BXT-2 kernel: [ 578.297895] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:32 BXT-2 kernel: [ 578.297939] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:32 BXT-2 kernel: [ 578.297981] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:32 BXT-2 kernel: [ 578.298026] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.298069] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:32 BXT-2 kernel: [ 578.298112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.298155] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:32 BXT-2 kernel: [ 578.298197] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.298239] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:32 BXT-2 kernel: [ 578.298246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.298288] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:32 BXT-2 kernel: [ 578.298294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.298337] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:32 BXT-2 kernel: [ 578.298380] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:32 BXT-2 kernel: [ 578.298423] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:32 BXT-2 kernel: [ 578.298828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:32 BXT-2 kernel: [ 578.298871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:32 BXT-2 kernel: [ 578.298916] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:32 BXT-2 kernel: [ 578.298958] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:32 BXT-2 kernel: [ 578.299003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.299045] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.299088] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:32 BXT-2 kernel: [ 578.299155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.299208] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.299252] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.299411] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:32 BXT-2 kernel: [ 578.299885] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:32 BXT-2 kernel: [ 578.300178] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:32 BXT-2 kernel: [ 578.300236] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.300276] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:32 BXT-2 kernel: [ 578.300333] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:32 BXT-2 kernel: [ 578.302974] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.303306] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.303351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:32 BXT-2 kernel: [ 578.303395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.304041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.304085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.304128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:32 BXT-2 kernel: [ 578.304171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:32 BXT-2 kernel: [ 578.304214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:32 BXT-2 kernel: [ 578.304256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:32 BXT-2 kernel: [ 578.304300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:32 BXT-2 kernel: [ 578.304350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:32 BXT-2 kernel: [ 578.304395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.305157] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:32 BXT-2 kernel: [ 578.305203] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.309576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.309622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.309666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:32 BXT-2 kernel: [ 578.310415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.310502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:32 BXT-2 kernel: [ 578.311231] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:32 BXT-2 kernel: [ 578.311275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:32 BXT-2 kernel: [ 578.312415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:32 BXT-2 kernel: [ 578.314534] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:32 BXT-2 kernel: [ 578.315581] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:32 BXT-2 kernel: [ 578.332593] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:32 BXT-2 kernel: [ 578.332653] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.332826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:32 BXT-2 kernel: [ 578.333183] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:32 BXT-2 kernel: [ 578.333376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:32 BXT-2 kernel: [ 578.349083] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.366699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.366811] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.366890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.367209] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.367253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.367297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.367339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.367382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.367425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.367514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.367559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.367604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.367649] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.367697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.367744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.367790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.367852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.367895] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.367949] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.368009] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.368052] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.368096] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.368135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.368715] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.368886] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.368935] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.369054] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.369098] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.369143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.369186] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.369229] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.369273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.369316] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.369359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.369402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.369489] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.369533] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.369543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.369586] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.369594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.369638] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.369682] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.369727] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.369771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.369814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.369860] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.369902] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.369948] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.369991] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.370034] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.370098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.370153] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.370196] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.370350] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.370388] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.370772] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.371303] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.371344] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.371402] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.372520] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.372846] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.372890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.372934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.372977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.373019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.373062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.373105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.373147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.373190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.373233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.373281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.373325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.373399] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.373477] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.375928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.375977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.376022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.377203] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.377251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.378960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.381073] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.382087] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.398978] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.399037] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.399210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.400169] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.400319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.415592] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.433693] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.433806] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.433885] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.434208] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.434252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.434295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.434338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.434381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.434423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.434510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.434556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.434601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.434646] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.434695] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.434741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.434787] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.434850] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.434892] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.434946] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.435007] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.435051] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.435094] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.435134] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.435715] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.435889] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.435945] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.436065] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.436108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.436153] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.436197] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.436240] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.436284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.436327] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.436371] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.436415] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.436505] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.436547] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.436555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.436597] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.436603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.436647] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.436690] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.436733] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.436776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.436819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.436864] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.436907] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.436950] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.436993] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.437036] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.437098] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.437150] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.437194] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.437346] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.437383] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.437692] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.437746] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.437786] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.437843] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.438281] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.438692] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.438739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.438783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.438826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.438868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.438911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.438954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.438997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.439039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.439082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.439130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.439175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.439249] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.439292] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.440883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.440928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.440972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.441920] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.441965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.443024] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.445126] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.446162] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.463022] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.463080] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.463251] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.463854] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.464001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.479733] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.497798] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.497910] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.497989] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.498310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.498354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.498397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.498795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.498838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.498881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.498930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.498972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.499015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.499058] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.499105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.499150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.499195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.499259] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.499301] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.499354] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.499413] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.500008] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.500051] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.500090] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.501256] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.501542] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.501581] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.501704] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.501747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.501792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.501835] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.501877] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.501922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.501964] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.502007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.502050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.502093] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.502134] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.502141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.502183] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.502189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.502232] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.502274] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.502317] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.502359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.502402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.503222] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.503264] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.503311] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.503355] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.503398] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.503693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.503749] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.503792] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.503939] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.503976] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.504264] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.504318] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.504358] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.504414] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.505053] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.505372] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.505415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.505641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.505685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.505728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.505772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.505815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.505857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.505900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.505943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.505992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.506036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.506110] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.506153] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.507963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.508008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.508053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.509016] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.509062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.509827] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.509873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.510935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.513045] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.514109] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.530987] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.531045] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.531216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.531569] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.531710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.547617] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.565912] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.566025] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.566104] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.566437] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.566879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.566924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.566966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.567009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.567052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.567103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.567146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.567189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.567232] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.567279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.567325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.567369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.567856] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.567902] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.567957] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.568019] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.568065] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.568109] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.568148] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.569319] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.569757] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.569811] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.569933] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.569977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.570022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.570066] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.570108] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.570153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.570196] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.570239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.570282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.570324] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.570366] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.570373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.570415] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.570782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.570843] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.570886] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.570930] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.570974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.571017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.571063] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.571106] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.571152] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.571196] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.571239] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.571307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.571362] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.571406] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.571922] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.571960] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.572257] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.572312] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.572352] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.572410] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.572974] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.573303] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.573348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.573391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.573759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.573804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.573848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.573891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.573934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.573976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.574019] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.574070] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.574114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.574190] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.574234] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.576041] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.576087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.576132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.576954] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.576997] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.577841] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.577886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.578923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.580488] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.581501] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.598408] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.598510] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.598681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.599003] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.599141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.615180] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.632725] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.632837] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.632916] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.633238] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.633282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.633325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.633368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.633410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.633892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.633943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.633986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.634029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.634072] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.634119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.634164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.634209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.634275] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.634319] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.634373] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.634889] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.634939] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.634983] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.635022] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.636190] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.636372] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.636591] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.636715] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.636759] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.636803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.636847] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.636889] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.636933] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.636976] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.637019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.637062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.637104] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.637146] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.637153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.637195] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.637201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.637244] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.637286] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.637329] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.637372] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.637414] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.638193] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.638237] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.638282] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.638325] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.638369] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.638668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.638724] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.638768] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.638916] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.638954] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.639242] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.639296] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.639336] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.639392] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.640074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.640398] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.640604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.640648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.640691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.640734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.640777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.640820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.640862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.640905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.640948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.640996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.641040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.641115] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.641158] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.643012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.643058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.643102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.644055] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.644101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.645162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.646486] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.647576] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.664519] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.664577] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.664751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.665081] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.665228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.681094] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.699774] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.699888] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.699968] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.700297] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.700342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.700386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.700428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.700898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.700942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.700993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.701036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.701079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.701122] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.701169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.701215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.701261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.701328] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.701371] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.701426] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.702044] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.702093] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.702137] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.702175] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.703345] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.703681] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.703738] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.703858] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.703902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.703947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.703990] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.704032] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.704076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.704120] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.704162] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.704205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.704248] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.704290] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.704297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.704339] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.704344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.704388] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.704430] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.705211] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.705254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.705296] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.705342] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.705384] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.705429] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.705785] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.705829] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.705898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.705953] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.705997] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.706160] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.706198] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.706840] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.707156] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.707197] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.707255] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.707895] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.708232] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.708276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.708320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.708363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.708406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.708936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.708979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.709022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.709065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.709108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.709159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.709203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.709281] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.709324] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.711197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.711244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.711288] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.712592] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.712640] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.714171] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.715573] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.716659] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.733639] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.733698] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.733870] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.734217] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.734345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.750186] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.767861] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.767973] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.768052] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.768374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.768418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.768774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.768817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.768860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.768902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.768951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.768994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.769037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.769079] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.769126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.769172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.769216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.769281] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.769323] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.769376] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.769983] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.770036] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.770081] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.770119] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.771287] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.771595] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.771648] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.771773] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.771816] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.771861] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.771905] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.771946] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.771991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.772033] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.772076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.772119] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.772161] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.772202] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.772209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.772251] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.772256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.772300] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.772342] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.772385] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.772427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.773227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.773273] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.773315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.773360] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.773403] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.773696] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.773764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.773818] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.773862] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.774008] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.774045] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.774333] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.774386] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.774427] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.774874] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.775132] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.775643] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.775689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.775732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.775774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.775817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.775860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.775903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.775945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.775988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.776030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.776078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.776122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.776196] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.776239] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.778196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.778240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.778285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.779178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 >May 24 03:31:33 BXT-2 kernel: [ 578.779221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2 >May 24 03:31:33 BXT-2 kernel: [ 578.780857] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.780903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.782049] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.784148] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.785206] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.802073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.802130] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.802299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.802893] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.803039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.818748] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.837243] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.837355] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.837490] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.837822] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.837867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.837911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.837955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.837998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.838045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.838093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.838136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.838180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.838223] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.838271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.838317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.838362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.838426] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.838504] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.838559] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.838620] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.838664] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.838708] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.838747] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.839301] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.839519] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.839571] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.839694] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.839737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.839783] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.839826] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.839868] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.839913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.839956] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.839999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.840042] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.840084] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.840125] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.840133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.840174] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.840180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.840223] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.840266] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.840309] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.840351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.840393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.840480] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.840523] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.840567] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.840610] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.840653] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.840719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.840773] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.840816] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.840959] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.840997] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.841287] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.841340] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.841382] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.841462] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.841752] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.842073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.842117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.842159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.842202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.842245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.842288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.842330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.842373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.842415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.842501] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.842548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.842593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.842667] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.842710] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.844172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.844217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.844262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.845050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.845094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.845892] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.845937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.847000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.849097] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.850182] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.867051] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.867110] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.867282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.867924] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.868073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.883679] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.901751] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.901864] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.901944] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.902284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.902341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.902392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.902534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.902586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.902636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.902699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.902749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.902798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.902849] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.902909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.902963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.903016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.903115] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.903164] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.903220] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.903290] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.903339] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.903383] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.903422] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.904088] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.904815] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.904872] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.904993] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.905037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.905082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.905126] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.905169] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.905214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.905258] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.905301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.905344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.905387] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.905429] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.905467] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.905511] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.905517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.905560] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.905606] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.905650] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.905695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.905740] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.905787] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.905830] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.905875] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.905920] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.905965] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.906030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.906085] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.906131] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.906823] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.906864] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.907155] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.907210] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.907251] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.907308] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.907645] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.907967] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.908011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.908055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.908097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.908141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.908184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.908228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.908270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.908313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.908356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.908404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.908542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.908616] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.908660] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.910117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.910163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.910207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.911025] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.911070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.912112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.913510] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.914580] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.931507] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.931566] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.931738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.932045] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.932167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.948136] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.965828] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.965942] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.966021] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.966345] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.966388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.966432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.966515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.966560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.966604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.966652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.966695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.966740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.966783] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.966830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.966876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.966921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.966984] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.967027] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.967080] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.967142] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.967186] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.967230] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 578.967268] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 578.967849] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.968022] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.968072] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.968191] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 578.968235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 578.968280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 578.968324] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 578.968366] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 578.968410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.968536] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 578.968580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.968624] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 578.968666] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.968709] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 578.968718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.968760] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 578.968766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.968810] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 578.968855] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 578.968898] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 578.968941] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 578.968984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 578.969031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 578.969073] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 578.969117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.969160] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.969203] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 578.969270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.969323] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.969367] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.969565] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 578.969603] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 578.969893] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 578.969946] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.969988] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 578.970046] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 578.970546] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.970881] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 578.970925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 578.970969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.971012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.971055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.971098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 578.971140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 578.971183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 578.971227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 578.971270] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 578.971318] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 578.971362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.971485] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 578.971529] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.973147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.973193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 578.973237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 578.974154] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 578.974199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 578.975483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 578.977579] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 578.978642] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 578.995579] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 578.995637] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.995808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 578.996142] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 578.996278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.012164] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.029715] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.029828] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.029907] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.030232] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.030276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.030319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.030362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.030405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.030531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.030581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.030624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.030667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.030711] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.030759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.030804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.030850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.030914] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.030957] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.031011] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.031073] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.031117] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.031160] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 579.031199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 579.031778] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.031945] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.031999] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.032120] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 579.032163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 579.032207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 579.032251] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 579.032294] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 579.032338] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.032381] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 579.032423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.032505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 579.032548] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.032591] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 579.032599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.032641] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 579.032647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.032691] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.032734] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 579.032777] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 579.032819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 579.032862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.032907] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 579.032950] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 579.032993] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.033036] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.033079] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.033145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.033199] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.033243] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.033391] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.033452] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.033742] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 579.033795] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.033837] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.033895] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.034886] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.035215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.035259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.035303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.035346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.035388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.035431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.035558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.035603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.035645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.035689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.035739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.035784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.035859] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.035903] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.037734] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.037779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.037824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 579.041334] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 579.041382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 579.042506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 579.044602] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 579.045634] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.062556] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.062614] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.062785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.063106] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.063247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.079155] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.097795] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.097910] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.097990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.098314] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.098359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.098402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.098851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.098894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.098938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.098988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.099031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.099074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.099117] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.099164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.099210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.099255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.099320] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.099363] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.099417] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.100046] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.100094] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.100137] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 579.100175] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 579.101344] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.101666] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.101722] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.101844] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 579.101888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 579.101933] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 579.101977] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 579.102019] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 579.102063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.102106] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 579.102149] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.102192] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 579.102234] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.102276] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 579.102284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.102326] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 579.102332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.102375] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.102417] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 579.103230] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 579.103273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 579.103316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.103361] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 579.103403] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 579.103747] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.103791] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.103834] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.103901] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.103955] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.103999] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.104147] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.104185] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.104889] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 579.105210] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.105251] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.105309] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.105830] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.106156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.106200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.106244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.106287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.106329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.106372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.106415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.106924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.106967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.107010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.107060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.107105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.107181] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.107225] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.111625] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.111671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.111716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 579.112703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.112746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.113644] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 579.113690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 579.114878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 579.116975] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 579.118007] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.134902] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.134962] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.135134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.135822] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.135970] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.152768] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.168744] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.168856] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.168935] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.169255] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.169299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.169342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.169385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.169427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.169876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.169926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.169969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.170012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.170055] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.170103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.170148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.170193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.170257] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.170299] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.170353] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.170413] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.170933] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.170976] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 579.171015] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 579.172182] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.172358] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.172559] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.172683] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 579.172726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 579.172771] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 579.172815] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 579.172856] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 579.172901] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.172944] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 579.172986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.173030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 579.173072] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.173114] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 579.173121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.173162] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 579.173168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.173211] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.173254] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 579.173296] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 579.173339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 579.173381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.173425] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 579.174410] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 579.174700] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.174754] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.174806] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.174908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.174967] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.175011] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.175197] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.175235] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.175964] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 579.176283] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.176324] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.176381] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.177394] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.177801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.177851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.177897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.177943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.177990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.178038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.178083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.178128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.178171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.178215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.178266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.178311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.178388] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.178432] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.181232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.181279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.181324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 579.182534] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 579.182582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 579.183932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 579.185502] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 579.186546] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.203438] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.203536] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.203709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.204028] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.204165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.220167] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.237795] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.237907] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.237986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.238309] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.238353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.238396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.238488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.238534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.238577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.238624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.238968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.239011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.239056] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.239107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.239152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.239198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.239261] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.239303] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.239357] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.239417] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.239500] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.239543] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 579.239582] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 579.240149] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.240325] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.240376] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.240605] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 579.240649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 579.240696] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 579.240740] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 579.240783] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 579.240827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.240871] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 579.240914] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.240958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 579.241001] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.241043] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 579.241051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.241094] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 579.241100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.241144] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.241187] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 579.241230] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 579.241273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 579.241316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.241361] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 579.241403] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 579.241473] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.241516] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.241558] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.241620] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.241672] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.241716] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.241863] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.241900] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.242189] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 579.242243] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.242283] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.242340] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.242825] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.243151] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.243194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.243238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.243280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.243323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.243366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.243409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.243522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.243565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.243609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.243658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.243703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.243778] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.243821] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.245483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.245528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.245572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 579.246328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.246370] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.247128] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 579.247173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 579.248249] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 579.250351] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 579.251380] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.268276] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.268334] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.268900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.269317] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.269824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.284895] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.302832] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.302943] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.303022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.303347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.303391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.303497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.303540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.303586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.303628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.303675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.303718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.303761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.303804] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.303852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.303898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.303943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.304238] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.304281] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.304335] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.304397] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.304473] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.304517] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:33 BXT-2 kernel: [ 579.304557] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:33 BXT-2 kernel: [ 579.305117] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.305295] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.305351] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.305519] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:33 BXT-2 kernel: [ 579.305564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:33 BXT-2 kernel: [ 579.305609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:33 BXT-2 kernel: [ 579.305653] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:33 BXT-2 kernel: [ 579.305695] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:33 BXT-2 kernel: [ 579.305739] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.305783] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:33 BXT-2 kernel: [ 579.305826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.305869] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:33 BXT-2 kernel: [ 579.305911] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.305953] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:33 BXT-2 kernel: [ 579.305961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.306003] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:33 BXT-2 kernel: [ 579.306009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.306052] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:33 BXT-2 kernel: [ 579.306094] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:33 BXT-2 kernel: [ 579.306137] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:33 BXT-2 kernel: [ 579.306179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:33 BXT-2 kernel: [ 579.306221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:33 BXT-2 kernel: [ 579.306266] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:33 BXT-2 kernel: [ 579.306308] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:33 BXT-2 kernel: [ 579.306351] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.306394] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.306475] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:33 BXT-2 kernel: [ 579.306544] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.306598] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.306642] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.306799] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:33 BXT-2 kernel: [ 579.306836] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:33 BXT-2 kernel: [ 579.307126] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:33 BXT-2 kernel: [ 579.307179] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.307219] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:33 BXT-2 kernel: [ 579.307278] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:33 BXT-2 kernel: [ 579.309050] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.309378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:33 BXT-2 kernel: [ 579.309424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:33 BXT-2 kernel: [ 579.309709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.309752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.309795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.309838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:33 BXT-2 kernel: [ 579.309881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:33 BXT-2 kernel: [ 579.309923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:33 BXT-2 kernel: [ 579.309966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:33 BXT-2 kernel: [ 579.310009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:33 BXT-2 kernel: [ 579.310060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:33 BXT-2 kernel: [ 579.310105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.310181] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:33 BXT-2 kernel: [ 579.310224] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.312980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.313030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:33 BXT-2 kernel: [ 579.313076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:33 BXT-2 kernel: [ 579.314625] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:33 BXT-2 kernel: [ 579.314673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:33 BXT-2 kernel: [ 579.315949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:33 BXT-2 kernel: [ 579.317497] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:33 BXT-2 kernel: [ 579.318535] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:33 BXT-2 kernel: [ 579.335420] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:33 BXT-2 kernel: [ 579.335504] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.335675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:33 BXT-2 kernel: [ 579.335985] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:33 BXT-2 kernel: [ 579.336124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.352054] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.369697] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.369809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.369888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.370206] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.370250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.370293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.370336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.370379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.370421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.370507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.370553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.370598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.370643] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.370692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.370738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.370782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.370845] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.370888] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.370941] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.371002] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.371045] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.371088] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.371127] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.371734] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.372443] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.372482] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.372607] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.372651] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.372696] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.372740] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.372783] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.372827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.372871] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.372914] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.372958] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.373001] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.373043] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.373050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.373092] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.373098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.373143] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.373186] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.373229] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.373272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.373315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.373360] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.373402] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.373481] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.373524] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.373567] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.373629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.373682] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.373726] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.373872] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.373910] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.374200] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.374253] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.374293] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.374351] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.374688] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.375020] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.375064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.375108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.375151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.375193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.375236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.375279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.375321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.375364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.375407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.375539] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.375585] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.375662] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.375705] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.377238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.377283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.377328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.378187] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.378232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.379492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.381486] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.382501] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.399382] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.399503] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.399841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.400169] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.400308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.416087] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.433698] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.433811] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.433890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.434211] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.434255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.434299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.434341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.434384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.434427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.434924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.434967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.435010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.435052] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.435100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.435145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.435189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.435254] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.435296] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.435350] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.435410] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.435941] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.435985] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.436023] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.437191] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.437367] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.437580] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.437704] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.437747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.437792] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.437835] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.437877] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.437921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.437964] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.438007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.438050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.438092] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.438134] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.438140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.438182] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.438188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.438231] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.438274] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.438316] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.438359] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.438401] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.439190] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.439233] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.439277] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.439321] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.439364] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.439430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.439775] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.439819] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.439966] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.440003] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.440291] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.440345] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.440385] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.440981] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.441223] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.441600] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.441645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.441689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.441732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.441775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.441818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.441861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.441904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.441946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.441989] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.442037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.442082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.442156] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.442199] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.444046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.444090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.444135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.445063] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.445108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.446162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.448255] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.449291] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.466187] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.466245] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.466415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.466995] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.467136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.482809] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.500884] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.500998] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.501077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.501410] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.501768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.501812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.501854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.501897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.501940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.501990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.502033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.502075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.502118] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.502166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.502211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.502256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.502321] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.502365] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.502418] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.503085] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.503134] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.503177] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.503216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.504387] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.505104] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.505161] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.505283] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.505327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.505372] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.505416] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.505809] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.505855] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.505901] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.505945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.505988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.506031] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.506073] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.506081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.506123] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.506129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.506172] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.506215] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.506259] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.506302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.506344] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.506389] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.506431] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.507193] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.507237] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.507280] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.507349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.507404] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.510581] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.510739] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.510777] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.511070] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.511125] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.511165] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.511223] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.511969] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.512296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.512340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.512384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.512427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.512724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.512767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.512810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.512853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.512896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.512939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.512987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.513032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.513106] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.513149] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.514892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.514937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.514981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.515993] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.516039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.517082] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.518492] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.519496] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.539136] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.539196] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.539373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.539748] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.539898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.553006] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.570893] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.571005] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.571084] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.571405] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.571510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.571553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.571599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.571642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.571684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.571731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.571774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.571817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.571860] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.571908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.571954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.571999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.572062] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.572105] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.572159] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.572220] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.572264] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.572307] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.572346] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.572929] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.573096] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.573132] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.573253] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.573296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.573341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.573384] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.573426] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.573516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.573561] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.573604] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.573647] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.573690] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.573733] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.573741] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.573783] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.573789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.573833] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.573876] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.573919] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.573962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.574005] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.574050] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.574092] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.574136] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.574181] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.574223] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.574287] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.574341] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.574385] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.574547] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.574585] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.574875] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.574928] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.574971] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.575028] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.575507] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.575843] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.575888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.575932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.575975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.576018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.576061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.576103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.576146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.576189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.576231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.576279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.576323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.576398] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.576490] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.578107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.578152] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.578196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.579031] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.579075] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.579816] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.579861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.580912] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.583042] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.584125] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.601041] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.601100] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.601271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.601708] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.601854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.617655] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.636193] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.636308] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.636389] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.636773] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.636820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.636863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.636906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.636949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.636992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.637041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.637084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.637126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.637169] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.637216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.637262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.637307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.637371] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.637414] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.637573] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.637640] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.637687] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.637731] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.637770] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.638329] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.638566] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.638625] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.638809] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.638878] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.638927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.638972] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.639016] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.639060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.639105] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.639148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.639191] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.639233] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.639275] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.639284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.639326] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.639332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.639375] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.639418] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.639506] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.639549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.639591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.639636] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.639678] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.639721] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.639763] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.639806] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.639881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.639937] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.639983] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.640190] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.640229] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.640546] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.640600] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.640641] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.640697] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.640956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.641273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.641317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.641360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.641403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.641467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.641510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.641554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.641597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.641640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.641683] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.641730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.641775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.641849] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.641892] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.643872] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.643918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.643963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.644838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.644883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.645985] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.646032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.647221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.648533] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.649684] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.666566] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.666625] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.666797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.667126] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.667263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.683270] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.700696] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.700809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.700888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.701208] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.701252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.701295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.701337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.701380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.701423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.701920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.701964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.702006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.702050] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.702096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.702142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.702186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.702250] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.702292] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.702346] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.702406] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.702921] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.702965] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.703003] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.704169] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.704348] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.704571] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.704699] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.704742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.704786] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.704830] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.704872] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.704916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.704959] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.705002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.705045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.705087] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.705129] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.705135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.705177] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.705183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.705226] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.705269] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.705311] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.705353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.705396] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.706179] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.706222] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.706267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.706310] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.706353] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.706418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.706764] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.706808] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.706955] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.706993] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.707281] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.707334] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.707374] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.707799] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.708057] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.708377] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.708420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.708717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.708760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.708803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.708846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.708889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.708931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.708974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.709016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.709065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.709109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.709184] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.709227] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.711140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.711186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.711231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.712328] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.712374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.713641] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.715740] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.716772] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.733650] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.733707] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.733876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.734208] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.734348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.750318] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.768689] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.768802] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.768881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.769200] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.769244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.769287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.769330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.769372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.769415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.769675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.769718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.769761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.769805] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.769853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.769898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.769943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.770005] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.770048] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.770101] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.770162] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.770206] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.770249] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.770288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.770890] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.771596] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.771653] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.771772] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.771815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.771860] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.771904] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.771946] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.771989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.772032] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.772075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.772118] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.772160] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.772202] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.772208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.772250] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.772255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.772298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.772341] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.772384] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.772426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.772505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.772554] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.772598] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.772645] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.772689] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.772734] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.772796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.772848] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.772894] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.773040] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.773078] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.773374] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.773466] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.773510] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.773567] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.773831] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.774158] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.774203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.774246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.774289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.774333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.774377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.774420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.774514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.774557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.774603] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.774651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.774696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.774770] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.774813] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.776241] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.776287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.776332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.777189] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.777234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.778607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.780709] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.781742] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.798630] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.798689] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.798862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.799218] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.799348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.815327] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.833878] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.833993] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.834077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.834403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.834514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.834562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.834607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.834654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.834698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.834751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.834794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.834837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.834880] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.834928] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.834974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.835019] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.835086] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.835129] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.835184] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.835246] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.835291] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.835335] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.835374] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.835958] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.836130] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.836181] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.836306] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.836350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.836395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.836481] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.836525] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.836574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.836620] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.836663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.836710] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.836753] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.836795] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.836803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.836845] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.836851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.836894] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.836937] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.836980] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.837022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.837064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.837109] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.837151] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.837195] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.837240] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.837283] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.837349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.837404] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.837481] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.837631] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.837669] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.837958] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.838012] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.838054] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.838111] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.838832] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.839161] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.839205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.839248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.839290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.839333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.839376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.839418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.839513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.839556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.839600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.839651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.839697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.839775] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.840104] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.841536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.841580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.841624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.842381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.842423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.843195] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.843240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.844427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.846563] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.847592] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.864564] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.864623] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.864794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.865104] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.865256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.881125] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.898917] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.899032] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.899112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.899490] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.899538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.899590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.899636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.899679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.899722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.899771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.899815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.899859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.899902] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.899950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.899996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.900041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.900108] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.900150] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.900204] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.900266] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.900310] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.900354] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.900392] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.900986] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.901167] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.901219] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.901341] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.901385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.901429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.901524] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.901570] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.901618] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.901664] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.901708] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.901752] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.901797] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.901839] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.901847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.901890] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.901896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.901940] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.901983] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.902027] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.902069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.902112] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.902157] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.902200] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.902243] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.902286] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.902329] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.902393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.902476] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.902523] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.902673] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.902711] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.903002] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.903055] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.903096] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.903154] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.903891] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.904215] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.904259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.904303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.904345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.904388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.904431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.904519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.904738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.904781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.904825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.904873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.904918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.904993] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.905037] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.906509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.906554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.906598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.907351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.907393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.908166] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.908212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.909317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.911412] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.912420] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.929301] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.929359] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.929788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.930189] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.930336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.946057] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.963855] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.963968] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.964047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.964367] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.964411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.964492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.964545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.964591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.964636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.964684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.964730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.964773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.964816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.964863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.964909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.964954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.965016] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.965060] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.965113] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.965175] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.965219] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.965263] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 579.965301] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 579.965910] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.966624] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.966680] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.966802] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 579.966845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 579.966890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 579.966933] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 579.966975] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 579.967019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.967062] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 579.967104] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.967147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 579.967189] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.967231] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 579.967237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.967279] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 579.967285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.967328] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 579.967371] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 579.967414] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 579.967503] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 579.967552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 579.967599] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 579.967643] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 579.967689] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.967735] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.967780] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 579.967843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.967897] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.967941] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.968093] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 579.968132] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 579.968428] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 579.968514] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.968555] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 579.968612] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 579.968904] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.969227] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 579.969271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 579.969315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.969358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.969402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.969483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 579.969526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 579.969569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 579.969618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 579.969664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 579.969714] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 579.969760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.969836] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 579.969879] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.972100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.972147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 579.972192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 579.973510] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 579.973557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 579.974798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 579.976902] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 579.977916] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 579.994792] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 579.994851] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.995023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 579.995342] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 579.995535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.011515] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.029705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.029818] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.029897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.030219] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.030263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.030306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.030349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.030392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.030499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.030548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.030593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.030637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.030680] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.030728] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.030774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.030819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.030883] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.030925] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.030979] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.031039] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.031083] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.031126] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 580.031164] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 580.031756] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.031934] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.031986] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.032104] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 580.032147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 580.032191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 580.032235] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 580.032277] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 580.032320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.032363] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 580.032405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.032490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 580.032536] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.032580] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 580.032590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.032633] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 580.032642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.032688] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.032731] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 580.032775] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 580.032818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 580.032860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.032905] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 580.032948] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 580.032991] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.033035] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.033078] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.033138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.033191] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.033235] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.033373] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.033411] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.033725] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 580.033778] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.033818] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.033875] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.034156] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.034479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.034525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.034568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.034611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.034653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.034696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.034739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.034781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.034823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.034866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.034912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.034957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.035029] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.035072] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.036559] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.036602] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.036647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 580.037404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.037485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.038207] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 580.038250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 580.039320] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 580.040543] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 580.046320] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.063230] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.063289] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.063543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.063869] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.064010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.079835] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.097697] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.097809] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.097888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.098211] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.098255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.098298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.098341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.098383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.098426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.098539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.098582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.098628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.098671] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.098719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.098764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.098809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.098872] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.098914] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.098968] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.099029] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.099073] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.099117] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 580.099155] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 580.099732] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.099900] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.099952] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.100072] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 580.100115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 580.100160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 580.100204] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 580.100246] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 580.100291] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.100334] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 580.100377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.100421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 580.100523] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.100566] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 580.100575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.100617] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 580.100623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.100667] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.100711] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 580.100754] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 580.100797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 580.100839] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.100884] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 580.100927] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 580.100971] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.101014] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.101058] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.101123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.101178] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.101221] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.101369] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.101407] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.101728] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 580.101782] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.101822] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.101879] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.102785] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.103106] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.103150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.103193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.103236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.103278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.103321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.103364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.103406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.103485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.103528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.103576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.103621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.103696] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.103740] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.105440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.105512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.105557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 580.106305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.106347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.107245] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 580.107291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 580.108424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 580.110559] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 580.111585] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.128531] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.128590] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.128762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.129086] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.129224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.145176] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.162900] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.163014] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.163793] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.164164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.164209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.164252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.164295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.164338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.164381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.164430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.164516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.164561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.164606] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.164656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.164702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.164749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.164812] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.164855] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.164908] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.164970] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.165014] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.165059] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 580.165097] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 580.165691] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.165866] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.165919] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.166043] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 580.166086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 580.166131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 580.166174] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 580.166216] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 580.166261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.166304] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 580.166347] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.166390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 580.166432] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.166512] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 580.166519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.166561] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 580.166567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.166610] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.166652] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 580.166695] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 580.166738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 580.166783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.166830] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 580.166874] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 580.166919] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.166964] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.167008] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.167074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.167127] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.167171] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.167318] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.167356] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.167684] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 580.167741] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.167784] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.167841] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.168334] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.168801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.168847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.168891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.168934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.168977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.169021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.169064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.169109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.169152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.169195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.169243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.169288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.169363] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.169406] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.171124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.171168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.171212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 580.172123] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 580.172169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 580.173228] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 580.175323] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 580.176344] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.193233] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.193291] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.193837] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.194258] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.194410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.209938] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.227797] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.227910] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.227988] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.228308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.228352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.228395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.228808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.228851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.228894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.228944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.228987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.229030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.229073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.229120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.229166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.229210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.229273] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.229315] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.229369] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.229429] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.230039] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.230084] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 580.230122] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 580.231289] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.231569] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.231620] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.231742] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 580.231785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 580.231830] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 580.231873] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 580.231915] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 580.231959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.232003] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 580.232046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.232089] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 580.232131] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.232173] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 580.232180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.232221] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 580.232227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.232271] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.232314] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 580.232356] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 580.232399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 580.233227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.233273] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 580.233315] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 580.233361] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.233404] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.233702] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.233772] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.233826] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.233870] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.234018] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.234056] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.234346] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 580.234399] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.234852] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.234962] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.235211] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.235678] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.235724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.235769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.235812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.235855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.235898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.235941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.235984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.236026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.236069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.236118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.236163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.236239] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.236282] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.242600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.242648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.242693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 580.243519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.243562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.244314] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 580.244361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 580.245516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 580.247536] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 580.248597] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.265514] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.265573] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.265744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.266076] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.266213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.282112] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.299699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.299812] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.299892] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.300212] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.300256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.300299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.300341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.300384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.300427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.300526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.300575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.300621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.300666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.300714] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.300762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.300807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.300873] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.300916] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.300970] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.301030] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.301075] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.301118] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:34 BXT-2 kernel: [ 580.301157] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:34 BXT-2 kernel: [ 580.301790] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.302472] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.302525] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.302650] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:34 BXT-2 kernel: [ 580.302694] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:34 BXT-2 kernel: [ 580.302738] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:34 BXT-2 kernel: [ 580.302782] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:34 BXT-2 kernel: [ 580.302824] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:34 BXT-2 kernel: [ 580.302868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.302911] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:34 BXT-2 kernel: [ 580.302954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.302997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:34 BXT-2 kernel: [ 580.303039] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.303081] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:34 BXT-2 kernel: [ 580.303088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.303130] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:34 BXT-2 kernel: [ 580.303135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.303178] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:34 BXT-2 kernel: [ 580.303221] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:34 BXT-2 kernel: [ 580.303264] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:34 BXT-2 kernel: [ 580.303306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:34 BXT-2 kernel: [ 580.303348] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:34 BXT-2 kernel: [ 580.303393] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:34 BXT-2 kernel: [ 580.303469] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:34 BXT-2 kernel: [ 580.303519] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.303564] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.303609] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:34 BXT-2 kernel: [ 580.303676] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.303731] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.303775] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.303919] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:34 BXT-2 kernel: [ 580.303957] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:34 BXT-2 kernel: [ 580.304248] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:34 BXT-2 kernel: [ 580.304301] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.304341] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:34 BXT-2 kernel: [ 580.304398] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:34 BXT-2 kernel: [ 580.305131] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.305506] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.305711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:34 BXT-2 kernel: [ 580.305755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.305797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.305840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.305883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:34 BXT-2 kernel: [ 580.305925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:34 BXT-2 kernel: [ 580.305968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:34 BXT-2 kernel: [ 580.306010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:34 BXT-2 kernel: [ 580.306053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:34 BXT-2 kernel: [ 580.306101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:34 BXT-2 kernel: [ 580.306145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.306219] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:34 BXT-2 kernel: [ 580.306262] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.307923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.307968] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.308012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:34 BXT-2 kernel: [ 580.308795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.308839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:34 BXT-2 kernel: [ 580.309705] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:34 BXT-2 kernel: [ 580.309751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:34 BXT-2 kernel: [ 580.310804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:34 BXT-2 kernel: [ 580.312891] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:34 BXT-2 kernel: [ 580.313936] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:34 BXT-2 kernel: [ 580.330820] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:34 BXT-2 kernel: [ 580.330879] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.331055] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:34 BXT-2 kernel: [ 580.331460] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:34 BXT-2 kernel: [ 580.331806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:34 BXT-2 kernel: [ 580.347488] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.364787] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.364899] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.364979] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.365303] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.365347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.365390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.365498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.365546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.365594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.365644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.365694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.365740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.365783] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.365832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.365877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.366402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.366516] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.366559] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.366613] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.366674] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.366719] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.366761] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.366800] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.367356] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.367581] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.367639] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.367763] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.367806] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.367851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.367895] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.367937] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.367981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.368024] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.368067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.368110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.368153] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.368195] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.368201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.368243] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.368249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.368292] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.368334] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.368377] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.368420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.368503] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.368551] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.368595] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.368640] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.368685] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.368731] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.368799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.368854] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.368898] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.369489] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.369530] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.370059] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.370498] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.370729] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.370787] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.372855] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.373217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.373277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.373328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.373379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.373424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.374173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.374220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.374264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.374308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.374353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.374407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.375085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.375183] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.375239] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.377193] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.377238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.377283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.378049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.378093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.378959] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.379004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.380095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.381486] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.382508] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.399374] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.399432] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.399650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.399966] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.400113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.416078] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.433749] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.433862] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.433941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.434258] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.434302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.434345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.434388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.434431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.434512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.434565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.434613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.434658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.434703] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.434758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.434807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.434852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.434919] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.434962] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.435016] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.435077] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.435121] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.435165] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.435205] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.435793] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.435972] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.436010] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.436131] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.436176] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.436221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.436265] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.436308] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.436352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.436396] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.436475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.436520] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.436566] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.436610] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.436621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.436665] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.436673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.436719] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.436762] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.436805] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.436848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.436890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.436935] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.436977] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.437020] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.437066] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.437109] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.437174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.437229] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.437273] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.437425] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.437520] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.437819] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.437874] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.437916] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.437973] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.438302] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.438636] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.438682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.438725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.438769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.438812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.438856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.438899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.438944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.438987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.439031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.439079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.439124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.439198] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.439242] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.440710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.440756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.440800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.441723] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.441766] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.442637] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.442681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.443862] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.445966] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.447035] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.463930] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.463988] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.464158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.464526] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.464668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.480586] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.498796] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.498911] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.498993] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.499319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.499364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.499407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.499507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.499556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.499601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.499653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.499706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.499752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.499796] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.499844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.499890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.499934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.500000] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.500043] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.500098] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.500160] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.500204] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.500247] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.500286] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.500882] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.501649] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.501704] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.501826] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.501870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.501915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.501959] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.502001] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.502045] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.502089] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.502132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.502175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.502217] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.502259] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.502267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.502309] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.502314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.502357] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.502400] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.502485] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.502531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.502574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.502622] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.502665] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.502711] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.502756] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.502801] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.502868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.502922] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.502966] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.504580] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.504621] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.504918] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.504975] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.505017] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.505074] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.505340] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.505669] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.505716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.505759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.505801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.505844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.505887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.505929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.505972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.506014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.506057] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.506104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.506150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.506223] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.506266] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.508085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.508130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.508175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.508942] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.508985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.509723] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.509767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.510816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.512914] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.513966] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.530884] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.530945] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.531117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.531585] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.531733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.547547] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.566076] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.566188] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.566268] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.566636] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.566681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.566725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.566768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.566812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.566855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.566902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.566945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.566989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.567032] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.567080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.567125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.567171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.567236] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.567278] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.567332] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.567393] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.567464] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.567511] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.567552] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.568104] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.568272] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.568328] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.568483] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.568530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.568578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.568622] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.568665] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.568709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.568753] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.568795] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.568839] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.568882] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.568924] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.568931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.568973] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.568980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.569024] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.569067] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.569110] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.569153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.569195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.569243] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.569285] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.569328] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.569371] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.569414] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.569501] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.569554] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.569600] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.569744] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.569782] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.570071] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.570124] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.570164] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.570221] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.570925] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.571251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.571295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.571338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.571381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.571423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.571511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.571558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.571602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.571645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.571688] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.571736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.571781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.571855] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.571898] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.573352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.573398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.573494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.574274] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.574318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.575203] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.575249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.576549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.578672] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.580639] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.597535] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.597594] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.597765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.598092] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.598233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.614219] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.632745] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.632858] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.632937] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.633264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.633309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.633353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.633396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.633478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.633523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.633574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.633617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.633661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.633705] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.633754] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.633799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.633845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.633914] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.633958] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.634013] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.634075] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.634120] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.634164] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.634203] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.634807] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.635550] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.635589] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.635709] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.635753] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.635798] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.635842] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.635885] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.635929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.635972] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.636015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.636058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.636100] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.636142] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.636149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.636191] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.636197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.636240] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.636283] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.636326] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.636368] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.636411] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.636487] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.636567] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.636611] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.636657] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.636700] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.636764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.636817] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.636860] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.637000] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.637038] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.637328] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.637382] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.637425] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.637511] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.637756] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.638082] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.638126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.638170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.638214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.638257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.638300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.638344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.638388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.638431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.638510] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.638559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.638606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.638682] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.638726] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.640175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.640218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.640263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.641045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.641089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.641818] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.641861] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.642899] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.644988] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.646040] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.662925] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.662983] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.663153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.663592] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.663731] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.679970] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.696499] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.696786] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.696867] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.697190] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.697233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.697277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.697319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.697362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.697405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.697482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.697528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.697574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.697619] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.697669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.697715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.697760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.697826] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.697870] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.697925] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.697987] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.698031] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.698075] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.698114] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.698689] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.698903] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.698954] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.699073] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.699117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.699162] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.699206] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.699248] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.699292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.699335] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.699377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.699421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.699496] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.699543] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.699554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.699598] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.699607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.699653] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.699698] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.699744] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.699788] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.699835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.699880] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.699923] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.699966] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.700010] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.700054] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.700117] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.700170] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.700214] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.700364] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.700403] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.700718] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.700773] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.700815] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.700872] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.701119] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.701477] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.701522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.701566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.701610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.701653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.701697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.701740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.701784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.701827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.701871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.701918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.701964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.702038] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.702082] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.703560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.703604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.703648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.704426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.704506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.705240] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.705284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.706335] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.707508] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.708498] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.725391] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.725541] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.725710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.726092] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.726233] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.742089] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.760614] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.760728] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.760808] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.761128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.761172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.761215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.761258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.761301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.761344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.761391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.761497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.761545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.761592] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.761644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.761691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.761737] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.761805] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.761847] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.761901] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.761962] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.762005] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.762048] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.762087] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.762672] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.762858] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.762913] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.763030] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.763074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.763120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.763164] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.763207] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.763253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.763296] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.763339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.763383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.763426] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.763493] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.763501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.763544] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.763550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.763594] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.763638] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.763682] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.763725] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.763768] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.763813] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.763856] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.763899] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.763943] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.763986] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.764049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.764103] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.764147] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.764295] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.764334] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.764643] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.764698] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.764741] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.764798] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.765043] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.765367] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.765411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.765501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.765544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.765587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.765630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.765673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.765716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.765762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.765807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.765857] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.765902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.765976] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.766019] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.767548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.767591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.767636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.768396] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.768486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.769223] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.769266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.770319] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.772409] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.773482] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.790386] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.790484] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.790660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.791057] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.791200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.807068] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.824874] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.824987] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.825067] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.825390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.825506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.825551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.825597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.825640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.825684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.825732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.825775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.825819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.825863] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.825911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.825959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.826539] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.826647] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.826914] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.827145] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.827209] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.827255] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.827299] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.827338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.827925] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.828101] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.828157] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.828274] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.828318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.828364] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.828409] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.828483] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.828530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.828577] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.828622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.828668] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.828711] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.828754] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.828761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.828803] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.828809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.828853] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.828896] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.828940] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.828983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.829025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.829071] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.829114] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.829157] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.829201] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.829244] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.829307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.829359] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.829403] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.829570] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.829608] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.829900] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.829954] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.829996] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.830053] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.830301] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.830641] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.830686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.830731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.830775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.830819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.830865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.830910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.830955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.830998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.831042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.831091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.831136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.831210] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.831253] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.832747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.832790] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.832835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.833619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.833662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.834398] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.834479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.835538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.837632] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.838703] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.855626] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.855684] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.855856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.856242] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.856364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.872315] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.889200] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.889314] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.889393] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.889781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.889827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.889870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.889915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.889958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.890004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.890053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.890096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.890139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.890183] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.890231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.890277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.890322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.890387] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.890467] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.890521] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.890584] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.890629] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.890673] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.890711] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.891264] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.891486] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.891537] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.891663] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.891708] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.891753] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.891797] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.891839] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.891883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.891927] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.891970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.892015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.892057] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.892098] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.892106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.892147] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.892153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.892196] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.892239] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.892281] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.892323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.892365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.892410] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.892499] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.892544] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.892587] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.892630] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.892693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.892747] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.892790] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.892934] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.892971] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.893262] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.893315] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.893357] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.893414] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.894532] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.894857] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.894901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.894945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.894987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.895030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.895073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.895116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.895158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.895201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.895244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.895290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.895335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.895408] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.895482] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.897272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.897318] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.897363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.898417] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.898508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.900225] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.901550] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.902571] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.919479] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.919537] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.919709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.920038] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.920172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.936102] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.953938] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.954052] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.954130] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.954483] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.954529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.954572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.954619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.954662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.954705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.954752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.954795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.954838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.954880] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.954928] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.954973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.955020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.955085] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.955128] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.955182] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.955243] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.955287] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.955331] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 580.955370] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 580.955956] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.956118] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.956169] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.956294] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 580.956338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 580.956383] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 580.956427] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 580.956545] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 580.956590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.956634] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 580.956677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.956721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 580.956764] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.956806] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 580.956815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.956857] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 580.956863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.956907] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 580.956950] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 580.956993] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 580.957036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 580.957079] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 580.957124] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 580.957167] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 580.957212] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.957255] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.957298] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 580.957365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.957419] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.957484] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.957651] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 580.957689] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 580.957979] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 580.958032] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.958074] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 580.958131] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 580.958661] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.958990] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 580.959033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 580.959077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.959119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.959161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.959204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 580.959247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 580.959290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 580.959333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 580.959376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 580.959422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 580.959528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.959605] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 580.959648] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.961277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.961322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 580.961367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 580.962245] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 580.962289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 580.963554] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 580.965656] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 580.966724] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 580.983615] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 580.983673] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.983843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 580.984176] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 580.984311] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.000238] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.018797] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.018911] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.018991] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.019317] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.019362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.019405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.019902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.019946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.019990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.020042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.020085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.020128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.020171] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.020219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.020264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.020309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.020376] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.020420] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.020879] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.020945] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.020993] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.021036] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 581.021075] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 581.022250] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.022735] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.022799] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.022993] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 581.023067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 581.023120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 581.023166] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 581.023209] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 581.023255] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.023300] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 581.023343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.023386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 581.023428] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.023838] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 581.023848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.023892] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 581.023898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.023942] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.023985] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 581.024029] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 581.024072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 581.024115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.024161] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 581.024203] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 581.024248] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.024293] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.024336] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.024403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.024822] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.024866] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.025015] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.025053] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.025346] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 581.025399] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.025752] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.025811] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.026128] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.026760] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.026807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.026851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.026894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.026936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.026979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.027022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.027065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.027108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.027151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.027201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.027245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.027321] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.027364] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.029224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.029271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.029315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 581.030307] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 581.030355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 581.031606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 581.033708] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 581.034732] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.054235] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.054294] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.054519] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.055014] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.055137] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.068263] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.086794] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.086906] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.086985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.087301] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.087346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.087389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.087432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.087847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.087890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.087940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.087984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.088029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.088073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.088121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.088165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.088210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.088275] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.088319] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.088372] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.088432] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.088994] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.089037] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 581.089077] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 581.090244] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.090549] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.090599] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.090722] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 581.090765] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 581.090810] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 581.090853] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 581.090896] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 581.090940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.090982] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 581.091025] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.091068] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 581.091110] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.091152] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 581.091159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.091200] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 581.091206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.091249] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.091291] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 581.091334] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 581.091376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 581.091418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.092231] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 581.092273] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 581.092318] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.092361] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.092404] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.092715] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.092770] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.092813] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.092960] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.092998] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.093286] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 581.093339] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.093379] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.093831] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.094091] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.094412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.094675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.094719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.094762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.094805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.094847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.094890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.094933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.094975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.095018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.095067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.095111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.095186] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.095229] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.097268] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.097314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.097359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 581.098513] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 581.098560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 581.100097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 581.101567] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 581.102577] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.119444] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.119530] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.119702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.120023] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.120161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.136076] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.153698] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.153811] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.153890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.154211] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.154270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.154313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.154356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.154399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.154508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.154883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.154926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.154970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.155013] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.155061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.155108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.155153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.155219] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.155262] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.155316] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.155377] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.155422] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.155509] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 581.155548] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 581.156111] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.156295] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.156347] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.156516] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 581.156561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 581.156606] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 581.156650] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 581.156693] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 581.156737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.156781] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 581.156824] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.156868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 581.156910] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.156953] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 581.156960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.157003] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 581.157009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.157053] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.157096] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 581.157140] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 581.157183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 581.157225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.157270] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 581.157313] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 581.157356] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.157400] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.157468] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.157530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.157583] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.157627] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.157774] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.157812] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.158101] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 581.158155] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.158195] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.158252] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.158678] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.159011] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.159055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.159098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.159140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.159183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.159226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.159269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.159311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.159354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.159396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.159493] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.159540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.159614] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.159657] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.161212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.161256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.161301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 581.162163] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 581.162208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 581.163318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 581.165414] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 581.166400] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.183316] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.183375] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.183607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.184011] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.184159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.199956] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.217944] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.218056] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.218134] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.218483] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.218530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.218573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.218618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.218664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.218706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.218753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.218796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.218838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.218881] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.218929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.218975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.219021] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.219182] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.219226] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.219280] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.219342] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.219387] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.219457] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 581.219496] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 581.220048] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.220219] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.220273] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.220395] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 581.220524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 581.220570] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 581.220614] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 581.220657] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 581.220702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.220746] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 581.220789] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.220833] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 581.220876] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.220918] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 581.220926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.220969] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 581.220975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.221019] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.221063] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 581.221107] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 581.221150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 581.221192] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.221238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 581.221281] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 581.221324] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.221367] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.221410] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.221494] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.221548] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.221592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.221759] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.221797] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.222086] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 581.222140] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.222182] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.222239] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.222759] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.223083] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.223127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.223170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.223213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.223257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.223300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.223343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.223385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.223428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.223535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.223584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.223630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.223704] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.223747] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.225411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.225481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.225526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 581.226286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.226328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.227231] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 581.227277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 581.228555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 581.230541] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 581.231645] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.248545] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.248604] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.248775] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.249107] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.249247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.265178] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.282980] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.283092] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.283171] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.283713] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.283759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.283803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.283846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.283889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.283932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.283980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.284023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.284066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.284109] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.284156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.284201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.284246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.284311] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.284353] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.284407] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.285085] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.285132] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.285175] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:35 BXT-2 kernel: [ 581.285213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:35 BXT-2 kernel: [ 581.286377] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.287092] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.287141] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.287261] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:35 BXT-2 kernel: [ 581.287305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:35 BXT-2 kernel: [ 581.287350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:35 BXT-2 kernel: [ 581.287393] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:35 BXT-2 kernel: [ 581.287745] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:35 BXT-2 kernel: [ 581.287792] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.287837] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:35 BXT-2 kernel: [ 581.287879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.287923] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:35 BXT-2 kernel: [ 581.287965] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.288007] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:35 BXT-2 kernel: [ 581.288016] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.288058] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:35 BXT-2 kernel: [ 581.288064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.288106] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:35 BXT-2 kernel: [ 581.288149] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:35 BXT-2 kernel: [ 581.288192] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:35 BXT-2 kernel: [ 581.288234] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:35 BXT-2 kernel: [ 581.288276] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:35 BXT-2 kernel: [ 581.288321] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:35 BXT-2 kernel: [ 581.288363] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:35 BXT-2 kernel: [ 581.288406] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.289156] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.289199] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:35 BXT-2 kernel: [ 581.289266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.289320] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.289363] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.289759] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:35 BXT-2 kernel: [ 581.289798] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:35 BXT-2 kernel: [ 581.290087] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:35 BXT-2 kernel: [ 581.290141] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.290181] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:35 BXT-2 kernel: [ 581.290238] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:35 BXT-2 kernel: [ 581.290787] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.291105] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.291148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:35 BXT-2 kernel: [ 581.291191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.291234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.291276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.291319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:35 BXT-2 kernel: [ 581.291362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:35 BXT-2 kernel: [ 581.291405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:35 BXT-2 kernel: [ 581.291805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:35 BXT-2 kernel: [ 581.291848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:35 BXT-2 kernel: [ 581.291896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:35 BXT-2 kernel: [ 581.291941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.292015] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:35 BXT-2 kernel: [ 581.292058] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.293760] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.293805] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.293849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:35 BXT-2 kernel: [ 581.294694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.294737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:35 BXT-2 kernel: [ 581.295621] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:35 BXT-2 kernel: [ 581.295666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:35 BXT-2 kernel: [ 581.296832] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:35 BXT-2 kernel: [ 581.298925] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:35 BXT-2 kernel: [ 581.299944] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:35 BXT-2 kernel: [ 581.316837] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:35 BXT-2 kernel: [ 581.316896] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.317068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:35 BXT-2 kernel: [ 581.317689] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:35 BXT-2 kernel: [ 581.317853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:35 BXT-2 kernel: [ 581.333488] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.351728] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.351842] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.351921] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.352250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.352294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.352337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.352381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.352425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.352516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.352568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.352613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.352658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.352702] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.352749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.352797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.352843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.352907] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.352950] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.353011] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.353090] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.353151] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.353203] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.353249] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.354477] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.354678] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.354732] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.354875] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.354928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.354981] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.355035] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.355085] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.355139] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.355192] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.355243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.355295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.355344] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.355393] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.355463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.355514] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.355522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.355568] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.355614] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.355659] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.355703] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.355748] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.355795] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.355838] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.355884] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.355927] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.355970] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.356038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.356092] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.356135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.357986] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.358027] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.358317] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.358373] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.358413] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.358550] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.358975] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.359301] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.359344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.359388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.359431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.359764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.359809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.359852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.359896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.359940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.359984] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.360032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.360077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.360152] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.360196] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.361758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.361802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.361846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.362703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.362747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.363624] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.363669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.364809] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.366909] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.367995] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.384888] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.384946] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.385117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.385722] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.385882] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.401591] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.419804] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.419917] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.419996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.420319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.420363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.420406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.420808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.420851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.420894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.420944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.420987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.421030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.421073] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.421121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.421166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.421211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.421276] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.421318] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.421371] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.421432] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.422048] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.422092] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.422130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.423299] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.423578] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.423633] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.423756] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.423800] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.423844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.423887] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.423929] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.423973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.424018] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.424061] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.424104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.424146] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.424188] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.424194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.424236] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.424242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.424285] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.424328] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.424370] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.424413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.425195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.425240] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.425282] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.425327] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.425370] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.425412] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.425759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.425815] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.425859] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.426006] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.426044] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.426335] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.426388] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.426763] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.426869] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.427103] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.427581] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.427627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.427671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.427713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.427756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.427799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.427842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.427885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.427927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.427970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.428017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.428062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.428136] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.428179] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.430046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.430093] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.430139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.431054] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.431099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.432155] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.434248] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.435212] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.452092] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.452151] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.452323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.452915] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.453068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.468721] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.486753] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.486867] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.486948] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.487276] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.487322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.487366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.487409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.487510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.487553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.487603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.487645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.487688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.487731] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.487779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.487824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.487869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.487934] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.487977] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.488031] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.488092] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.488135] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.488179] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.488217] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.488849] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.489609] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.489654] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.489784] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.489829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.489878] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.489929] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.489979] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.490035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.490091] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.490143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.490194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.490246] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.490295] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.490306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.490359] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.490366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.490417] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.490705] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.490762] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.490816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.490860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.490907] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.490955] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.491002] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.491048] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.491093] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.491165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.491225] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.491270] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.491425] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.491496] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.491790] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.491846] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.491888] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.491947] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.492228] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.492564] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.492610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.492655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.492699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.492743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.492788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.492832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.492875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.492919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.492963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.493012] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.493058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.493139] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.493183] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.498837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.498884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.498929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.499775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.499821] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.500566] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.500613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.501763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.503873] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.504967] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.521844] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.521902] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.522074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.522397] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.522612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.538558] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.556813] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.556925] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.557004] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.557330] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.557375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.557418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.557521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.557567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.557612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.557660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.557704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.557747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.557791] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.557839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.557885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.557931] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.557997] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.558040] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.558094] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.558155] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.558200] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.558244] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.558283] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.558865] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.559036] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.559085] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.559205] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.559249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.559293] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.559337] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.559379] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.559423] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.559502] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.559548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.559595] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.559640] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.559684] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.559692] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.559737] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.559744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.559788] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.559833] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.559878] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.559921] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.559964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.560010] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.560053] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.560097] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.560142] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.560185] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.560250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.560305] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.560349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.560524] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.560563] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.560859] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.560913] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.560953] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.561011] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.561322] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.561647] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.561692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.561738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.561783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.561827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.561872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.561915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.561958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.562003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.562046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.562093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.562137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.562213] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.562256] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.563721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.563765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.563810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.564773] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.564816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.565554] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.565600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.566644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.568738] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.569771] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.586676] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.586735] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.586907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.587224] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.587373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.603298] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.621733] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.621866] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.621974] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.622337] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.622398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.622514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.622560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.622608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.622654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.622707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.622751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.622802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.622852] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.622912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.622971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.623020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.623101] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.623147] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.623204] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.623270] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.623318] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.623368] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.623411] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.624254] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.624986] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.625041] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.625164] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.625209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.625253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.625297] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.625339] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.625384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.625427] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.625517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.625563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.625610] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.625653] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.625663] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.625707] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.625714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.625760] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.625804] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.625850] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.625893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.625938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.625984] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.626027] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.626070] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.626114] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.626157] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.626227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.626282] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.626326] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.626539] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.626578] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.626880] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.626937] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.626979] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.627038] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.627306] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.627659] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.627704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.627748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.627792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.627837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.627880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.627923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.627967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.628010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.628054] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.628102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.628147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.628222] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.628265] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.629902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.629946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.629991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.630867] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.630911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.631954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.634048] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.635079] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.651986] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.652046] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.652216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.652599] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.652749] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.668650] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.685751] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.685864] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.685943] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.686267] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.686311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.686354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.686397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.686491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.686535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.686584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.686627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.686671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.686716] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.686763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.686808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.686853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.686914] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.686957] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.687010] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.687071] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.687116] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.687159] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.687198] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.687775] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.687949] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.687988] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.688109] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.688152] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.688198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.688242] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.688285] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.688329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.688373] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.688416] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.688483] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.688526] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.688569] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.688576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.688618] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.688625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.688669] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.688712] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.688755] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.688798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.688841] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.689263] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.689596] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.689643] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.689686] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.689729] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.689796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.689851] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.689894] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.690049] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.690086] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.690375] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.690515] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.690556] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.690613] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.691148] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.691505] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.691550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.691594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.691637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.691680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.691724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.691768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.691811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.691854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.691898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.691945] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.691990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.692065] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.692108] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.693882] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.693926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.693972] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.694904] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.694949] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.696050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.698143] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.699117] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.716157] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.716216] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.716387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.716990] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.717134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.732636] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.750833] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.750945] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.751025] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.751351] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.751395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.751501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.751546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.751589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.751632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.751680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.751723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.751766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.751810] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.751857] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.751903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.751948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.752013] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.752055] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.752109] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.752172] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.752216] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.752259] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.752298] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.752887] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.753066] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.753117] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.753241] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.753285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.753330] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.753374] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.753416] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.753505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.753550] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.753593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.753636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.753678] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.753720] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.753729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.753770] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.753778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.753821] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.753864] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.753907] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.753951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.753993] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.754039] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.754081] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.754125] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.754168] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.754211] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.754276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.754331] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.754374] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.754562] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.754600] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.754891] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.754944] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.754987] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.755045] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.755830] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.756164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.756208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.756251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.756294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.756337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.756380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.756423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.756784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.756827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.756871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.756920] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.756965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.757040] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.757083] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.759024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.759070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.759114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.760179] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.760227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.762803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.764905] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.765959] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.782859] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.782918] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.783090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.783458] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.783601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.799537] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.817773] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.817886] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.817966] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.818289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.818333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.818377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.818420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.818506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.818550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.818601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.818644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.818688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.818732] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.818781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.818827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.818872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.818942] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.818985] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.819039] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.819101] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.819146] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.819190] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.819229] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.819850] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.820537] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.820593] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.820712] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.820756] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.820801] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.820845] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.820887] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.820931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.820974] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.821017] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.821060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.821102] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.821144] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.821151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.821193] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.821198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.821241] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.821284] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.821327] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.821370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.821412] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.821490] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.821536] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.821582] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.821627] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.821674] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.821738] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.821790] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.821836] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.821983] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.822020] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.822310] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.822364] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.822406] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.822499] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.822747] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.823066] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.823111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.823155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.823199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.823242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.823286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.823329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.823373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.823416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.823501] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.823551] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.823598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.823674] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.823718] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.825181] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.825225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.825270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.826056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.826099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.826860] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.826905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.827971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.830072] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.831089] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.847960] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.848018] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.848190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.848598] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.848747] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.864612] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.883141] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.883256] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.883336] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.883666] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.883712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.883757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.883800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.883844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.883888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.883936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.883980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.884024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.884067] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.884115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.884163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.884209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.884274] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.884317] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.884372] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.884472] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.884519] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.884565] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.884605] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.885155] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.885333] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.885388] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.885541] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.885585] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.885631] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.885676] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.885719] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.885763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.885807] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.885850] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.885894] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.885937] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.885980] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.885987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.886029] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.886036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.886079] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.886123] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.886166] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.886209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.886252] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.886297] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.886340] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.886383] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.886426] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.886494] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.886559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.886613] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.886659] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.886806] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.886844] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.887134] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.887796] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.887838] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.887894] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.888149] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.888480] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.888528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.888573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.888617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.888660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.888703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.888746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.888789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.888832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.888876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.888924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.888969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.889043] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.889087] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.890550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.890593] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.890638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.891399] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.891473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.892259] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.892307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.893653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.895835] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.896995] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.913879] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.913938] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.914108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.914473] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.914601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.930519] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.948863] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.948976] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.949055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.949373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.949418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.949504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.949549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.949594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.949637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.949687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.949730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.949772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.949816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.949863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.949908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.949953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.950014] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.950057] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.950110] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.950171] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.950213] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.950256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 581.950295] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 581.950872] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.951042] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.951090] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.951209] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 581.951253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 581.951298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 581.951342] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 581.951384] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 581.951428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.951547] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 581.951590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.951633] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 581.951676] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.951717] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 581.951725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.951767] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 581.951773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.951816] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 581.951859] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 581.951902] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 581.951944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 581.951986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 581.952031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 581.952073] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 581.952117] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.952159] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.952202] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 581.952266] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.952320] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.952363] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.954382] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 581.954422] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 581.954759] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 581.954815] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.954855] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 581.954912] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 581.955356] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.955691] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.955736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 581.955779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.955822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.955864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.955907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 581.955950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 581.955993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 581.956035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 581.956078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 581.956125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 581.956170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.956244] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 581.956288] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.958724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.958770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.958815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 581.959943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.959988] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 581.961065] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 581.961110] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 581.962210] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 581.964310] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 581.965327] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 581.982176] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 581.982234] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.982405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 581.983277] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 581.983422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 581.998879] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.016763] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.016876] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.016955] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.017274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.017318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.017362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.017404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.018088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.018131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.018180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.018223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.018266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.018309] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.018356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.018401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.019092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.019157] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.019200] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.019253] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.019314] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.019358] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.019401] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 582.020045] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 582.021213] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.021394] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.021807] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.021935] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 582.021978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 582.022023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 582.022067] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 582.022109] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 582.022154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.022196] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 582.022239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.022282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 582.022324] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.022366] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 582.022372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.022414] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 582.023222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.023282] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.023325] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 582.023369] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 582.023411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 582.023912] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.023959] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 582.024000] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 582.024046] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.024089] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.024131] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.024197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.024252] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.024295] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.025167] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.025208] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.025839] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 582.026146] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.026186] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.026243] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.026927] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.027251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.027295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.027338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.027381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.027424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.027972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.028015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.028058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.028100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.028144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.028193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.028237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.028312] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.028355] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.030381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.030426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.030879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 582.031827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.031870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.032821] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 582.032865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 582.034281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 582.036379] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 582.037399] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.054278] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.054336] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.054943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.055343] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.055893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.070993] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.089490] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.089601] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.089679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.089999] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.090043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.090087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.090129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.090172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.090215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.090261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.090304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.090346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.090389] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.091322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.091369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.091414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.091868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.091911] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.091965] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.092026] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.092070] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.092112] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 582.092151] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 582.093492] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.093669] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.093723] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.093840] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 582.093883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 582.093927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 582.093971] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 582.094013] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 582.094057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.094100] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 582.094143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.094186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 582.094228] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.094270] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 582.094277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.094318] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 582.094324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.094368] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.094410] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 582.095613] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 582.095657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 582.095699] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.095746] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 582.095788] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 582.095834] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.095877] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.095920] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.095988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.096042] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.096086] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.096238] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.096275] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.097382] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 582.097999] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.098041] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.098098] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.098355] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.099034] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.099080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.099124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.099166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.099209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.099252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.099295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.099337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.099380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.099423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.100219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.100264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.100341] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.100384] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.102245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.102289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.102334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 582.103398] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 582.103488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 582.104831] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 582.106927] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 582.107963] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.124833] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.124892] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.125063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.125925] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.126072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.141572] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.160071] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.160183] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.160262] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.160641] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.160686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.160730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.160773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.160815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.160858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.160906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.160949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.160992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.161035] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.161082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.161127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.161172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.161234] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.161276] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.161329] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.161389] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.161450] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.161493] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 582.161531] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 582.162078] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.162255] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.162303] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.162416] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 582.162481] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 582.162526] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 582.162569] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 582.162612] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 582.162656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.162699] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 582.162741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.162785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 582.162827] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.162869] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 582.162875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.162917] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 582.162923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.162966] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.163009] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 582.163051] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 582.163093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 582.163135] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.163180] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 582.163222] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 582.163265] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.163308] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.163350] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.163409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.163478] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.163522] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.166150] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.166191] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.166861] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 582.167171] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.167212] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.167270] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.167928] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.168249] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.168293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.168336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.168378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.168421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.168958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.169001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.169044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.169087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.169130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.169178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.169223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.169297] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.169340] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.171374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.171418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.171853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 582.172830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.172873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.173846] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 582.173891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 582.175308] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 582.177408] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 582.178438] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.195340] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.195398] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.196017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.196743] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.196902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.212045] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.230544] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.230656] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.230735] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.231055] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.231099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.231142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.231185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.231227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.231270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.231317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.231360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.231402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.232293] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.232346] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.232391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.232835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.232902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.232945] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.232998] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.233058] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.233102] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.233145] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 582.233183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 582.234584] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.234763] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.234814] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.234931] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 582.234974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 582.235019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 582.235062] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 582.235104] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 582.235148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.235192] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 582.235234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.235278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 582.235320] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.235362] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 582.235369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.235412] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 582.236437] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.236497] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.236540] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 582.236583] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 582.236625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 582.236668] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.236713] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 582.236755] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 582.236801] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.236844] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.236886] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.236954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.237008] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.237051] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.237203] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.237241] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.238470] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 582.238780] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.238821] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.238878] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.239143] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.240021] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.240068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.240112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.240155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.240198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.240240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.240283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.240326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.240368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.240411] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.241146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.241191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.241268] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.241310] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.243120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.243164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.243209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 582.244380] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 582.244425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 582.245915] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 582.248012] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 582.249046] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.265920] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.265978] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.266149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.267033] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.267190] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.282623] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.301118] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.301229] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.301307] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.302056] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.302102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.302146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.302189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.302232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.302275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.302323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.302366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.302409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.303108] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.303159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.303204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.303249] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.303313] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.303356] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.303410] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.304070] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.304118] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.304161] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:36 BXT-2 kernel: [ 582.304199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:36 BXT-2 kernel: [ 582.305409] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.305607] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.305662] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.305780] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:36 BXT-2 kernel: [ 582.305824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:36 BXT-2 kernel: [ 582.305868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:36 BXT-2 kernel: [ 582.305912] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:36 BXT-2 kernel: [ 582.305954] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:36 BXT-2 kernel: [ 582.305998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.306041] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:36 BXT-2 kernel: [ 582.306083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.306126] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:36 BXT-2 kernel: [ 582.306169] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.306210] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:36 BXT-2 kernel: [ 582.306217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.306259] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:36 BXT-2 kernel: [ 582.306265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.306308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:36 BXT-2 kernel: [ 582.306350] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:36 BXT-2 kernel: [ 582.306393] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:36 BXT-2 kernel: [ 582.307534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:36 BXT-2 kernel: [ 582.307577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:36 BXT-2 kernel: [ 582.307623] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:36 BXT-2 kernel: [ 582.307665] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:36 BXT-2 kernel: [ 582.307710] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.307753] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.307795] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:36 BXT-2 kernel: [ 582.307863] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.307917] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.307961] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.308111] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:36 BXT-2 kernel: [ 582.308149] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:36 BXT-2 kernel: [ 582.309307] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:36 BXT-2 kernel: [ 582.309933] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.309975] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:36 BXT-2 kernel: [ 582.310032] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:36 BXT-2 kernel: [ 582.310288] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.311025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:36 BXT-2 kernel: [ 582.311071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:36 BXT-2 kernel: [ 582.311114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.311157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.311200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.311243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:36 BXT-2 kernel: [ 582.311286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:36 BXT-2 kernel: [ 582.311329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:36 BXT-2 kernel: [ 582.311371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:36 BXT-2 kernel: [ 582.311414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:36 BXT-2 kernel: [ 582.312113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:36 BXT-2 kernel: [ 582.312158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.312234] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:36 BXT-2 kernel: [ 582.312277] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.314118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.314164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:36 BXT-2 kernel: [ 582.314208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:36 BXT-2 kernel: [ 582.315396] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:36 BXT-2 kernel: [ 582.315485] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:36 BXT-2 kernel: [ 582.316874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:36 BXT-2 kernel: [ 582.318979] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:36 BXT-2 kernel: [ 582.320036] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:36 BXT-2 kernel: [ 582.336906] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:36 BXT-2 kernel: [ 582.336964] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.337135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:36 BXT-2 kernel: [ 582.338019] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:36 BXT-2 kernel: [ 582.338182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.353617] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.371674] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.371786] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.371865] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.372190] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.372234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.372277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.372320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.372363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.372406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.373182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.373225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.373268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.373311] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.373359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.373404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.373958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.374024] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.374067] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.374120] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.374181] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.374224] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.374267] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.374306] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.375699] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.375876] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.375925] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.376044] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.376087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.376131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.376175] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.376217] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.376261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.376306] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.376349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.376392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.377314] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.377356] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.377365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.377407] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.377824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.377882] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.377926] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.377968] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.378011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.378053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.378099] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.378141] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.378186] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.378229] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.378272] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.378339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.378393] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.379207] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.379363] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.379401] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.380121] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.380178] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.380218] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.380275] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.380929] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.381255] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.381299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.381342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.381385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.381428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.382040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.382083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.382126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.382169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.382212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.382260] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.382305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.382379] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.382422] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.384534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.384578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.384623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.385373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.385415] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.386655] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.386700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.388072] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.390172] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.391247] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.408102] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.408160] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.408331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.409190] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.409331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.424810] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.443301] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.443412] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.443913] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.444233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.444277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.444320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.444363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.444406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.445018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.445069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.445112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.445154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.445198] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.445245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.445290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.445335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.445400] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.446130] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.446185] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.446249] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.446296] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.446339] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.446377] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.447698] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.447880] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.447931] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.448048] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.448091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.448135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.448179] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.448221] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.448265] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.448308] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.448350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.448393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.449213] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.449255] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.449265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.449306] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.449312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.449356] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.449399] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.449967] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.450010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.450053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.450098] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.450140] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.450185] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.450229] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.450271] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.450339] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.450393] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.451195] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.451350] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.451388] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.452088] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.452395] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.452782] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.452840] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.453091] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.453409] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.453914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.453959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.454001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.454044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.454087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.454130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.454173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.454215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.454258] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.454307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.454352] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.454426] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.455182] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.456804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.456848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.456892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.458191] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.458237] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.459694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.461789] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.462830] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.479697] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.479755] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.479926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.480313] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.481027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.496397] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.514924] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.515036] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.515115] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.515900] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.515947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.515991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.516034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.516077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.516120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.516168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.516211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.516254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.516297] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.516344] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.516389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.517158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.517226] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.517269] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.517322] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.517383] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.518039] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.518085] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.518124] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.519324] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.519800] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.519854] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.519978] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.520021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.520065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.520109] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.520151] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.520196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.520238] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.520281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.520324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.520366] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.520408] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.521312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.521369] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.521375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.521419] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.521882] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.521926] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.521968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.522011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.522056] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.522098] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.522143] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.522186] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.522229] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.522295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.522349] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.522393] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.523277] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.523314] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.523982] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.524289] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.524330] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.524386] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.525063] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.525384] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.525428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.525942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.525985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.526028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.526072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.526115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.526158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.526200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.526244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.526292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.526337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.526411] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.527186] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.528794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.528839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.528883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.529912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.529955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.531045] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.531091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.532224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.534322] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.535307] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.552166] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.552223] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.552394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.553279] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.553427] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.568866] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.587361] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.587856] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.587938] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.588256] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.588300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.588343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.588385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.588428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.589044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.589094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.589137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.589180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.589223] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.589271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.589316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.589361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.589425] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.590145] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.590200] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.590264] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.590310] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.590353] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.590391] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.591504] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.592160] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.592195] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.592313] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.592356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.592401] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.592990] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.593033] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.593078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.593123] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.593166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.593209] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.593251] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.593293] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.593301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.593343] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.593349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.593392] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.594155] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.594199] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.594241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.594284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.594329] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.594371] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.594415] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.595081] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.595124] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.595191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.595246] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.595289] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.595940] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.595980] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.596269] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.596323] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.596363] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.596421] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.597173] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.597777] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.597823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.597867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.597909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.597952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.597995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.598038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.598080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.598123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.598166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.598214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.598258] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.598333] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.598376] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.600603] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.600647] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.600692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.601960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.602004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.603064] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.603109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.604222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.606321] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.607343] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.624200] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.624259] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.624429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.625375] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.625869] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.640900] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.659394] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.659550] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.659629] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.659951] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.659995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.660039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.660081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.660124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.660167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.660213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.660256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.660298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.660342] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.660389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.661305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.661353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.661418] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.661868] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.661922] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.661986] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.662032] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.662075] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.662114] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.663397] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.663600] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.663650] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.663768] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.663811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.663856] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.663900] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.663942] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.663986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.664029] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.664071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.664114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.664157] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.664199] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.664205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.664247] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.664252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.664295] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.664338] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.664381] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.664423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.665684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.665731] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.665773] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.665818] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.665862] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.665905] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.665972] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.666025] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.666069] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.666217] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.666254] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.667279] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.667886] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.667928] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.667985] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.668240] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.668961] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.669008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.669052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.669094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.669137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.669182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.669225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.669267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.669310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.669353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.669401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.670196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.670273] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.670317] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.672131] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.672175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.672221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.673401] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.673489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.674835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.676934] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.677962] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.694834] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.694891] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.695061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.695942] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.696104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.711572] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.730070] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.730183] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.730262] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.731073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.731120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.731164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.731207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.731249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.731293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.731341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.731384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.731427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.732115] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.732167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.732212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.732257] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.732322] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.732365] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.732418] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.733081] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.733129] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.733172] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.733211] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.734425] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.734624] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.734677] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.734797] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.734841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.734886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.734929] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.734971] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.735015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.735058] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.735101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.735144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.735186] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.735228] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.735235] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.735276] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.735282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.735325] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.735368] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.735411] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.736604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.736647] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.736693] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.736735] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.736780] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.736823] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.736866] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.736932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.736986] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.737029] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.737176] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.737214] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.738330] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.738949] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.738991] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.739048] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.739314] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.740033] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.740080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.740124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.740166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.740209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.740252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.740295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.740338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.740380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.740423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.741117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.741163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.741238] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.741281] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.743127] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.743171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.743215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.744437] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.744527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.745830] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.747927] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.748969] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.765845] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.765903] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.766074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.767040] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.767207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.782565] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.801057] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.801167] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.801246] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.801906] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.801953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.801997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.802039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.802082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.802125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.802173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.802216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.802259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.802302] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.802350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.802395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.803178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.803243] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.803286] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.803339] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.803400] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.803925] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.803969] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.804008] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.805193] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.805369] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.805756] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.805885] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.805928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.805973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.806017] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.806059] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.806103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.806146] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.806189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.806232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.806274] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.806316] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.806323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.806364] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.806370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.806413] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.807450] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.807800] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.807843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.807886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.807931] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.807973] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.808018] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.808061] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.808104] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.808172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.808225] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.808268] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.808415] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.809201] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.809792] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.810114] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.810155] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.810212] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.810977] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.811300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.811344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.811387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.811429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.811930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.811974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.812017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.812059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.812102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.812145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.812193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.812238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.812312] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.812355] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.814516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.814561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.814605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.815363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.815405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.816736] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.816781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.818047] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.820150] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.821220] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.838083] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.838141] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.838311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.839195] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.839336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.854780] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.872789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.872902] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.872981] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.873305] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.873349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.873393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.874070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.874113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.874157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.874206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.874249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.874292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.874335] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.874383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.874428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.875136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.875202] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.875245] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.875299] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.875360] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.875404] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.876011] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.876050] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.877219] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.877717] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.877771] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.877897] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.877940] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.877984] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.878028] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.878070] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.878114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.878157] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.878202] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.878245] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.878287] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.878328] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.878335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.878377] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.878382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.878426] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.879439] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.879785] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.879828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.879870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.879916] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.879958] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.880003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.880046] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.880089] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.880157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.880211] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.880255] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.880404] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.881251] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.881844] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.882167] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.882208] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.882265] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.882926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.883247] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.883291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.883334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.883376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.883419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.883965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.884008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.884051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.884094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.884137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.884186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.884231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.884305] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.884348] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.886386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.886431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.886928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.888022] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.888067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.889229] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.891329] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.892357] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.909218] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.909276] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.909942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.910340] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.910902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.925938] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.944430] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.944579] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.944658] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.944980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.945024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.945067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.945109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.945152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.945195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.945241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.945284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.945327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.945370] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.945417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.946327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.946373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.946791] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.946834] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.946888] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.946951] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.946996] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.947039] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 582.947077] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 582.948413] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.948613] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.948664] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.948785] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 582.948828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 582.948872] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 582.948916] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 582.948958] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 582.949002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.949045] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 582.949088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.949131] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 582.949173] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.949215] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 582.949221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.949263] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 582.949269] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.949312] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 582.949354] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 582.949397] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 582.950652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 582.950695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 582.950741] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 582.950782] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 582.950827] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.950871] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.950913] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 582.950982] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.951036] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.951079] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.951228] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 582.951266] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 582.952331] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 582.952939] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.952982] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 582.953038] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 582.953301] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.954090] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.954136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 582.954180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.954223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.954265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.954308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 582.954351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 582.954394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 582.955059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 582.955103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 582.955152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 582.955197] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.955272] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 582.955315] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.957232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.957275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 582.957320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 582.958406] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 582.958628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 582.960100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 582.962199] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 582.963249] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 582.980106] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 582.980163] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.980334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 582.981219] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 582.981366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 582.996797] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.014743] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.014855] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.014934] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.015254] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.015298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.015341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.015384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.015426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.016164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.016215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.016259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.016302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.016345] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.016392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.017033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.017079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.017143] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.017186] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.017239] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.017300] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.017345] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.017388] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 583.017426] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 583.018694] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.019323] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.019378] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.019936] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 583.019981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 583.020026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 583.020069] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 583.020111] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 583.020156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.020199] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 583.020242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.020285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 583.020327] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.020369] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 583.020377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.020418] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 583.021190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.021249] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.021292] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 583.021335] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 583.021378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 583.021420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.022024] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 583.022066] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 583.022111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.022154] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.022197] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.022265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.022319] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.022362] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.023164] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.023203] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.023877] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 583.024186] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.024227] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.024284] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.024932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.025256] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.025301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.025344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.025387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.025430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.025977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.026020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.026063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.026106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.026149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.026198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.026243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.026317] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.026360] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.028387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.028431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.028923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 583.030015] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 583.030060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 583.031224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 583.033323] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 583.034292] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.051167] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.051225] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.051397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.052310] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.052439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.067864] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.086352] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.086851] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.086936] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.087253] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.087297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.087341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.087383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.087426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.088019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.088068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.088111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.088154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.088197] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.088245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.088290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.088335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.088399] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.089041] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.089095] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.089159] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.089205] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.089247] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 583.089286] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 583.090622] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.090807] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.090855] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.090975] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 583.091018] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 583.091063] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 583.091107] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 583.091149] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 583.091193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.091236] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 583.091280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.091323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 583.091365] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.091407] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 583.092356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.092414] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 583.092764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.092821] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.092864] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 583.092907] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 583.092950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 583.092992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.093039] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 583.093081] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 583.093126] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.093169] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.093212] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.093279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.093332] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.093376] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.094340] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.094380] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.095036] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 583.095342] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.095383] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.095862] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.096123] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.096847] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.096893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.096937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.096980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.097023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.097066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.097109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.097152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.097194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.097237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.097285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.097330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.097404] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.098248] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.100004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.100048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.100093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 583.101271] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 583.101317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 583.102640] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 583.104738] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 583.105794] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.122676] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.122734] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.122906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.123286] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.123424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.139359] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.157862] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.157974] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.158053] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.158374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.158418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.159155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.159198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.159241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.159284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.159335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.159378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.159420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.160101] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.160155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.160201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.160246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.160311] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.160353] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.160407] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.161115] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.161164] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.161208] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 583.161246] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 583.162498] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.162676] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.162728] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.162843] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 583.162886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 583.162930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 583.162974] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 583.163016] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 583.163061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.163104] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 583.163147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.163190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 583.163232] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.163274] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 583.163280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.163322] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 583.163328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.163371] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.163413] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 583.164565] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 583.164609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 583.164651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.164697] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 583.164739] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 583.164784] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.164827] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.164870] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.164938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.164992] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.165035] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.165186] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.165223] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.166369] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 583.166987] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.167029] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.167086] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.167338] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.168045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.168091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.168136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.168178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.168221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.168264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.168307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.168350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.168394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.169052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.169101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.169146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.169221] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.169265] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.171161] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.171205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.171249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 583.172502] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 583.172547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 583.173842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 583.175940] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 583.176999] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.193874] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.193932] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.194103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.195033] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.195198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.210578] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.229072] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.229184] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.229263] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.230086] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.230133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.230177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.230220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.230263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.230306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.230354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.230397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.230992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.231036] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.231085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.231131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.231176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.231240] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.231283] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.231336] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.231396] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.232074] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.232118] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 583.232156] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 583.233333] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.233784] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.233840] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.233962] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 583.234005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 583.234050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 583.234093] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 583.234135] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 583.234179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.234222] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 583.234265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.234309] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 583.234351] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.234392] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 583.235292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.235349] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 583.235356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.235399] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.235884] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 583.235928] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 583.235971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 583.236013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.236059] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 583.236101] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 583.236146] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.236189] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.236232] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.236299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.236352] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.236396] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.237284] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.237321] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.237979] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 583.238287] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.238328] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.238384] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.239033] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.239358] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.239401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.239854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.239897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.239940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.239984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.240027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.240070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.240112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.240156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.240204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.240249] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.240324] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.240367] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.242567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.242611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.242656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 583.243415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.243934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.245016] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 583.245062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 583.246241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 583.248340] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 583.249369] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.266236] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.266294] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.266915] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.267312] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.267440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.282929] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.301415] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.301565] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.301644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.301969] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.302013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.302057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.302099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.302142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.302185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.302232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.302274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.302317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.302360] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.302407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.303419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.303786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.303852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.303895] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.303949] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.304009] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.304054] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.304097] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:37 BXT-2 kernel: [ 583.304135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:37 BXT-2 kernel: [ 583.305536] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.305711] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.305760] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.305876] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:37 BXT-2 kernel: [ 583.305919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:37 BXT-2 kernel: [ 583.305964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:37 BXT-2 kernel: [ 583.306007] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:37 BXT-2 kernel: [ 583.306050] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:37 BXT-2 kernel: [ 583.306094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.306137] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:37 BXT-2 kernel: [ 583.306181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.306224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:37 BXT-2 kernel: [ 583.306266] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.306308] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:37 BXT-2 kernel: [ 583.306315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.306356] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:37 BXT-2 kernel: [ 583.306362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.306405] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:37 BXT-2 kernel: [ 583.307513] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:37 BXT-2 kernel: [ 583.307557] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:37 BXT-2 kernel: [ 583.307599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:37 BXT-2 kernel: [ 583.307641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:37 BXT-2 kernel: [ 583.307687] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:37 BXT-2 kernel: [ 583.307729] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:37 BXT-2 kernel: [ 583.307774] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.307817] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.307860] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:37 BXT-2 kernel: [ 583.307927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.307981] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.308024] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.308173] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:37 BXT-2 kernel: [ 583.308210] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:37 BXT-2 kernel: [ 583.309401] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:37 BXT-2 kernel: [ 583.309733] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.309774] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:37 BXT-2 kernel: [ 583.309831] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:37 BXT-2 kernel: [ 583.310112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.310946] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:37 BXT-2 kernel: [ 583.310993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:37 BXT-2 kernel: [ 583.311036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.311079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.311122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.311165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:37 BXT-2 kernel: [ 583.311208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:37 BXT-2 kernel: [ 583.311251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:37 BXT-2 kernel: [ 583.311293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:37 BXT-2 kernel: [ 583.311336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:37 BXT-2 kernel: [ 583.311384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:37 BXT-2 kernel: [ 583.311429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.312229] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:37 BXT-2 kernel: [ 583.312272] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.314050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.314095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:37 BXT-2 kernel: [ 583.314139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:37 BXT-2 kernel: [ 583.315338] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:37 BXT-2 kernel: [ 583.315384] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:37 BXT-2 kernel: [ 583.316829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:37 BXT-2 kernel: [ 583.318927] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:37 BXT-2 kernel: [ 583.320097] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:37 BXT-2 kernel: [ 583.336953] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:37 BXT-2 kernel: [ 583.337012] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.337184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:37 BXT-2 kernel: [ 583.338116] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:37 BXT-2 kernel: [ 583.338267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.353660] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.371949] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.372061] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.372140] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.372938] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.372984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.373028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.373071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.373114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.373157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.373206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.373249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.373291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.373335] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.373382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.373427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.374211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.374277] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.374320] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.374373] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.374865] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.374913] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.374957] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:38 BXT-2 kernel: [ 583.374995] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:38 BXT-2 kernel: [ 583.376214] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.376395] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.376821] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.376948] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:38 BXT-2 kernel: [ 583.376991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:38 BXT-2 kernel: [ 583.377036] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:38 BXT-2 kernel: [ 583.377079] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:38 BXT-2 kernel: [ 583.377122] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:38 BXT-2 kernel: [ 583.377166] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.377209] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:38 BXT-2 kernel: [ 583.377252] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.377295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:38 BXT-2 kernel: [ 583.377337] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.377379] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:38 BXT-2 kernel: [ 583.377386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.377428] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:38 BXT-2 kernel: [ 583.378329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.378388] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.378431] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:38 BXT-2 kernel: [ 583.378863] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:38 BXT-2 kernel: [ 583.378906] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:38 BXT-2 kernel: [ 583.378948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.378994] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:38 BXT-2 kernel: [ 583.379036] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:38 BXT-2 kernel: [ 583.379080] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.379123] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.379166] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.379232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.379286] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.379330] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.380175] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.380214] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.380845] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:38 BXT-2 kernel: [ 583.381151] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.381192] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.381249] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.382006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.382329] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.382373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.382416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.382883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.382926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.382969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.383012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.383055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.383097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.383141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.383189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.383234] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.383309] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.383352] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.385529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.385574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.385618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:38 BXT-2 kernel: [ 583.386374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.386416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.387732] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:38 BXT-2 kernel: [ 583.387777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:38 BXT-2 kernel: [ 583.388861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:38 BXT-2 kernel: [ 583.390954] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:38 BXT-2 kernel: [ 583.391976] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.408820] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.408876] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.409046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.409494] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.409873] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.425569] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.444059] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.444170] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.444249] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.444734] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.444780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.444824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.444868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.444912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.444955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.445003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.445047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.445090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.445134] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.445182] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.445227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.445273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.445334] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.445377] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.445459] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.445520] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.445564] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.445608] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:38 BXT-2 kernel: [ 583.445647] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:38 BXT-2 kernel: [ 583.446812] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.446986] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.447039] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.447156] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:38 BXT-2 kernel: [ 583.447199] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:38 BXT-2 kernel: [ 583.447244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:38 BXT-2 kernel: [ 583.447288] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:38 BXT-2 kernel: [ 583.447330] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:38 BXT-2 kernel: [ 583.447374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.447417] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:38 BXT-2 kernel: [ 583.447491] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.447538] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:38 BXT-2 kernel: [ 583.447583] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.447627] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:38 BXT-2 kernel: [ 583.447637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.447680] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:38 BXT-2 kernel: [ 583.447689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.447733] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.448078] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:38 BXT-2 kernel: [ 583.448121] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:38 BXT-2 kernel: [ 583.448164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:38 BXT-2 kernel: [ 583.448207] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.448253] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:38 BXT-2 kernel: [ 583.448295] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:38 BXT-2 kernel: [ 583.448340] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.448384] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.448428] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.448517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.448571] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.448615] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.448758] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.448797] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.449086] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:38 BXT-2 kernel: [ 583.449140] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.449182] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.449240] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.449518] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.450156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.450201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.450244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.450287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.450330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.450372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.450415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.450488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.450533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.450578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.450627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.450819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.450895] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.450939] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.452364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.452408] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.452494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:38 BXT-2 kernel: [ 583.453489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.453673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.454398] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:38 BXT-2 kernel: [ 583.454487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:38 BXT-2 kernel: [ 583.455530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:38 BXT-2 kernel: [ 583.457621] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:38 BXT-2 kernel: [ 583.458624] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.475538] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.475596] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.475766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.476154] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.476300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.492217] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.510776] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.510894] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.510975] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.511306] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.511350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.511394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.511481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.511529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.511575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.511626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.511937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.511982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.512027] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.512079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.512127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.512173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.512240] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.512284] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.512339] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.512402] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.512742] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.512790] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:38 BXT-2 kernel: [ 583.512830] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:38 BXT-2 kernel: [ 583.513385] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.513819] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.513869] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.513992] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:38 BXT-2 kernel: [ 583.514037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:38 BXT-2 kernel: [ 583.514083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:38 BXT-2 kernel: [ 583.514128] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:38 BXT-2 kernel: [ 583.514171] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:38 BXT-2 kernel: [ 583.514215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.514258] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:38 BXT-2 kernel: [ 583.514301] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.514344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:38 BXT-2 kernel: [ 583.514386] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.514429] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:38 BXT-2 kernel: [ 583.514474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.514522] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:38 BXT-2 kernel: [ 583.514531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.514577] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.514623] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:38 BXT-2 kernel: [ 583.514669] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:38 BXT-2 kernel: [ 583.514714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:38 BXT-2 kernel: [ 583.514759] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.514807] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:38 BXT-2 kernel: [ 583.514852] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:38 BXT-2 kernel: [ 583.514896] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.515245] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.515289] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.515358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.515414] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.515493] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.515828] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.515868] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.516162] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:38 BXT-2 kernel: [ 583.516220] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.516262] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.516321] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.516803] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.517146] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.517191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.517235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.517278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.517321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.517365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.517408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.517530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.517814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.517859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.517910] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.517959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.518040] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.518085] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.519733] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.519779] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.519961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:38 BXT-2 kernel: [ 583.520919] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:38 BXT-2 kernel: [ 583.520966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:38 BXT-2 kernel: [ 583.522130] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:38 BXT-2 kernel: [ 583.524239] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:38 BXT-2 kernel: [ 583.525235] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.542121] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.542179] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.542350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.542989] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.543136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.558823] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:38 BXT-2 kernel: [ 583.576514] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:38 BXT-2 kernel: [ 583.576626] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.576705] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.577028] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.577073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.577116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.577159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.577202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.577244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.577291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.577334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.577377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.577420] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.577538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.577950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.577996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.578060] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.578104] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.578159] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.578222] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 583.578267] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.578312] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:38 BXT-2 kernel: [ 583.578351] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:38 BXT-2 kernel: [ 583.578946] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.611382] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:38 BXT-2 kernel: [ 583.611426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:38 BXT-2 kernel: [ 583.611530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:38 BXT-2 kernel: [ 583.611573] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:38 BXT-2 kernel: [ 583.611615] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:38 BXT-2 kernel: [ 583.611658] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.611701] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:38 BXT-2 kernel: [ 583.611743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.611785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:38 BXT-2 kernel: [ 583.611826] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.611868] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:38 BXT-2 kernel: [ 583.611875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.611916] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:38 BXT-2 kernel: [ 583.611921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.611963] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.612005] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:38 BXT-2 kernel: [ 583.612046] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:38 BXT-2 kernel: [ 583.612088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:38 BXT-2 kernel: [ 583.612129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:38 BXT-2 kernel: [ 583.612173] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:38 BXT-2 kernel: [ 583.612214] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:38 BXT-2 kernel: [ 583.612256] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.612297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.612339] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.612381] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 583.612425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.612550] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.612592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:38 BXT-2 kernel: [ 583.612751] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:38 BXT-2 kernel: [ 583.612788] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:38 BXT-2 kernel: [ 583.613076] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:38 BXT-2 kernel: [ 583.613130] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.613170] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 583.613225] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 583.613509] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.613825] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 583.613867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 583.613910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.613951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.613993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.614035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 583.614076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 583.614118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 583.614159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 583.614201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 583.614247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 583.614291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.614364] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:38 BXT-2 kernel: [ 583.614406] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.615943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.615985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.616029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:38 BXT-2 kernel: [ 583.616814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.616855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 583.617592] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:38 BXT-2 kernel: [ 583.617634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:38 BXT-2 kernel: [ 583.618725] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:38 BXT-2 kernel: [ 583.620820] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:38 BXT-2 kernel: [ 583.622008] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:38 BXT-2 kernel: [ 583.638938] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.638992] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:38 BXT-2 kernel: [ 583.639169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 583.639728] Console: switching to colour frame buffer device 240x67 >May 24 03:31:38 BXT-2 kernel: [ 583.859032] Console: switching to colour dummy device 80x25 >May 24 03:31:38 BXT-2 kernel: [ 583.882983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:38 BXT-2 kernel: [ 583.883043] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:38 BXT-2 kernel: [ 583.883058] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:38 BXT-2 kernel: [ 583.883081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.883126] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 583.883778] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:38 BXT-2 kernel: [ 583.884649] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:38 BXT-2 kernel: [ 583.884694] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:38 BXT-2 kernel: [ 583.884737] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:38 BXT-2 kernel: [ 583.884779] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:38 BXT-2 kernel: [ 583.885260] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:38 BXT-2 kernel: [ 583.885302] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:38 BXT-2 kernel: [ 583.890020] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:38 BXT-2 kernel: [ 583.890081] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:38 BXT-2 kernel: [ 583.890088] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890093] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890099] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890104] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890109] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890114] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890119] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:38 BXT-2 kernel: [ 583.890124] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890129] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:38 BXT-2 kernel: [ 583.890134] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:38 BXT-2 kernel: [ 583.890139] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:38 BXT-2 kernel: [ 583.890144] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:38 BXT-2 kernel: [ 583.891365] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:38 BXT-2 kernel: [ 583.891472] [drm:drm_mode_addfb2] [FB:80] >May 24 03:31:38 BXT-2 kernel: [ 584.005078] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:38 BXT-2 kernel: [ 584.005248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:38 BXT-2 kernel: [ 584.005429] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:38 BXT-2 kernel: [ 584.023972] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:38 BXT-2 kernel: [ 584.024083] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 584.024169] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 584.024495] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 584.024541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 584.024587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 584.024630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 584.024677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 584.024721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 584.024769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 584.024812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 584.024855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 584.024899] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 584.024946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 584.024991] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 584.025037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 584.025101] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 584.025143] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 584.025197] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 584.025259] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:38 BXT-2 kernel: [ 584.025311] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:38 BXT-2 kernel: [ 584.025354] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:38 BXT-2 kernel: [ 584.025393] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:38 BXT-2 kernel: [ 584.025968] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:38 BXT-2 kernel: [ 584.026082] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:38 BXT-2 kernel: [ 584.026603] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:38 BXT-2 kernel: [ 584.027174] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:38 BXT-2 kernel: [ 584.027207] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 584.027322] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:38 BXT-2 kernel: [ 584.027365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:38 BXT-2 kernel: [ 584.027410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:38 BXT-2 kernel: [ 584.027486] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:38 BXT-2 kernel: [ 584.027533] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:38 BXT-2 kernel: [ 584.027578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 584.027625] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:38 BXT-2 kernel: [ 584.027669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:38 BXT-2 kernel: [ 584.027713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:38 BXT-2 kernel: [ 584.027755] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:38 BXT-2 kernel: [ 584.027798] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:38 BXT-2 kernel: [ 584.027805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 584.027848] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:38 BXT-2 kernel: [ 584.027854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:38 BXT-2 kernel: [ 584.027898] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:38 BXT-2 kernel: [ 584.027941] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:38 BXT-2 kernel: [ 584.027984] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:38 BXT-2 kernel: [ 584.028027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:38 BXT-2 kernel: [ 584.028070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:38 BXT-2 kernel: [ 584.028115] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:38 BXT-2 kernel: [ 584.028157] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:38 BXT-2 kernel: [ 584.028201] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 584.028244] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 584.028287] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 584.028330] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:38 BXT-2 kernel: [ 584.028393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:38 BXT-2 kernel: [ 584.028475] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 584.028522] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:38 BXT-2 kernel: [ 584.029095] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:38 BXT-2 kernel: [ 584.029132] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:38 BXT-2 kernel: [ 584.029421] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:38 BXT-2 kernel: [ 584.029509] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 584.029551] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:38 BXT-2 kernel: [ 584.029608] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:38 BXT-2 kernel: [ 584.029846] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 584.030163] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:38 BXT-2 kernel: [ 584.030207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:38 BXT-2 kernel: [ 584.030250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 584.030292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 584.030335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 584.030378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:38 BXT-2 kernel: [ 584.030421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:38 BXT-2 kernel: [ 584.030503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:38 BXT-2 kernel: [ 584.030549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:38 BXT-2 kernel: [ 584.030596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:38 BXT-2 kernel: [ 584.030645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:38 BXT-2 kernel: [ 584.030692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 584.030766] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:38 BXT-2 kernel: [ 584.030809] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:38 BXT-2 kernel: [ 584.032247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 584.032290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 584.032334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:38 BXT-2 kernel: [ 584.033112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:38 BXT-2 kernel: [ 584.033155] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:38 BXT-2 kernel: [ 584.033884] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:38 BXT-2 kernel: [ 584.033927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:38 BXT-2 kernel: [ 584.034965] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:38 BXT-2 kernel: [ 584.037045] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:38 BXT-2 kernel: [ 584.038086] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:38 BXT-2 kernel: [ 584.054951] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:38 BXT-2 kernel: [ 584.055004] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:38 BXT-2 kernel: [ 584.055173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:42 BXT-2 kernel: [ 587.688517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:42 BXT-2 kernel: [ 587.688647] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:42 BXT-2 kernel: [ 587.706704] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:42 BXT-2 kernel: [ 587.706818] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:42 BXT-2 kernel: [ 587.706910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:42 BXT-2 kernel: [ 587.707231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:42 BXT-2 kernel: [ 587.707275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:42 BXT-2 kernel: [ 587.707319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:42 BXT-2 kernel: [ 587.707362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:42 BXT-2 kernel: [ 587.707405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:42 BXT-2 kernel: [ 587.707510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:42 BXT-2 kernel: [ 587.707558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:42 BXT-2 kernel: [ 587.707601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:42 BXT-2 kernel: [ 587.707644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:42 BXT-2 kernel: [ 587.707687] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:42 BXT-2 kernel: [ 587.707735] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:42 BXT-2 kernel: [ 587.707780] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:42 BXT-2 kernel: [ 587.707825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:42 BXT-2 kernel: [ 587.707887] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:42 BXT-2 kernel: [ 587.707930] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:42 BXT-2 kernel: [ 587.707984] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:42 BXT-2 kernel: [ 587.708046] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:42 BXT-2 kernel: [ 587.708098] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:42 BXT-2 kernel: [ 587.708142] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:42 BXT-2 kernel: [ 587.708181] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:42 BXT-2 kernel: [ 587.708763] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:42 BXT-2 kernel: [ 587.710254] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:42 BXT-2 kernel: [ 587.710316] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:42 BXT-2 kernel: [ 587.770815] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:42 BXT-2 kernel: [ 587.771374] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:42 BXT-2 kernel: [ 587.771936] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:42 BXT-2 kernel: [ 587.772588] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:42 BXT-2 kernel: [ 587.772641] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:42 BXT-2 kernel: [ 587.772763] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:42 BXT-2 kernel: [ 587.772807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:42 BXT-2 kernel: [ 587.772853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:42 BXT-2 kernel: [ 587.772897] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:42 BXT-2 kernel: [ 587.772939] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:42 BXT-2 kernel: [ 587.772984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:42 BXT-2 kernel: [ 587.773027] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:31:42 BXT-2 kernel: [ 587.773071] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:31:42 BXT-2 kernel: [ 587.773114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:42 BXT-2 kernel: [ 587.773157] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:42 BXT-2 kernel: [ 587.773199] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:42 BXT-2 kernel: [ 587.773207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:42 BXT-2 kernel: [ 587.773248] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:42 BXT-2 kernel: [ 587.773254] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:42 BXT-2 kernel: [ 587.773298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:42 BXT-2 kernel: [ 587.773342] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:42 BXT-2 kernel: [ 587.773385] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:42 BXT-2 kernel: [ 587.773428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:42 BXT-2 kernel: [ 587.773506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:42 BXT-2 kernel: [ 587.773552] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:42 BXT-2 kernel: [ 587.773595] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:42 BXT-2 kernel: [ 587.773638] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:31:42 BXT-2 kernel: [ 587.773682] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:31:42 BXT-2 kernel: [ 587.773725] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:31:42 BXT-2 kernel: [ 587.773768] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:31:42 BXT-2 kernel: [ 587.773830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:42 BXT-2 kernel: [ 587.773883] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:31:42 BXT-2 kernel: [ 587.773926] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:31:42 BXT-2 kernel: [ 587.774520] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:42 BXT-2 kernel: [ 587.774561] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:42 BXT-2 kernel: [ 587.774860] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:42 BXT-2 kernel: [ 587.774914] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:42 BXT-2 kernel: [ 587.774954] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:42 BXT-2 kernel: [ 587.775011] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:42 BXT-2 kernel: [ 587.775329] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:42 BXT-2 kernel: [ 587.775675] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:42 BXT-2 kernel: [ 587.775721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:42 BXT-2 kernel: [ 587.775764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:42 BXT-2 kernel: [ 587.775808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:42 BXT-2 kernel: [ 587.775851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:42 BXT-2 kernel: [ 587.775894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:42 BXT-2 kernel: [ 587.775938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:42 BXT-2 kernel: [ 587.775981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:42 BXT-2 kernel: [ 587.776024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:42 BXT-2 kernel: [ 587.776068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:42 BXT-2 kernel: [ 587.776116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:42 BXT-2 kernel: [ 587.776161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:42 BXT-2 kernel: [ 587.776236] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:31:42 BXT-2 kernel: [ 587.776281] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:42 BXT-2 kernel: [ 587.778838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:42 BXT-2 kernel: [ 587.778885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:42 BXT-2 kernel: [ 587.778930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:42 BXT-2 kernel: [ 587.779793] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:42 BXT-2 kernel: [ 587.779840] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:42 BXT-2 kernel: [ 587.781075] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:42 BXT-2 kernel: [ 587.782525] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:42 BXT-2 kernel: [ 587.783608] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:31:42 BXT-2 kernel: [ 587.800534] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:42 BXT-2 kernel: [ 587.800592] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:42 BXT-2 kernel: [ 587.800763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.434010] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:46 BXT-2 kernel: [ 591.434149] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:31:46 BXT-2 kernel: [ 591.450618] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:31:46 BXT-2 kernel: [ 591.450732] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.450823] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:46 BXT-2 kernel: [ 591.451146] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:46 BXT-2 kernel: [ 591.451190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:46 BXT-2 kernel: [ 591.451233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:46 BXT-2 kernel: [ 591.451276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:46 BXT-2 kernel: [ 591.451319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:46 BXT-2 kernel: [ 591.451362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:46 BXT-2 kernel: [ 591.451408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:46 BXT-2 kernel: [ 591.451491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:46 BXT-2 kernel: [ 591.451535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:46 BXT-2 kernel: [ 591.451581] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:46 BXT-2 kernel: [ 591.451630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:46 BXT-2 kernel: [ 591.451677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:46 BXT-2 kernel: [ 591.451722] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.451782] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:46 BXT-2 kernel: [ 591.451824] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:46 BXT-2 kernel: [ 591.451877] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:46 BXT-2 kernel: [ 591.451939] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:31:46 BXT-2 kernel: [ 591.451984] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:46 BXT-2 kernel: [ 591.452028] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:46 BXT-2 kernel: [ 591.452067] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:46 BXT-2 kernel: [ 591.452694] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:46 BXT-2 kernel: [ 591.453595] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:46 BXT-2 kernel: [ 591.453658] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:46 BXT-2 kernel: [ 591.514162] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:46 BXT-2 kernel: [ 591.514778] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:46 BXT-2 kernel: [ 591.515207] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:46 BXT-2 kernel: [ 591.515961] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:46 BXT-2 kernel: [ 591.516010] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:46 BXT-2 kernel: [ 591.516125] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:46 BXT-2 kernel: [ 591.516169] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:46 BXT-2 kernel: [ 591.516214] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:46 BXT-2 kernel: [ 591.516257] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:46 BXT-2 kernel: [ 591.516299] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:46 BXT-2 kernel: [ 591.516343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:46 BXT-2 kernel: [ 591.516386] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:31:46 BXT-2 kernel: [ 591.516429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:31:46 BXT-2 kernel: [ 591.516913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:46 BXT-2 kernel: [ 591.516955] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:46 BXT-2 kernel: [ 591.516997] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:46 BXT-2 kernel: [ 591.517006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:46 BXT-2 kernel: [ 591.517048] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:46 BXT-2 kernel: [ 591.517054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:46 BXT-2 kernel: [ 591.517097] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:46 BXT-2 kernel: [ 591.517139] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:46 BXT-2 kernel: [ 591.517182] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:46 BXT-2 kernel: [ 591.517225] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:46 BXT-2 kernel: [ 591.517267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:46 BXT-2 kernel: [ 591.517312] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:46 BXT-2 kernel: [ 591.517354] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:46 BXT-2 kernel: [ 591.517398] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:31:46 BXT-2 kernel: [ 591.517977] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:31:46 BXT-2 kernel: [ 591.518020] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:31:46 BXT-2 kernel: [ 591.518089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:46 BXT-2 kernel: [ 591.518143] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.518186] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:31:46 BXT-2 kernel: [ 591.519293] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:46 BXT-2 kernel: [ 591.519348] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:46 BXT-2 kernel: [ 591.519866] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:46 BXT-2 kernel: [ 591.520278] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:46 BXT-2 kernel: [ 591.520320] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:46 BXT-2 kernel: [ 591.520379] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:46 BXT-2 kernel: [ 591.521092] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:46 BXT-2 kernel: [ 591.521425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:46 BXT-2 kernel: [ 591.521805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:46 BXT-2 kernel: [ 591.521850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:46 BXT-2 kernel: [ 591.521893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:46 BXT-2 kernel: [ 591.521936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:46 BXT-2 kernel: [ 591.521979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:46 BXT-2 kernel: [ 591.522023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:46 BXT-2 kernel: [ 591.522067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:46 BXT-2 kernel: [ 591.522112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:46 BXT-2 kernel: [ 591.522159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:46 BXT-2 kernel: [ 591.522225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:46 BXT-2 kernel: [ 591.522275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.522358] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:31:46 BXT-2 kernel: [ 591.522401] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.524975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:46 BXT-2 kernel: [ 591.525022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:46 BXT-2 kernel: [ 591.525067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:46 BXT-2 kernel: [ 591.526181] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:46 BXT-2 kernel: [ 591.526228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:46 BXT-2 kernel: [ 591.527781] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:46 BXT-2 kernel: [ 591.529881] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:46 BXT-2 kernel: [ 591.530876] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:31:46 BXT-2 kernel: [ 591.547771] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:46 BXT-2 kernel: [ 591.547832] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:46 BXT-2 kernel: [ 591.548004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:46 BXT-2 kernel: [ 591.597208] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x10001918, pins 0x00000040 >May 24 03:31:46 BXT-2 kernel: [ 591.597257] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short >May 24 03:31:46 BXT-2 kernel: [ 591.597350] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short >May 24 03:31:46 BXT-2 kernel: [ 591.598130] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:46 BXT-2 kernel: [ 591.599925] [drm:intel_dp_check_link_status [i915]] DDI C: channel EQ not ok, retraining >May 24 03:31:46 BXT-2 kernel: [ 591.601156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:46 BXT-2 kernel: [ 591.601200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:46 BXT-2 kernel: [ 591.601244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:46 BXT-2 kernel: [ 591.602150] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:46 BXT-2 kernel: [ 591.602195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:46 BXT-2 kernel: [ 591.603380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:49 BXT-2 kernel: [ 591.605722] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:49 BXT-2 kernel: [ 595.181285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:49 BXT-2 kernel: [ 595.181418] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:31:49 BXT-2 kernel: [ 595.197937] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:31:49 BXT-2 kernel: [ 595.198050] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:49 BXT-2 kernel: [ 595.198130] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:49 BXT-2 kernel: [ 595.198494] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:49 BXT-2 kernel: [ 595.198539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:49 BXT-2 kernel: [ 595.198582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:49 BXT-2 kernel: [ 595.198625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:49 BXT-2 kernel: [ 595.198668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:49 BXT-2 kernel: [ 595.198711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:49 BXT-2 kernel: [ 595.198758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:49 BXT-2 kernel: [ 595.198801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:49 BXT-2 kernel: [ 595.198843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:49 BXT-2 kernel: [ 595.198887] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:49 BXT-2 kernel: [ 595.198934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:49 BXT-2 kernel: [ 595.198979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:49 BXT-2 kernel: [ 595.199024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:49 BXT-2 kernel: [ 595.199085] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:49 BXT-2 kernel: [ 595.199127] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:49 BXT-2 kernel: [ 595.199180] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:49 BXT-2 kernel: [ 595.199242] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:31:49 BXT-2 kernel: [ 595.199285] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:49 BXT-2 kernel: [ 595.199328] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:49 BXT-2 kernel: [ 595.199366] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:49 BXT-2 kernel: [ 595.199931] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:49 BXT-2 kernel: [ 595.236431] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:49 BXT-2 kernel: [ 595.236520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:49 BXT-2 kernel: [ 595.236564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:49 BXT-2 kernel: [ 595.236607] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:49 BXT-2 kernel: [ 595.236648] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:49 BXT-2 kernel: [ 595.236692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:49 BXT-2 kernel: [ 595.236734] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:49 BXT-2 kernel: [ 595.236776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:49 BXT-2 kernel: [ 595.236818] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:49 BXT-2 kernel: [ 595.236859] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:49 BXT-2 kernel: [ 595.236900] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:49 BXT-2 kernel: [ 595.236908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:49 BXT-2 kernel: [ 595.236948] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:49 BXT-2 kernel: [ 595.236953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:49 BXT-2 kernel: [ 595.236995] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:49 BXT-2 kernel: [ 595.237037] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:49 BXT-2 kernel: [ 595.237079] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:49 BXT-2 kernel: [ 595.237120] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:49 BXT-2 kernel: [ 595.237161] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:49 BXT-2 kernel: [ 595.237205] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:49 BXT-2 kernel: [ 595.237246] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:49 BXT-2 kernel: [ 595.237288] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:49 BXT-2 kernel: [ 595.237330] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:49 BXT-2 kernel: [ 595.237371] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:49 BXT-2 kernel: [ 595.237412] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:49 BXT-2 kernel: [ 595.237601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:49 BXT-2 kernel: [ 595.237652] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:49 BXT-2 kernel: [ 595.237695] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:49 BXT-2 kernel: [ 595.237875] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:49 BXT-2 kernel: [ 595.237911] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:49 BXT-2 kernel: [ 595.238199] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:49 BXT-2 kernel: [ 595.238251] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:49 BXT-2 kernel: [ 595.238290] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:49 BXT-2 kernel: [ 595.238344] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:49 BXT-2 kernel: [ 595.238640] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:49 BXT-2 kernel: [ 595.238956] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:49 BXT-2 kernel: [ 595.238999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:49 BXT-2 kernel: [ 595.239041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:49 BXT-2 kernel: [ 595.239083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:49 BXT-2 kernel: [ 595.239124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:49 BXT-2 kernel: [ 595.239166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:49 BXT-2 kernel: [ 595.239207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:49 BXT-2 kernel: [ 595.239249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:49 BXT-2 kernel: [ 595.239290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:49 BXT-2 kernel: [ 595.239332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:49 BXT-2 kernel: [ 595.239377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:49 BXT-2 kernel: [ 595.239421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:49 BXT-2 kernel: [ 595.239535] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:49 BXT-2 kernel: [ 595.239577] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:49 BXT-2 kernel: [ 595.241067] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:49 BXT-2 kernel: [ 595.241108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:49 BXT-2 kernel: [ 595.241152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:49 BXT-2 kernel: [ 595.241931] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:49 BXT-2 kernel: [ 595.241972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:49 BXT-2 kernel: [ 595.242707] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:49 BXT-2 kernel: [ 595.242749] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:49 BXT-2 kernel: [ 595.243799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:49 BXT-2 kernel: [ 595.245893] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:49 BXT-2 kernel: [ 595.247099] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:49 BXT-2 kernel: [ 595.264001] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:49 BXT-2 kernel: [ 595.264055] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:49 BXT-2 kernel: [ 595.264232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:49 BXT-2 kernel: [ 595.264657] Console: switching to colour frame buffer device 240x67 >May 24 03:31:50 BXT-2 kernel: [ 595.487168] Console: switching to colour dummy device 80x25 >May 24 03:31:50 BXT-2 kernel: [ 595.524316] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:50 BXT-2 kernel: [ 595.524643] [drm:drm_mode_addfb2] [FB:80] >May 24 03:31:50 BXT-2 kernel: [ 595.524895] [drm:drm_mode_addfb2] [FB:81] >May 24 03:31:50 BXT-2 kernel: [ 595.531117] [drm:drm_mode_addfb2] [FB:82] >May 24 03:31:50 BXT-2 kernel: [ 595.568482] [drm:drm_mode_addfb2] [FB:83] >May 24 03:31:50 BXT-2 kernel: [ 595.584503] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:50 BXT-2 kernel: [ 595.584786] [drm:drm_mode_addfb2] [FB:80] >May 24 03:31:50 BXT-2 kernel: [ 595.585168] [drm:drm_mode_addfb2] [FB:81] >May 24 03:31:50 BXT-2 kernel: [ 595.591936] [drm:drm_mode_addfb2] [FB:82] >May 24 03:31:50 BXT-2 kernel: [ 595.629160] [drm:drm_mode_addfb2] [FB:83] >May 24 03:31:50 BXT-2 kernel: [ 595.629177] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 595.629340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.629841] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:50 BXT-2 kernel: [ 595.632193] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:50 BXT-2 kernel: [ 595.632306] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.632395] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.632759] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.632804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:50 BXT-2 kernel: [ 595.632847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 595.632890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 595.632933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 595.632975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:50 BXT-2 kernel: [ 595.633022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 595.633064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 595.633107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 595.633152] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 595.633199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:50 BXT-2 kernel: [ 595.633244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:50 BXT-2 kernel: [ 595.633288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.633348] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:50 BXT-2 kernel: [ 595.633390] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 595.633468] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 595.633532] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 595.633585] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:50 BXT-2 kernel: [ 595.633629] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:50 BXT-2 kernel: [ 595.633669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:50 BXT-2 kernel: [ 595.634217] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:50 BXT-2 kernel: [ 595.634816] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:50 BXT-2 kernel: [ 595.635519] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:50 BXT-2 kernel: [ 595.651908] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:50 BXT-2 kernel: [ 595.657159] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 595.657214] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 595.657342] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:50 BXT-2 kernel: [ 595.657386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:50 BXT-2 kernel: [ 595.657432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:50 BXT-2 kernel: [ 595.657506] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:50 BXT-2 kernel: [ 595.657551] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:50 BXT-2 kernel: [ 595.657597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:50 BXT-2 kernel: [ 595.657642] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:50 BXT-2 kernel: [ 595.657686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:50 BXT-2 kernel: [ 595.657731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:50 BXT-2 kernel: [ 595.657776] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:50 BXT-2 kernel: [ 595.657818] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:50 BXT-2 kernel: [ 595.657826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:50 BXT-2 kernel: [ 595.657868] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:50 BXT-2 kernel: [ 595.657874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:50 BXT-2 kernel: [ 595.657918] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:50 BXT-2 kernel: [ 595.657962] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:50 BXT-2 kernel: [ 595.658006] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:50 BXT-2 kernel: [ 595.658050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:50 BXT-2 kernel: [ 595.658093] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:50 BXT-2 kernel: [ 595.658139] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:50 BXT-2 kernel: [ 595.658181] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:50 BXT-2 kernel: [ 595.658225] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 595.658268] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 595.658311] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 595.658354] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 595.658418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.658499] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.658543] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:50 BXT-2 kernel: [ 595.659132] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:50 BXT-2 kernel: [ 595.659170] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:50 BXT-2 kernel: [ 595.659485] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:50 BXT-2 kernel: [ 595.659542] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 595.659584] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 595.659642] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:50 BXT-2 kernel: [ 595.659938] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.660262] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.660306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:50 BXT-2 kernel: [ 595.660349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 595.660391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 595.660484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 595.660530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:50 BXT-2 kernel: [ 595.660574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 595.660618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 595.660662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 595.660706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:50 BXT-2 kernel: [ 595.660753] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:50 BXT-2 kernel: [ 595.660799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.660875] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:50 BXT-2 kernel: [ 595.660918] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.662356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:50 BXT-2 kernel: [ 595.662399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:50 BXT-2 kernel: [ 595.662481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:50 BXT-2 kernel: [ 595.663243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:50 BXT-2 kernel: [ 595.663285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:50 BXT-2 kernel: [ 595.664015] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:50 BXT-2 kernel: [ 595.664058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:50 BXT-2 kernel: [ 595.665095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:50 BXT-2 kernel: [ 595.667175] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:50 BXT-2 kernel: [ 595.668218] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:50 BXT-2 kernel: [ 595.685113] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 595.685166] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 595.685334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.718992] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 595.719165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.719335] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:50 BXT-2 kernel: [ 595.736836] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:50 BXT-2 kernel: [ 595.736949] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.737037] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.737354] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 595.737398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:50 BXT-2 kernel: [ 595.737488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 595.737540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 595.737588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 595.737634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:50 BXT-2 kernel: [ 595.737682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 595.737729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 595.737772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 595.737816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 595.737864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:50 BXT-2 kernel: [ 595.737909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:50 BXT-2 kernel: [ 595.737954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 595.738015] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:50 BXT-2 kernel: [ 595.738058] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 595.738112] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 595.738174] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 595.738225] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:50 BXT-2 kernel: [ 595.738268] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:50 BXT-2 kernel: [ 595.738307] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:50 BXT-2 kernel: [ 595.738898] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:50 BXT-2 kernel: [ 595.739490] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:50 BXT-2 kernel: [ 595.740131] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:50 BXT-2 kernel: [ 595.758881] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:50 BXT-2 kernel: [ 595.770995] [drm:drm_mode_addfb2] [FB:84] >May 24 03:31:50 BXT-2 kernel: [ 595.782970] [drm:drm_mode_addfb2] [FB:85] >May 24 03:31:50 BXT-2 kernel: [ 595.794918] [drm:drm_mode_addfb2] [FB:86] >May 24 03:31:50 BXT-2 kernel: [ 596.015130] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.015195] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.015323] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:50 BXT-2 kernel: [ 596.015368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:50 BXT-2 kernel: [ 596.015412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:50 BXT-2 kernel: [ 596.015494] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:50 BXT-2 kernel: [ 596.015541] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:50 BXT-2 kernel: [ 596.015589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.015635] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:50 BXT-2 kernel: [ 596.015680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.015990] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:50 BXT-2 kernel: [ 596.016033] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.016076] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:50 BXT-2 kernel: [ 596.016085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:50 BXT-2 kernel: [ 596.016127] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:50 BXT-2 kernel: [ 596.016134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:50 BXT-2 kernel: [ 596.016177] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:50 BXT-2 kernel: [ 596.016221] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:50 BXT-2 kernel: [ 596.016264] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:50 BXT-2 kernel: [ 596.016307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:50 BXT-2 kernel: [ 596.016350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.016395] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:50 BXT-2 kernel: [ 596.016467] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:50 BXT-2 kernel: [ 596.016514] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.016559] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.016606] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.016651] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.016989] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.017045] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.017089] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:50 BXT-2 kernel: [ 596.017734] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:50 BXT-2 kernel: [ 596.017773] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:50 BXT-2 kernel: [ 596.018061] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:50 BXT-2 kernel: [ 596.018115] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 596.018155] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 596.018211] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:50 BXT-2 kernel: [ 596.018486] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.018806] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.018853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:50 BXT-2 kernel: [ 596.018897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 596.018941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 596.018984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 596.019027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:50 BXT-2 kernel: [ 596.019071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 596.019113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 596.019157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 596.019201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:50 BXT-2 kernel: [ 596.019248] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:50 BXT-2 kernel: [ 596.019293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.019367] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:50 BXT-2 kernel: [ 596.019411] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.021122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.021167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.021211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:50 BXT-2 kernel: [ 596.022029] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.022071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.022808] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:50 BXT-2 kernel: [ 596.022852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:50 BXT-2 kernel: [ 596.023895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:50 BXT-2 kernel: [ 596.025978] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:50 BXT-2 kernel: [ 596.027002] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:50 BXT-2 kernel: [ 596.043870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.043924] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.044093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.077171] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.077228] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.127152] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.127202] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.177151] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.177202] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.227229] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.227381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.227628] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:50 BXT-2 kernel: [ 596.245792] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:50 BXT-2 kernel: [ 596.245918] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.246007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.246332] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.246376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:50 BXT-2 kernel: [ 596.246419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 596.246519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 596.246562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 596.246607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:50 BXT-2 kernel: [ 596.246656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 596.246698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 596.246741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 596.246784] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.246832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:50 BXT-2 kernel: [ 596.246879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:50 BXT-2 kernel: [ 596.246923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.246984] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:50 BXT-2 kernel: [ 596.247028] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 596.247082] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 596.247143] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.247195] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:50 BXT-2 kernel: [ 596.247238] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:50 BXT-2 kernel: [ 596.247277] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:50 BXT-2 kernel: [ 596.248467] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:50 BXT-2 kernel: [ 596.249033] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:50 BXT-2 kernel: [ 596.250240] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:50 BXT-2 kernel: [ 596.256480] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.256539] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.256663] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:50 BXT-2 kernel: [ 596.256706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:50 BXT-2 kernel: [ 596.256751] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:50 BXT-2 kernel: [ 596.256794] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:50 BXT-2 kernel: [ 596.256836] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:50 BXT-2 kernel: [ 596.256880] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.256923] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:50 BXT-2 kernel: [ 596.256965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.257008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:50 BXT-2 kernel: [ 596.257050] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.257092] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:50 BXT-2 kernel: [ 596.257099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:50 BXT-2 kernel: [ 596.257140] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:50 BXT-2 kernel: [ 596.257146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:50 BXT-2 kernel: [ 596.257189] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:50 BXT-2 kernel: [ 596.257231] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:50 BXT-2 kernel: [ 596.257274] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:50 BXT-2 kernel: [ 596.257316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:50 BXT-2 kernel: [ 596.257358] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:50 BXT-2 kernel: [ 596.257403] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:50 BXT-2 kernel: [ 596.257494] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:50 BXT-2 kernel: [ 596.257539] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.257584] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.257628] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.257672] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:50 BXT-2 kernel: [ 596.257734] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.257788] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.257831] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:50 BXT-2 kernel: [ 596.263588] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:50 BXT-2 kernel: [ 596.263629] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:50 BXT-2 kernel: [ 596.263919] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:50 BXT-2 kernel: [ 596.263975] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 596.264016] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:50 BXT-2 kernel: [ 596.264073] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:50 BXT-2 kernel: [ 596.264329] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.264980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:50 BXT-2 kernel: [ 596.265027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:50 BXT-2 kernel: [ 596.265072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 596.265115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 596.265159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 596.265203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:50 BXT-2 kernel: [ 596.265246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:50 BXT-2 kernel: [ 596.265290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:50 BXT-2 kernel: [ 596.265333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:50 BXT-2 kernel: [ 596.265377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:50 BXT-2 kernel: [ 596.265425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:50 BXT-2 kernel: [ 596.265939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.266016] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:50 BXT-2 kernel: [ 596.266060] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:50 BXT-2 kernel: [ 596.267765] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.267810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.267855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:50 BXT-2 kernel: [ 596.268864] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.268908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:50 BXT-2 kernel: [ 596.269715] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:50 BXT-2 kernel: [ 596.269760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:50 BXT-2 kernel: [ 596.270931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:50 BXT-2 kernel: [ 596.272541] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:50 BXT-2 kernel: [ 596.273603] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:50 BXT-2 kernel: [ 596.290516] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:50 BXT-2 kernel: [ 596.290572] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:50 BXT-2 kernel: [ 596.290742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.368847] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:51 BXT-2 kernel: [ 596.873933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:51 BXT-2 kernel: [ 596.874063] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:51 BXT-2 kernel: [ 596.891829] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:51 BXT-2 kernel: [ 596.891941] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.892030] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:51 BXT-2 kernel: [ 596.892351] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:51 BXT-2 kernel: [ 596.892395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:51 BXT-2 kernel: [ 596.892488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:51 BXT-2 kernel: [ 596.892532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:51 BXT-2 kernel: [ 596.892575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:51 BXT-2 kernel: [ 596.892618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:51 BXT-2 kernel: [ 596.892666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:51 BXT-2 kernel: [ 596.892709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:51 BXT-2 kernel: [ 596.892752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:51 BXT-2 kernel: [ 596.892796] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:51 BXT-2 kernel: [ 596.892844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:51 BXT-2 kernel: [ 596.892890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:51 BXT-2 kernel: [ 596.892935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.892997] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:51 BXT-2 kernel: [ 596.893040] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:51 BXT-2 kernel: [ 596.893095] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:51 BXT-2 kernel: [ 596.893159] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:51 BXT-2 kernel: [ 596.893212] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:51 BXT-2 kernel: [ 596.893256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:51 BXT-2 kernel: [ 596.893298] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:51 BXT-2 kernel: [ 596.893880] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:51 BXT-2 kernel: [ 596.946846] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:51 BXT-2 kernel: [ 596.946893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:51 BXT-2 kernel: [ 596.946938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:51 BXT-2 kernel: [ 596.946981] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:51 BXT-2 kernel: [ 596.947023] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:51 BXT-2 kernel: [ 596.947068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:51 BXT-2 kernel: [ 596.947129] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:51 BXT-2 kernel: [ 596.947171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:51 BXT-2 kernel: [ 596.947215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:51 BXT-2 kernel: [ 596.947257] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:51 BXT-2 kernel: [ 596.947299] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:51 BXT-2 kernel: [ 596.947309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:51 BXT-2 kernel: [ 596.947351] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:51 BXT-2 kernel: [ 596.947357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:51 BXT-2 kernel: [ 596.947400] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:51 BXT-2 kernel: [ 596.947528] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:51 BXT-2 kernel: [ 596.947773] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:51 BXT-2 kernel: [ 596.947815] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:51 BXT-2 kernel: [ 596.947857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:51 BXT-2 kernel: [ 596.947902] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:51 BXT-2 kernel: [ 596.947944] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:51 BXT-2 kernel: [ 596.947987] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:51 BXT-2 kernel: [ 596.948029] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:51 BXT-2 kernel: [ 596.948072] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:51 BXT-2 kernel: [ 596.948114] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:51 BXT-2 kernel: [ 596.948162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:51 BXT-2 kernel: [ 596.948214] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.948257] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:51 BXT-2 kernel: [ 596.948411] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:51 BXT-2 kernel: [ 596.948503] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:51 BXT-2 kernel: [ 596.948560] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:51 BXT-2 kernel: [ 596.949136] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:51 BXT-2 kernel: [ 596.949175] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:51 BXT-2 kernel: [ 596.949347] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:51 BXT-2 kernel: [ 596.951866] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:51 BXT-2 kernel: [ 596.952213] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:51 BXT-2 kernel: [ 596.952257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:51 BXT-2 kernel: [ 596.952301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:51 BXT-2 kernel: [ 596.952343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:51 BXT-2 kernel: [ 596.952386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:51 BXT-2 kernel: [ 596.952429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:51 BXT-2 kernel: [ 596.952544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:51 BXT-2 kernel: [ 596.952587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:51 BXT-2 kernel: [ 596.952632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:51 BXT-2 kernel: [ 596.952676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:51 BXT-2 kernel: [ 596.952724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:51 BXT-2 kernel: [ 596.952769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.952882] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:51 BXT-2 kernel: [ 596.952956] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.956209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:51 BXT-2 kernel: [ 596.956255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:51 BXT-2 kernel: [ 596.956299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:51 BXT-2 kernel: [ 596.957136] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:51 BXT-2 kernel: [ 596.957181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:51 BXT-2 kernel: [ 596.958247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:51 BXT-2 kernel: [ 596.960347] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:51 BXT-2 kernel: [ 596.961479] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:51 BXT-2 kernel: [ 596.978366] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:51 BXT-2 kernel: [ 596.978422] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:51 BXT-2 kernel: [ 596.978657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:51 BXT-2 kernel: [ 596.995172] Console: switching to colour frame buffer device 240x67 >May 24 03:31:51 BXT-2 kernel: [ 597.243130] Console: switching to colour dummy device 80x25 >May 24 03:31:51 BXT-2 kernel: [ 597.257462] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:51 BXT-2 kernel: [ 597.257524] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:51 BXT-2 kernel: [ 597.257539] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:51 BXT-2 kernel: [ 597.257562] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:51 BXT-2 kernel: [ 597.257607] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:51 BXT-2 kernel: [ 597.258138] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:51 BXT-2 kernel: [ 597.259289] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:51 BXT-2 kernel: [ 597.259336] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:51 BXT-2 kernel: [ 597.259378] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:51 BXT-2 kernel: [ 597.259421] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:51 BXT-2 kernel: [ 597.260105] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:51 BXT-2 kernel: [ 597.260149] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:51 BXT-2 kernel: [ 597.264872] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:51 BXT-2 kernel: [ 597.264934] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:51 BXT-2 kernel: [ 597.264941] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264946] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264951] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264956] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264961] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264967] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264972] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:51 BXT-2 kernel: [ 597.264977] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264982] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.264987] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:51 BXT-2 kernel: [ 597.264992] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:51 BXT-2 kernel: [ 597.264997] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:51 BXT-2 kernel: [ 597.271935] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:51 BXT-2 kernel: [ 597.271997] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:51 BXT-2 kernel: [ 597.272012] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:51 BXT-2 kernel: [ 597.272369] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:51 BXT-2 kernel: [ 597.272415] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:51 BXT-2 kernel: [ 597.273002] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:51 BXT-2 kernel: [ 597.273910] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:51 BXT-2 kernel: [ 597.273956] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:51 BXT-2 kernel: [ 597.273998] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:51 BXT-2 kernel: [ 597.274041] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:51 BXT-2 kernel: [ 597.274576] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:51 BXT-2 kernel: [ 597.274620] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:51 BXT-2 kernel: [ 597.279392] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:51 BXT-2 kernel: [ 597.279475] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:51 BXT-2 kernel: [ 597.279482] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279488] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279493] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279498] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279503] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279508] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279513] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:51 BXT-2 kernel: [ 597.279518] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279523] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:51 BXT-2 kernel: [ 597.279528] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:51 BXT-2 kernel: [ 597.279533] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:51 BXT-2 kernel: [ 597.279538] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:51 BXT-2 kernel: [ 597.280216] [drm:display_crc_ctl_write [i915]] unknown pipe D >May 24 03:31:51 BXT-2 kernel: [ 597.311824] Console: switching to colour frame buffer device 240x67 >May 24 03:31:52 BXT-2 kernel: [ 597.551631] Console: switching to colour dummy device 80x25 >May 24 03:31:52 BXT-2 kernel: [ 597.576966] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.577026] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.577041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:52 BXT-2 kernel: [ 597.577063] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.577108] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.577772] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:52 BXT-2 kernel: [ 597.578661] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:52 BXT-2 kernel: [ 597.578707] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:52 BXT-2 kernel: [ 597.578750] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.578792] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.579276] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:52 BXT-2 kernel: [ 597.579319] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:52 BXT-2 kernel: [ 597.584396] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:52 BXT-2 kernel: [ 597.584476] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:52 BXT-2 kernel: [ 597.584483] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584488] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584493] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584498] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584503] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584509] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584514] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.584519] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584524] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.584529] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.584534] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.584539] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:52 BXT-2 kernel: [ 597.591681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.591742] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.591757] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:52 BXT-2 kernel: [ 597.592090] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.592136] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.592763] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:52 BXT-2 kernel: [ 597.593661] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:52 BXT-2 kernel: [ 597.593707] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:52 BXT-2 kernel: [ 597.593749] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.593791] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.594277] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:52 BXT-2 kernel: [ 597.594319] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:52 BXT-2 kernel: [ 597.599364] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:52 BXT-2 kernel: [ 597.599539] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:52 BXT-2 kernel: [ 597.599547] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599553] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599558] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599563] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599568] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599573] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599578] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.599583] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599588] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.599593] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.599598] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.599603] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:52 BXT-2 kernel: [ 597.600334] [drm:intel_crtc_set_crc_source [i915]] unknown source foo >May 24 03:31:52 BXT-2 kernel: [ 597.628518] Console: switching to colour frame buffer device 240x67 >May 24 03:31:52 BXT-2 kernel: [ 597.884296] Console: switching to colour dummy device 80x25 >May 24 03:31:52 BXT-2 kernel: [ 597.905960] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.906038] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.906058] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:52 BXT-2 kernel: [ 597.906091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.906146] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.906734] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:52 BXT-2 kernel: [ 597.907648] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:52 BXT-2 kernel: [ 597.907697] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:52 BXT-2 kernel: [ 597.907739] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.907782] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.908320] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:52 BXT-2 kernel: [ 597.908368] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:52 BXT-2 kernel: [ 597.913227] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:52 BXT-2 kernel: [ 597.913292] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:52 BXT-2 kernel: [ 597.913299] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913305] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913310] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913315] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913320] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913325] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913330] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.913335] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913340] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.913345] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.913350] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.913356] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:52 BXT-2 kernel: [ 597.920236] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.920301] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 597.920317] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:52 BXT-2 kernel: [ 597.920814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.920876] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 597.921433] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:52 BXT-2 kernel: [ 597.922562] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:52 BXT-2 kernel: [ 597.922610] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:52 BXT-2 kernel: [ 597.922653] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.922695] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 597.923201] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:52 BXT-2 kernel: [ 597.923246] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:52 BXT-2 kernel: [ 597.928282] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:52 BXT-2 kernel: [ 597.928347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:52 BXT-2 kernel: [ 597.928354] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928359] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928364] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928370] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928375] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928380] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928385] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.928390] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928395] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 597.928577] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.928584] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 597.928589] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:52 BXT-2 kernel: [ 597.929302] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words >May 24 03:31:52 BXT-2 kernel: [ 597.961886] Console: switching to colour frame buffer device 240x67 >May 24 03:31:52 BXT-2 kernel: [ 598.214618] Console: switching to colour dummy device 80x25 >May 24 03:31:52 BXT-2 kernel: [ 598.232032] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 598.232093] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 598.232109] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:52 BXT-2 kernel: [ 598.232131] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 598.232177] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 598.232792] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:52 BXT-2 kernel: [ 598.233681] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:52 BXT-2 kernel: [ 598.233728] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:52 BXT-2 kernel: [ 598.233771] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 598.233816] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 598.234371] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:52 BXT-2 kernel: [ 598.234417] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:52 BXT-2 kernel: [ 598.241814] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:52 BXT-2 kernel: [ 598.241881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:52 BXT-2 kernel: [ 598.241888] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241893] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241899] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241904] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241909] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241914] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241919] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 598.241924] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241929] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.241934] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 598.241939] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 598.241944] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:52 BXT-2 kernel: [ 598.249186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 598.249249] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:52 BXT-2 kernel: [ 598.249266] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:52 BXT-2 kernel: [ 598.249774] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 598.249870] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:52 BXT-2 kernel: [ 598.250624] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:52 BXT-2 kernel: [ 598.251525] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:52 BXT-2 kernel: [ 598.251572] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:52 BXT-2 kernel: [ 598.251614] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 598.251657] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:52 BXT-2 kernel: [ 598.252138] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:52 BXT-2 kernel: [ 598.252181] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:52 BXT-2 kernel: [ 598.257149] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:52 BXT-2 kernel: [ 598.257215] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:52 BXT-2 kernel: [ 598.257222] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257228] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257233] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257238] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257243] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257248] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257253] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 598.257258] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257263] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:52 BXT-2 kernel: [ 598.257268] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 598.257273] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:52 BXT-2 kernel: [ 598.257278] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:52 BXT-2 kernel: [ 598.258076] [drm:display_crc_ctl_write [i915]] too many words, allowed <= 3 >May 24 03:31:52 BXT-2 kernel: [ 598.258114] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words >May 24 03:31:52 BXT-2 kernel: [ 598.278640] Console: switching to colour frame buffer device 240x67 >May 24 03:31:53 BXT-2 kernel: [ 598.507030] Console: switching to colour dummy device 80x25 >May 24 03:31:53 BXT-2 kernel: [ 598.533967] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 598.534030] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 598.534046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:53 BXT-2 kernel: [ 598.534070] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.534118] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.534695] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:53 BXT-2 kernel: [ 598.535570] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:53 BXT-2 kernel: [ 598.535618] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:53 BXT-2 kernel: [ 598.535660] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 598.535703] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 598.536203] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:53 BXT-2 kernel: [ 598.536247] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:53 BXT-2 kernel: [ 598.541019] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:53 BXT-2 kernel: [ 598.541082] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:53 BXT-2 kernel: [ 598.541089] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541094] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541099] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541104] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541109] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541114] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541119] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 598.541124] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541129] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.541134] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 598.541139] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 598.541144] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:53 BXT-2 kernel: [ 598.548142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 598.548204] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 598.548219] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:53 BXT-2 kernel: [ 598.548590] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.548649] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.549195] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:53 BXT-2 kernel: [ 598.550078] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:53 BXT-2 kernel: [ 598.550123] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:53 BXT-2 kernel: [ 598.550166] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 598.550208] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 598.550731] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:53 BXT-2 kernel: [ 598.550775] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:53 BXT-2 kernel: [ 598.555607] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:53 BXT-2 kernel: [ 598.555668] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:53 BXT-2 kernel: [ 598.555675] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555680] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555685] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555690] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555695] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555700] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555705] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 598.555710] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555715] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.555720] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 598.555725] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 598.555730] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:53 BXT-2 kernel: [ 598.556877] [drm:drm_mode_addfb2] [FB:79] >May 24 03:31:53 BXT-2 kernel: [ 598.572578] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 598.572640] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.594936] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:53 BXT-2 kernel: [ 598.595389] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:53 BXT-2 kernel: [ 598.661883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.662022] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:53 BXT-2 kernel: [ 598.679831] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:53 BXT-2 kernel: [ 598.679945] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.680036] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.680359] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.680403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:53 BXT-2 kernel: [ 598.680494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.680539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.680583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.680626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:53 BXT-2 kernel: [ 598.680674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.680717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.680760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.680803] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.680850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:53 BXT-2 kernel: [ 598.680895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:53 BXT-2 kernel: [ 598.680940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.681001] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:53 BXT-2 kernel: [ 598.681045] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.681099] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.681160] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 598.681212] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:53 BXT-2 kernel: [ 598.681256] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:53 BXT-2 kernel: [ 598.681295] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:53 BXT-2 kernel: [ 598.681879] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:53 BXT-2 kernel: [ 598.682934] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:53 BXT-2 kernel: [ 598.703935] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 598.703999] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.704128] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:53 BXT-2 kernel: [ 598.704172] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:53 BXT-2 kernel: [ 598.704216] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:53 BXT-2 kernel: [ 598.704260] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:53 BXT-2 kernel: [ 598.704302] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:53 BXT-2 kernel: [ 598.704346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.704389] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:53 BXT-2 kernel: [ 598.704432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.704969] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:53 BXT-2 kernel: [ 598.705011] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.705053] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:53 BXT-2 kernel: [ 598.705062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.705104] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:53 BXT-2 kernel: [ 598.705110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.705153] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.705196] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:53 BXT-2 kernel: [ 598.705239] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:53 BXT-2 kernel: [ 598.705281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:53 BXT-2 kernel: [ 598.705323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.705368] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:53 BXT-2 kernel: [ 598.705410] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:53 BXT-2 kernel: [ 598.705966] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.706010] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.706052] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.706095] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.706164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.706217] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.706261] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:53 BXT-2 kernel: [ 598.707154] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:53 BXT-2 kernel: [ 598.707193] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:53 BXT-2 kernel: [ 598.707681] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:53 BXT-2 kernel: [ 598.708104] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.708145] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.708201] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:53 BXT-2 kernel: [ 598.708720] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.709049] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.709093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:53 BXT-2 kernel: [ 598.709136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.709179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.709221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.709264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:53 BXT-2 kernel: [ 598.709307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.709349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.709392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.709856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:53 BXT-2 kernel: [ 598.709905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:53 BXT-2 kernel: [ 598.709950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.710025] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:53 BXT-2 kernel: [ 598.710068] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.711710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.711755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.711799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:53 BXT-2 kernel: [ 598.712705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.712748] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.713615] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:53 BXT-2 kernel: [ 598.713660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:53 BXT-2 kernel: [ 598.714989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:53 BXT-2 kernel: [ 598.717090] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:53 BXT-2 kernel: [ 598.718158] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:53 BXT-2 kernel: [ 598.735038] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.735094] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 598.735264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.818718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.818858] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:53 BXT-2 kernel: [ 598.837017] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:53 BXT-2 kernel: [ 598.837130] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.837221] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.837545] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.837590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:53 BXT-2 kernel: [ 598.837633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.837676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.837719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.837762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:53 BXT-2 kernel: [ 598.837809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.837854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.837897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.837942] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.837990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:53 BXT-2 kernel: [ 598.838035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:53 BXT-2 kernel: [ 598.838081] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.838142] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:53 BXT-2 kernel: [ 598.838185] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.838240] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.838301] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 598.838354] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:53 BXT-2 kernel: [ 598.838399] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:53 BXT-2 kernel: [ 598.838478] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:53 BXT-2 kernel: [ 598.839030] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:53 BXT-2 kernel: [ 598.865344] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:53 BXT-2 kernel: [ 598.865387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:53 BXT-2 kernel: [ 598.865431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:53 BXT-2 kernel: [ 598.865499] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:53 BXT-2 kernel: [ 598.865540] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:53 BXT-2 kernel: [ 598.865583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.865625] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:53 BXT-2 kernel: [ 598.865667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.865709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:53 BXT-2 kernel: [ 598.865750] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.865790] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:53 BXT-2 kernel: [ 598.865798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.865838] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:53 BXT-2 kernel: [ 598.865843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.865885] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:53 BXT-2 kernel: [ 598.865927] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:53 BXT-2 kernel: [ 598.865968] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:53 BXT-2 kernel: [ 598.866009] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:53 BXT-2 kernel: [ 598.866050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:53 BXT-2 kernel: [ 598.866094] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:53 BXT-2 kernel: [ 598.866134] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:53 BXT-2 kernel: [ 598.866176] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.866217] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.866258] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.866299] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 598.866342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.866394] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.866454] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:53 BXT-2 kernel: [ 598.866576] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:53 BXT-2 kernel: [ 598.866612] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:53 BXT-2 kernel: [ 598.866899] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:53 BXT-2 kernel: [ 598.866954] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.866993] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 598.867048] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:53 BXT-2 kernel: [ 598.867336] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.867866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 598.867909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:53 BXT-2 kernel: [ 598.867951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.867992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.868033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.868075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:53 BXT-2 kernel: [ 598.868116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 598.868157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 598.868199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 598.868240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:53 BXT-2 kernel: [ 598.868285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:53 BXT-2 kernel: [ 598.868329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.868401] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:53 BXT-2 kernel: [ 598.868479] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.869913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.869954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.869997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:53 BXT-2 kernel: [ 598.870761] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.870802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:53 BXT-2 kernel: [ 598.871535] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:53 BXT-2 kernel: [ 598.871577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:53 BXT-2 kernel: [ 598.872615] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:53 BXT-2 kernel: [ 598.874708] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:53 BXT-2 kernel: [ 598.875898] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:53 BXT-2 kernel: [ 598.892788] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 598.892842] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 598.893018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 598.893379] Console: switching to colour frame buffer device 240x67 >May 24 03:31:53 BXT-2 kernel: [ 599.126931] Console: switching to colour dummy device 80x25 >May 24 03:31:53 BXT-2 kernel: [ 599.146973] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 599.147033] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 599.147049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:53 BXT-2 kernel: [ 599.147072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.147118] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.147673] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:53 BXT-2 kernel: [ 599.148549] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:53 BXT-2 kernel: [ 599.148595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:53 BXT-2 kernel: [ 599.148638] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 599.148681] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 599.149177] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:53 BXT-2 kernel: [ 599.149220] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:53 BXT-2 kernel: [ 599.153990] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:53 BXT-2 kernel: [ 599.154052] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:53 BXT-2 kernel: [ 599.154060] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154065] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154070] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154075] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154080] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154085] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154090] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 599.154096] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154101] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.154106] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 599.154111] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 599.154116] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:53 BXT-2 kernel: [ 599.160857] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 599.160922] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:53 BXT-2 kernel: [ 599.160938] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:53 BXT-2 kernel: [ 599.161296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.161347] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.161906] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:53 BXT-2 kernel: [ 599.162788] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:53 BXT-2 kernel: [ 599.162834] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:53 BXT-2 kernel: [ 599.162877] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 599.162920] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:53 BXT-2 kernel: [ 599.163406] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:53 BXT-2 kernel: [ 599.163625] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:53 BXT-2 kernel: [ 599.168367] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:53 BXT-2 kernel: [ 599.168458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:53 BXT-2 kernel: [ 599.168465] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168470] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168475] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168480] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168485] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168491] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168496] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 599.168501] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168506] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.168511] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 599.168516] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:53 BXT-2 kernel: [ 599.168521] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:53 BXT-2 kernel: [ 599.169667] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:53 BXT-2 kernel: [ 599.185197] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 599.185264] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.209366] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:53 BXT-2 kernel: [ 599.209887] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:53 BXT-2 kernel: [ 599.276285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:53 BXT-2 kernel: [ 599.276415] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:53 BXT-2 kernel: [ 599.294705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:53 BXT-2 kernel: [ 599.294819] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 599.294911] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 599.295235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 599.295279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:53 BXT-2 kernel: [ 599.295322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 599.295365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 599.295408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 599.295530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:53 BXT-2 kernel: [ 599.295579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 599.295625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 599.295667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 599.295710] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.295759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:53 BXT-2 kernel: [ 599.295804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:53 BXT-2 kernel: [ 599.295849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 599.295911] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:53 BXT-2 kernel: [ 599.295954] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 599.296008] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 599.296070] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 599.296123] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:53 BXT-2 kernel: [ 599.296166] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:53 BXT-2 kernel: [ 599.296205] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:53 BXT-2 kernel: [ 599.296828] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:53 BXT-2 kernel: [ 599.298335] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:53 BXT-2 kernel: [ 599.317485] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 599.317534] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.317661] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:53 BXT-2 kernel: [ 599.317704] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:53 BXT-2 kernel: [ 599.317749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:53 BXT-2 kernel: [ 599.317793] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:53 BXT-2 kernel: [ 599.317835] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:53 BXT-2 kernel: [ 599.317879] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:53 BXT-2 kernel: [ 599.317922] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:53 BXT-2 kernel: [ 599.317965] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:53 BXT-2 kernel: [ 599.318008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:53 BXT-2 kernel: [ 599.318050] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:53 BXT-2 kernel: [ 599.318092] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:53 BXT-2 kernel: [ 599.318099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.318140] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:53 BXT-2 kernel: [ 599.318146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.318189] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:53 BXT-2 kernel: [ 599.318232] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:53 BXT-2 kernel: [ 599.318275] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:53 BXT-2 kernel: [ 599.318317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:53 BXT-2 kernel: [ 599.318359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:53 BXT-2 kernel: [ 599.318404] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:53 BXT-2 kernel: [ 599.318494] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:53 BXT-2 kernel: [ 599.318543] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 599.318588] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 599.318633] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 599.318678] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:53 BXT-2 kernel: [ 599.318742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:53 BXT-2 kernel: [ 599.318795] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 599.318838] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:53 BXT-2 kernel: [ 599.319440] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:53 BXT-2 kernel: [ 599.319510] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:53 BXT-2 kernel: [ 599.319801] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:53 BXT-2 kernel: [ 599.319856] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 599.319898] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:53 BXT-2 kernel: [ 599.319954] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:53 BXT-2 kernel: [ 599.320421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 599.320971] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:53 BXT-2 kernel: [ 599.321016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:53 BXT-2 kernel: [ 599.321059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 599.321102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 599.321145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 599.321191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:53 BXT-2 kernel: [ 599.321234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:53 BXT-2 kernel: [ 599.321276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:53 BXT-2 kernel: [ 599.321319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:53 BXT-2 kernel: [ 599.321363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:53 BXT-2 kernel: [ 599.321411] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:53 BXT-2 kernel: [ 599.321537] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 599.321611] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:53 BXT-2 kernel: [ 599.321656] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:53 BXT-2 kernel: [ 599.323616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:53 BXT-2 kernel: [ 599.323660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:53 BXT-2 kernel: [ 599.323705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:53 BXT-2 kernel: [ 599.324755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:53 BXT-2 kernel: [ 599.324802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:53 BXT-2 kernel: [ 599.325694] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:53 BXT-2 kernel: [ 599.325739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:53 BXT-2 kernel: [ 599.327114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:53 BXT-2 kernel: [ 599.329226] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:53 BXT-2 kernel: [ 599.330343] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:53 BXT-2 kernel: [ 599.347223] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:53 BXT-2 kernel: [ 599.347280] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:53 BXT-2 kernel: [ 599.347660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.430852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.431013] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:54 BXT-2 kernel: [ 599.448848] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:54 BXT-2 kernel: [ 599.448960] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.449053] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.449978] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.450026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:54 BXT-2 kernel: [ 599.450070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.450113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.450156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.450198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:54 BXT-2 kernel: [ 599.450249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.450291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.450334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.450378] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.450425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:54 BXT-2 kernel: [ 599.450519] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:54 BXT-2 kernel: [ 599.450564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.450629] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:54 BXT-2 kernel: [ 599.450672] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.450727] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.450789] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 599.450842] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:54 BXT-2 kernel: [ 599.450886] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:54 BXT-2 kernel: [ 599.450929] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:54 BXT-2 kernel: [ 599.451568] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:54 BXT-2 kernel: [ 599.476364] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:54 BXT-2 kernel: [ 599.476406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:54 BXT-2 kernel: [ 599.476483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:54 BXT-2 kernel: [ 599.476526] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:54 BXT-2 kernel: [ 599.476566] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:54 BXT-2 kernel: [ 599.476609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.476651] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:54 BXT-2 kernel: [ 599.476693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.476735] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:54 BXT-2 kernel: [ 599.476776] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.476817] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:54 BXT-2 kernel: [ 599.476824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.476865] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:54 BXT-2 kernel: [ 599.476869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.476911] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.476953] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:54 BXT-2 kernel: [ 599.476994] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:54 BXT-2 kernel: [ 599.477035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:54 BXT-2 kernel: [ 599.477076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.477121] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:54 BXT-2 kernel: [ 599.477162] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:54 BXT-2 kernel: [ 599.477204] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.477245] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.477288] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.477329] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.477373] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.477424] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.477509] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:54 BXT-2 kernel: [ 599.477632] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:54 BXT-2 kernel: [ 599.477667] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:54 BXT-2 kernel: [ 599.477955] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:54 BXT-2 kernel: [ 599.478010] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.478049] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.478104] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:54 BXT-2 kernel: [ 599.478358] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.478684] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.478727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:54 BXT-2 kernel: [ 599.478769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.478810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.478851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.478893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:54 BXT-2 kernel: [ 599.478934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.478976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.479017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.479059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:54 BXT-2 kernel: [ 599.479104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:54 BXT-2 kernel: [ 599.479148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.479220] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:54 BXT-2 kernel: [ 599.479261] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.480701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:54 BXT-2 kernel: [ 599.480742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:54 BXT-2 kernel: [ 599.480785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:54 BXT-2 kernel: [ 599.481579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:54 BXT-2 kernel: [ 599.481619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:54 BXT-2 kernel: [ 599.482345] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:54 BXT-2 kernel: [ 599.482386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:54 BXT-2 kernel: [ 599.483472] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:54 BXT-2 kernel: [ 599.485547] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:54 BXT-2 kernel: [ 599.486716] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:54 BXT-2 kernel: [ 599.503630] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.503683] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 599.503860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.504211] Console: switching to colour frame buffer device 240x67 >May 24 03:31:54 BXT-2 kernel: [ 599.737270] Console: switching to colour dummy device 80x25 >May 24 03:31:54 BXT-2 kernel: [ 599.756056] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:54 BXT-2 kernel: [ 599.756118] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:54 BXT-2 kernel: [ 599.756134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:54 BXT-2 kernel: [ 599.756157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.756203] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.756801] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:54 BXT-2 kernel: [ 599.757686] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:54 BXT-2 kernel: [ 599.757734] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:54 BXT-2 kernel: [ 599.757777] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:54 BXT-2 kernel: [ 599.757819] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:54 BXT-2 kernel: [ 599.758327] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:54 BXT-2 kernel: [ 599.758370] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:54 BXT-2 kernel: [ 599.763369] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:54 BXT-2 kernel: [ 599.763571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:54 BXT-2 kernel: [ 599.763579] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763584] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763589] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763594] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763599] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763604] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763609] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:54 BXT-2 kernel: [ 599.763614] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763619] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.763624] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:54 BXT-2 kernel: [ 599.763629] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:54 BXT-2 kernel: [ 599.763634] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:54 BXT-2 kernel: [ 599.770400] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:54 BXT-2 kernel: [ 599.770476] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:54 BXT-2 kernel: [ 599.770493] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:54 BXT-2 kernel: [ 599.770804] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.770851] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.771388] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:54 BXT-2 kernel: [ 599.772385] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:54 BXT-2 kernel: [ 599.772432] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:54 BXT-2 kernel: [ 599.772531] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:54 BXT-2 kernel: [ 599.772574] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:54 BXT-2 kernel: [ 599.773077] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:54 BXT-2 kernel: [ 599.773120] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:54 BXT-2 kernel: [ 599.778042] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:54 BXT-2 kernel: [ 599.778105] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:54 BXT-2 kernel: [ 599.778112] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778117] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778122] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778127] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778132] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778137] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778142] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:54 BXT-2 kernel: [ 599.778147] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778152] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.778157] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:54 BXT-2 kernel: [ 599.778162] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:54 BXT-2 kernel: [ 599.778167] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:54 BXT-2 kernel: [ 599.780015] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:54 BXT-2 kernel: [ 599.795927] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 599.795994] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.820160] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:54 BXT-2 kernel: [ 599.820782] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:54 BXT-2 kernel: [ 599.920560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.920696] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:54 BXT-2 kernel: [ 599.938722] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:54 BXT-2 kernel: [ 599.938837] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.938930] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.939258] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.939302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:54 BXT-2 kernel: [ 599.939345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.939388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.939431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.939556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:54 BXT-2 kernel: [ 599.939605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.939648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.939691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.939734] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.939782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:54 BXT-2 kernel: [ 599.939827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:54 BXT-2 kernel: [ 599.939872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.939933] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:54 BXT-2 kernel: [ 599.939976] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.940030] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.940093] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 599.940145] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:54 BXT-2 kernel: [ 599.940188] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:54 BXT-2 kernel: [ 599.940227] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:54 BXT-2 kernel: [ 599.940813] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:54 BXT-2 kernel: [ 599.943120] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:54 BXT-2 kernel: [ 599.966074] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 599.966138] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.966272] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:54 BXT-2 kernel: [ 599.966315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:54 BXT-2 kernel: [ 599.966360] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:54 BXT-2 kernel: [ 599.966404] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:54 BXT-2 kernel: [ 599.966917] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:54 BXT-2 kernel: [ 599.966966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.967011] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:54 BXT-2 kernel: [ 599.967055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.967098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:54 BXT-2 kernel: [ 599.967140] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.967182] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:54 BXT-2 kernel: [ 599.967191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.967233] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:54 BXT-2 kernel: [ 599.967239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.967282] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:54 BXT-2 kernel: [ 599.967325] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:54 BXT-2 kernel: [ 599.967368] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:54 BXT-2 kernel: [ 599.967411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:54 BXT-2 kernel: [ 599.967787] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:54 BXT-2 kernel: [ 599.967834] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:54 BXT-2 kernel: [ 599.967877] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:54 BXT-2 kernel: [ 599.967921] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.967965] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.968008] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.968052] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 599.968125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.968179] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.968223] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:54 BXT-2 kernel: [ 599.969212] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:54 BXT-2 kernel: [ 599.969252] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:54 BXT-2 kernel: [ 599.969880] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:54 BXT-2 kernel: [ 599.970199] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.970241] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 599.970296] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:54 BXT-2 kernel: [ 599.970905] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.971234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 599.971278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:54 BXT-2 kernel: [ 599.971322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.971365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.971408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.971520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:54 BXT-2 kernel: [ 599.971566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 599.971613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 599.971658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 599.971704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:54 BXT-2 kernel: [ 599.971755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:54 BXT-2 kernel: [ 599.972071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.972148] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:54 BXT-2 kernel: [ 599.972192] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 599.973626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:54 BXT-2 kernel: [ 599.973671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:54 BXT-2 kernel: [ 599.973716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:54 BXT-2 kernel: [ 599.974531] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:54 BXT-2 kernel: [ 599.974583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:54 BXT-2 kernel: [ 599.975637] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:54 BXT-2 kernel: [ 599.977728] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:54 BXT-2 kernel: [ 599.978750] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:54 BXT-2 kernel: [ 599.995631] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 599.995688] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 599.995859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.112579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:54 BXT-2 kernel: [ 600.112720] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:54 BXT-2 kernel: [ 600.130827] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:54 BXT-2 kernel: [ 600.130940] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.131033] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 600.131357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 600.131401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:54 BXT-2 kernel: [ 600.131502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 600.131549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 600.131593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 600.131637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:54 BXT-2 kernel: [ 600.131685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 600.131728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 600.131772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 600.131816] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 600.131864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:54 BXT-2 kernel: [ 600.132005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:54 BXT-2 kernel: [ 600.132050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.132114] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:54 BXT-2 kernel: [ 600.132158] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 600.132213] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 600.132276] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 600.132330] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:54 BXT-2 kernel: [ 600.132374] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:54 BXT-2 kernel: [ 600.132413] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:54 BXT-2 kernel: [ 600.133006] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:54 BXT-2 kernel: [ 600.161346] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:54 BXT-2 kernel: [ 600.161390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:54 BXT-2 kernel: [ 600.161474] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:54 BXT-2 kernel: [ 600.161517] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:54 BXT-2 kernel: [ 600.161558] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:54 BXT-2 kernel: [ 600.161602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:54 BXT-2 kernel: [ 600.161645] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:54 BXT-2 kernel: [ 600.161687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:54 BXT-2 kernel: [ 600.161729] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:54 BXT-2 kernel: [ 600.161770] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:54 BXT-2 kernel: [ 600.161811] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:54 BXT-2 kernel: [ 600.161818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 600.161859] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:54 BXT-2 kernel: [ 600.161864] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:54 BXT-2 kernel: [ 600.161906] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:54 BXT-2 kernel: [ 600.161948] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:54 BXT-2 kernel: [ 600.161989] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:54 BXT-2 kernel: [ 600.162031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:54 BXT-2 kernel: [ 600.162072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:54 BXT-2 kernel: [ 600.162116] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:54 BXT-2 kernel: [ 600.162157] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:54 BXT-2 kernel: [ 600.162199] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 600.162241] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 600.162282] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 600.162324] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:54 BXT-2 kernel: [ 600.162370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:54 BXT-2 kernel: [ 600.162424] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.162521] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:54 BXT-2 kernel: [ 600.162657] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:54 BXT-2 kernel: [ 600.162693] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:54 BXT-2 kernel: [ 600.162988] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:54 BXT-2 kernel: [ 600.163046] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 600.163085] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:54 BXT-2 kernel: [ 600.163140] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:54 BXT-2 kernel: [ 600.163398] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 600.163810] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:54 BXT-2 kernel: [ 600.163854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:54 BXT-2 kernel: [ 600.163895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 600.163937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 600.163978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 600.164020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:54 BXT-2 kernel: [ 600.164061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:54 BXT-2 kernel: [ 600.164103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:54 BXT-2 kernel: [ 600.164144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:54 BXT-2 kernel: [ 600.164186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:54 BXT-2 kernel: [ 600.164232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:54 BXT-2 kernel: [ 600.164276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.164350] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:54 BXT-2 kernel: [ 600.164391] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.165849] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:54 BXT-2 kernel: [ 600.165891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:54 BXT-2 kernel: [ 600.165935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:54 BXT-2 kernel: [ 600.166735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:54 BXT-2 kernel: [ 600.166776] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:54 BXT-2 kernel: [ 600.167496] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:54 BXT-2 kernel: [ 600.167537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:54 BXT-2 kernel: [ 600.168575] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:54 BXT-2 kernel: [ 600.170663] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:54 BXT-2 kernel: [ 600.171842] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:54 BXT-2 kernel: [ 600.188733] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:54 BXT-2 kernel: [ 600.188787] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:54 BXT-2 kernel: [ 600.188963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:54 BXT-2 kernel: [ 600.189332] Console: switching to colour frame buffer device 240x67 >May 24 03:31:55 BXT-2 kernel: [ 600.420932] Console: switching to colour dummy device 80x25 >May 24 03:31:55 BXT-2 kernel: [ 600.439977] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 600.440038] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 600.440054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:55 BXT-2 kernel: [ 600.440077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.440122] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.440681] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:55 BXT-2 kernel: [ 600.441555] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:55 BXT-2 kernel: [ 600.441601] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:55 BXT-2 kernel: [ 600.441643] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 600.441686] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 600.442189] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:55 BXT-2 kernel: [ 600.442233] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:55 BXT-2 kernel: [ 600.447105] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:55 BXT-2 kernel: [ 600.447170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:55 BXT-2 kernel: [ 600.447177] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447183] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447188] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447193] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447198] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447203] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447208] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 600.447213] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447218] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.447223] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 600.447228] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 600.447233] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:55 BXT-2 kernel: [ 600.454878] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 600.454940] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 600.454956] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:55 BXT-2 kernel: [ 600.455310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.455362] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.455967] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:55 BXT-2 kernel: [ 600.456867] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:55 BXT-2 kernel: [ 600.456913] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:55 BXT-2 kernel: [ 600.456956] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 600.456998] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 600.457606] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:55 BXT-2 kernel: [ 600.457650] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:55 BXT-2 kernel: [ 600.462502] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:55 BXT-2 kernel: [ 600.462570] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:55 BXT-2 kernel: [ 600.462577] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462583] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462588] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462593] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462598] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462603] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462608] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 600.462613] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462618] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.462623] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 600.462628] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 600.462633] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:55 BXT-2 kernel: [ 600.463790] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:55 BXT-2 kernel: [ 600.479236] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:55 BXT-2 kernel: [ 600.479299] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.505293] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:31:55 BXT-2 kernel: [ 600.505867] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:31:55 BXT-2 kernel: [ 600.605695] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.605836] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:55 BXT-2 kernel: [ 600.623752] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:55 BXT-2 kernel: [ 600.623866] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.623956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.624277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.624321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:55 BXT-2 kernel: [ 600.624364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.624407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.624494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.624537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:55 BXT-2 kernel: [ 600.624589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.624632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.624676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.624719] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.624767] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:55 BXT-2 kernel: [ 600.624815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:55 BXT-2 kernel: [ 600.624861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.624921] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:55 BXT-2 kernel: [ 600.624964] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.625019] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.625082] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:55 BXT-2 kernel: [ 600.625135] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:55 BXT-2 kernel: [ 600.625179] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:55 BXT-2 kernel: [ 600.625218] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:55 BXT-2 kernel: [ 600.625826] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:55 BXT-2 kernel: [ 600.627285] [drm:drm_mode_addfb2] [FB:78] >May 24 03:31:55 BXT-2 kernel: [ 600.649990] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:31:55 BXT-2 kernel: [ 600.650056] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.650189] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:55 BXT-2 kernel: [ 600.650233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:55 BXT-2 kernel: [ 600.650278] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:55 BXT-2 kernel: [ 600.650321] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:55 BXT-2 kernel: [ 600.650364] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:55 BXT-2 kernel: [ 600.650408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.650488] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:55 BXT-2 kernel: [ 600.650536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.650582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:55 BXT-2 kernel: [ 600.650627] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.650674] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:55 BXT-2 kernel: [ 600.650684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.650726] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:55 BXT-2 kernel: [ 600.650732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.650775] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.650822] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:55 BXT-2 kernel: [ 600.650868] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:55 BXT-2 kernel: [ 600.650911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:55 BXT-2 kernel: [ 600.650953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.650998] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:55 BXT-2 kernel: [ 600.651040] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:55 BXT-2 kernel: [ 600.651083] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.651126] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.651169] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.651214] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.651278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.651330] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.651375] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:55 BXT-2 kernel: [ 600.652021] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:55 BXT-2 kernel: [ 600.652061] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:55 BXT-2 kernel: [ 600.652351] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:55 BXT-2 kernel: [ 600.652406] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.652474] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.652533] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:55 BXT-2 kernel: [ 600.652789] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.653114] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.653158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:55 BXT-2 kernel: [ 600.653203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.653246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.653289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.653333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:55 BXT-2 kernel: [ 600.653377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.653421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.653500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.653545] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:55 BXT-2 kernel: [ 600.653594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:55 BXT-2 kernel: [ 600.653640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.653716] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:55 BXT-2 kernel: [ 600.653759] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.655220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.655264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.655308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:55 BXT-2 kernel: [ 600.656089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.656133] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.656867] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:55 BXT-2 kernel: [ 600.656911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:55 BXT-2 kernel: [ 600.657963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:55 BXT-2 kernel: [ 600.660060] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:55 BXT-2 kernel: [ 600.661140] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:55 BXT-2 kernel: [ 600.678041] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.678097] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:55 BXT-2 kernel: [ 600.678268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.794938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.795079] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:31:55 BXT-2 kernel: [ 600.813109] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:31:55 BXT-2 kernel: [ 600.813223] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.813313] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.813660] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.813705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:55 BXT-2 kernel: [ 600.813750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.813794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.813837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.813881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:55 BXT-2 kernel: [ 600.813928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.813972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.814015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.814059] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.814107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:55 BXT-2 kernel: [ 600.814155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:55 BXT-2 kernel: [ 600.814200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.814267] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:31:55 BXT-2 kernel: [ 600.814311] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.814366] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.814428] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:55 BXT-2 kernel: [ 600.814522] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:31:55 BXT-2 kernel: [ 600.814568] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:31:55 BXT-2 kernel: [ 600.814610] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:31:55 BXT-2 kernel: [ 600.815160] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:31:55 BXT-2 kernel: [ 600.842332] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:31:55 BXT-2 kernel: [ 600.842376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:31:55 BXT-2 kernel: [ 600.842420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:31:55 BXT-2 kernel: [ 600.842489] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:31:55 BXT-2 kernel: [ 600.842530] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:31:55 BXT-2 kernel: [ 600.842574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.842617] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:31:55 BXT-2 kernel: [ 600.842658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.842700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:31:55 BXT-2 kernel: [ 600.842741] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.842783] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:31:55 BXT-2 kernel: [ 600.842790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.842831] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:31:55 BXT-2 kernel: [ 600.842835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.842877] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:31:55 BXT-2 kernel: [ 600.842919] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:31:55 BXT-2 kernel: [ 600.842961] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:31:55 BXT-2 kernel: [ 600.843002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:31:55 BXT-2 kernel: [ 600.843043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:31:55 BXT-2 kernel: [ 600.843088] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:31:55 BXT-2 kernel: [ 600.843129] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:31:55 BXT-2 kernel: [ 600.843171] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.843212] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.843253] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.843295] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:31:55 BXT-2 kernel: [ 600.843341] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.843396] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.843469] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:31:55 BXT-2 kernel: [ 600.843605] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:31:55 BXT-2 kernel: [ 600.843641] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:31:55 BXT-2 kernel: [ 600.843932] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:31:55 BXT-2 kernel: [ 600.843987] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.844026] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:31:55 BXT-2 kernel: [ 600.844082] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:31:55 BXT-2 kernel: [ 600.844370] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.844705] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:31:55 BXT-2 kernel: [ 600.844748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:31:55 BXT-2 kernel: [ 600.844791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.844832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.844874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.844915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:31:55 BXT-2 kernel: [ 600.844957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:31:55 BXT-2 kernel: [ 600.844999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:31:55 BXT-2 kernel: [ 600.845040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:31:55 BXT-2 kernel: [ 600.845082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:31:55 BXT-2 kernel: [ 600.845130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:31:55 BXT-2 kernel: [ 600.845173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.845247] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:31:55 BXT-2 kernel: [ 600.845289] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.846766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.846808] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.846852] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:31:55 BXT-2 kernel: [ 600.847644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.847686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:31:55 BXT-2 kernel: [ 600.848432] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:31:55 BXT-2 kernel: [ 600.848494] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:31:55 BXT-2 kernel: [ 600.849667] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:31:55 BXT-2 kernel: [ 600.851783] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:31:55 BXT-2 kernel: [ 600.853045] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:31:55 BXT-2 kernel: [ 600.869951] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 600.870005] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:31:55 BXT-2 kernel: [ 600.870183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:31:55 BXT-2 kernel: [ 600.870575] Console: switching to colour frame buffer device 240x67 >May 24 03:31:55 BXT-2 kernel: [ 601.098293] Console: switching to colour dummy device 80x25 >May 24 03:31:55 BXT-2 kernel: [ 601.123156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 601.123216] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 601.123233] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:55 BXT-2 kernel: [ 601.123255] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 601.123301] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 601.124084] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:55 BXT-2 kernel: [ 601.125222] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:55 BXT-2 kernel: [ 601.125270] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:55 BXT-2 kernel: [ 601.125313] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 601.125356] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 601.126098] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:55 BXT-2 kernel: [ 601.126145] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:55 BXT-2 kernel: [ 601.131641] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:55 BXT-2 kernel: [ 601.131707] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:55 BXT-2 kernel: [ 601.131714] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131719] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131724] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131729] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131734] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131739] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131744] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 601.131749] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131754] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.131760] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 601.131765] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 601.131770] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:55 BXT-2 kernel: [ 601.138444] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 601.138505] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:31:55 BXT-2 kernel: [ 601.138523] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:31:55 BXT-2 kernel: [ 601.138877] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 601.138924] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:31:55 BXT-2 kernel: [ 601.139525] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:31:55 BXT-2 kernel: [ 601.140519] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:31:55 BXT-2 kernel: [ 601.140566] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:31:55 BXT-2 kernel: [ 601.140608] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 601.140650] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:31:55 BXT-2 kernel: [ 601.141137] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:31:55 BXT-2 kernel: [ 601.141180] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:31:55 BXT-2 kernel: [ 601.146042] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:31:55 BXT-2 kernel: [ 601.146105] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:31:55 BXT-2 kernel: [ 601.146112] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146117] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146123] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146128] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146133] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146138] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146143] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 601.146148] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146153] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:31:55 BXT-2 kernel: [ 601.146158] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 601.146163] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:31:55 BXT-2 kernel: [ 601.146168] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:31:55 BXT-2 kernel: [ 601.260591] PM: Syncing filesystems ... done. >May 24 03:31:55 BXT-2 kernel: [ 601.268721] PM: Preparing system for sleep (mem) >May 24 03:32:12 BXT-2 kernel: [ 601.269353] Freezing user space processes ... (elapsed 0.115 seconds) done. >May 24 03:32:12 BXT-2 kernel: [ 601.384584] OOM killer disabled. >May 24 03:32:12 BXT-2 kernel: [ 601.384588] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 03:32:12 BXT-2 kernel: [ 601.385646] PM: Suspending system (mem) >May 24 03:32:12 BXT-2 kernel: [ 601.385755] Suspending console(s) (use no_console_suspend to debug) >May 24 03:32:12 BXT-2 kernel: [ 601.507215] sd 0:0:0:0: [sda] Synchronizing SCSI cache >May 24 03:32:12 BXT-2 kernel: [ 601.512932] system 00:00: System wakeup disabled by ACPI >May 24 03:32:12 BXT-2 kernel: [ 601.513667] ACPI : EC: event blocked >May 24 03:32:12 BXT-2 kernel: [ 601.514041] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:32:12 BXT-2 kernel: [ 601.515748] sd 0:0:0:0: [sda] Stopping disk >May 24 03:32:12 BXT-2 kernel: [ 601.543212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:12 BXT-2 kernel: [ 601.543597] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:12 BXT-2 kernel: [ 601.559844] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:12 BXT-2 kernel: [ 601.561772] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 601.563426] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 601.564631] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 601.564785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:12 BXT-2 kernel: [ 601.564937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 601.565089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 601.565240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 601.565393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:12 BXT-2 kernel: [ 601.565672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 601.565822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 601.565975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 601.566127] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 601.566282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:12 BXT-2 kernel: [ 601.566667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:12 BXT-2 kernel: [ 601.566821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 601.567331] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 601.872758] PM: suspend of devices complete after 366.269 msecs >May 24 03:32:12 BXT-2 kernel: [ 601.883642] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 601.883712] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:32:12 BXT-2 kernel: [ 601.883751] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 601.883891] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 601.883930] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:12 BXT-2 kernel: [ 601.883971] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:12 BXT-2 kernel: [ 601.884010] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:12 BXT-2 kernel: [ 601.884599] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:12 BXT-2 kernel: [ 601.884646] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:12 BXT-2 kernel: [ 601.885494] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 601.885530] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:32:12 BXT-2 kernel: [ 601.885574] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:32:12 BXT-2 kernel: [ 601.885616] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:32:12 BXT-2 kernel: [ 601.885661] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:32:12 BXT-2 kernel: [ 601.885701] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:32:12 BXT-2 kernel: [ 601.897530] PM: late suspend of devices complete after 24.764 msecs >May 24 03:32:12 BXT-2 kernel: [ 601.899897] ACPI : EC: interrupt blocked >May 24 03:32:12 BXT-2 kernel: [ 601.899948] r8169 0000:03:00.0: System wakeup enabled by ACPI >May 24 03:32:12 BXT-2 kernel: [ 601.900679] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI >May 24 03:32:12 BXT-2 kernel: [ 601.923575] PM: noirq suspend of devices complete after 26.034 msecs >May 24 03:32:12 BXT-2 kernel: [ 601.923820] ACPI: Preparing to enter system sleep state S3 >May 24 03:32:12 BXT-2 kernel: [ 601.926945] ACPI : EC: EC stopped >May 24 03:32:12 BXT-2 kernel: [ 601.926948] PM: Saving platform NVS memory >May 24 03:32:12 BXT-2 kernel: [ 601.928868] Disabling non-boot CPUs ... >May 24 03:32:12 BXT-2 kernel: [ 601.941873] Broke affinity for irq 369 >May 24 03:32:12 BXT-2 kernel: [ 601.941883] Broke affinity for irq 371 >May 24 03:32:12 BXT-2 kernel: [ 601.941892] Broke affinity for irq 373 >May 24 03:32:12 BXT-2 kernel: [ 601.943081] smpboot: CPU 1 is now offline >May 24 03:32:12 BXT-2 kernel: [ 601.962798] Broke affinity for irq 369 >May 24 03:32:12 BXT-2 kernel: [ 601.962810] Broke affinity for irq 370 >May 24 03:32:12 BXT-2 kernel: [ 601.962819] Broke affinity for irq 371 >May 24 03:32:12 BXT-2 kernel: [ 601.962831] Broke affinity for irq 373 >May 24 03:32:12 BXT-2 kernel: [ 601.964259] smpboot: CPU 2 is now offline >May 24 03:32:12 BXT-2 kernel: [ 601.984675] Broke affinity for irq 1 >May 24 03:32:12 BXT-2 kernel: [ 601.984693] Broke affinity for irq 8 >May 24 03:32:12 BXT-2 kernel: [ 601.984705] Broke affinity for irq 9 >May 24 03:32:12 BXT-2 kernel: [ 601.984719] Broke affinity for irq 12 >May 24 03:32:12 BXT-2 kernel: [ 601.984732] Broke affinity for irq 14 >May 24 03:32:12 BXT-2 kernel: [ 601.984943] Broke affinity for irq 367 >May 24 03:32:12 BXT-2 kernel: [ 601.984955] Broke affinity for irq 368 >May 24 03:32:12 BXT-2 kernel: [ 601.984966] Broke affinity for irq 369 >May 24 03:32:12 BXT-2 kernel: [ 601.984977] Broke affinity for irq 370 >May 24 03:32:12 BXT-2 kernel: [ 601.984989] Broke affinity for irq 371 >May 24 03:32:12 BXT-2 kernel: [ 601.985001] Broke affinity for irq 372 >May 24 03:32:12 BXT-2 kernel: [ 601.985012] Broke affinity for irq 373 >May 24 03:32:12 BXT-2 kernel: [ 601.986197] smpboot: CPU 3 is now offline >May 24 03:32:12 BXT-2 kernel: [ 601.997627] ACPI: Low-level resume complete >May 24 03:32:12 BXT-2 kernel: [ 601.998232] ACPI : EC: EC started >May 24 03:32:12 BXT-2 kernel: [ 601.998244] PM: Restoring platform NVS memory >May 24 03:32:12 BXT-2 kernel: [ 601.999952] Suspended for 15.356 seconds >May 24 03:32:12 BXT-2 kernel: [ 602.000470] Enabling non-boot CPUs ... >May 24 03:32:12 BXT-2 kernel: [ 602.000926] x86: Booting SMP configuration: >May 24 03:32:12 BXT-2 kernel: [ 602.000942] smpboot: Booting Node 0 Processor 1 APIC 0x2 >May 24 03:32:12 BXT-2 kernel: [ 602.012612] cache: parent cpu1 should not be sleeping >May 24 03:32:12 BXT-2 kernel: [ 602.015662] CPU1 is up >May 24 03:32:12 BXT-2 kernel: [ 602.015882] smpboot: Booting Node 0 Processor 2 APIC 0x4 >May 24 03:32:12 BXT-2 kernel: [ 602.024476] cache: parent cpu2 should not be sleeping >May 24 03:32:12 BXT-2 kernel: [ 602.027802] CPU2 is up >May 24 03:32:12 BXT-2 kernel: [ 602.028011] smpboot: Booting Node 0 Processor 3 APIC 0x6 >May 24 03:32:12 BXT-2 kernel: [ 602.036483] cache: parent cpu3 should not be sleeping >May 24 03:32:12 BXT-2 kernel: [ 602.040202] CPU3 is up >May 24 03:32:12 BXT-2 kernel: [ 602.046626] ACPI: Waking up from system sleep state S3 >May 24 03:32:12 BXT-2 kernel: [ 602.054720] ACPI : EC: interrupt unblocked >May 24 03:32:12 BXT-2 kernel: [ 602.054805] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI >May 24 03:32:12 BXT-2 kernel: [ 602.078509] PM: noirq resume of devices complete after 24.694 msecs >May 24 03:32:12 BXT-2 kernel: [ 602.079162] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.079266] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:32:12 BXT-2 kernel: [ 602.079334] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.079467] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 03:32:12 BXT-2 kernel: [ 602.079879] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.079959] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:32:12 BXT-2 kernel: [ 602.080056] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.080133] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:32:12 BXT-2 kernel: [ 602.082523] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.084633] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.084699] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.084767] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.084849] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.084920] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:32:12 BXT-2 kernel: [ 602.086816] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.093950] PM: early resume of devices complete after 15.083 msecs >May 24 03:32:12 BXT-2 kernel: [ 602.094710] ACPI : EC: event unblocked >May 24 03:32:12 BXT-2 kernel: [ 602.095458] r8169 0000:03:00.0: System wakeup disabled by ACPI >May 24 03:32:12 BXT-2 kernel: [ 602.095633] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 03:32:12 BXT-2 kernel: [ 602.104922] sd 0:0:0:0: [sda] Starting disk >May 24 03:32:12 BXT-2 kernel: [ 602.107864] r8169 0000:03:00.0 enp3s0: link down >May 24 03:32:12 BXT-2 kernel: [ 602.204823] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:32:12 BXT-2 kernel: [ 602.204921] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:32:12 BXT-2 kernel: [ 602.204963] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:32:12 BXT-2 kernel: [ 602.205068] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:32:12 BXT-2 kernel: [ 602.205215] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38 >May 24 03:32:12 BXT-2 kernel: [ 602.205702] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:32:12 BXT-2 kernel: [ 602.205765] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:32:12 BXT-2 kernel: [ 602.205871] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:32:12 BXT-2 kernel: [ 602.205979] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:32:12 BXT-2 kernel: [ 602.206086] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:32:12 BXT-2 kernel: [ 602.206998] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.207100] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:32:12 BXT-2 kernel: [ 602.207288] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.207331] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:32:12 BXT-2 kernel: [ 602.207382] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.207424] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:32:12 BXT-2 kernel: [ 602.207474] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.207516] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:32:12 BXT-2 kernel: [ 602.207563] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:32:12 BXT-2 kernel: [ 602.207608] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:32:12 BXT-2 kernel: [ 602.207652] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:32:12 BXT-2 kernel: [ 602.207699] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.207741] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.207784] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:32:12 BXT-2 kernel: [ 602.207826] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:32:12 BXT-2 kernel: [ 602.207871] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.207913] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.207955] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:32:12 BXT-2 kernel: [ 602.207997] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:32:12 BXT-2 kernel: [ 602.208079] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:32:12 BXT-2 kernel: [ 602.208127] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:32:12 BXT-2 kernel: [ 602.208179] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:32:12 BXT-2 kernel: [ 602.208245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.208287] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.208328] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:12 BXT-2 kernel: [ 602.208337] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.208378] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:12 BXT-2 kernel: [ 602.208383] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.208425] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.208469] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:32:12 BXT-2 kernel: [ 602.208511] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.208552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:12 BXT-2 kernel: [ 602.208594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.208639] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.208680] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:12 BXT-2 kernel: [ 602.208725] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.208767] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.208811] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.208852] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.208897] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:32:12 BXT-2 kernel: [ 602.208938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.208979] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209020] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:12 BXT-2 kernel: [ 602.209025] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209066] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:12 BXT-2 kernel: [ 602.209071] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209113] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209154] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209214] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:12 BXT-2 kernel: [ 602.209296] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209339] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209380] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:12 BXT-2 kernel: [ 602.209422] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.209465] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.209509] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.209550] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.209594] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:32:12 BXT-2 kernel: [ 602.209636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209677] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209718] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:12 BXT-2 kernel: [ 602.209723] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209764] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:12 BXT-2 kernel: [ 602.209769] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209810] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.209852] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209893] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.209935] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:12 BXT-2 kernel: [ 602.209976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.210019] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:32:12 BXT-2 kernel: [ 602.210060] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:12 BXT-2 kernel: [ 602.210103] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.210147] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.210208] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.210415] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.210534] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:32:12 BXT-2 kernel: [ 602.210574] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.210741] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.210781] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.210824] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:12 BXT-2 kernel: [ 602.210863] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:12 BXT-2 kernel: [ 602.211423] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.211502] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:12 BXT-2 kernel: [ 602.211544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:12 BXT-2 kernel: [ 602.211587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:12 BXT-2 kernel: [ 602.211630] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:12 BXT-2 kernel: [ 602.211671] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:12 BXT-2 kernel: [ 602.211715] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.211757] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:12 BXT-2 kernel: [ 602.211798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.211840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:12 BXT-2 kernel: [ 602.211882] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.211923] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:12 BXT-2 kernel: [ 602.211928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.211971] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:12 BXT-2 kernel: [ 602.211976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.212019] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.212060] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:12 BXT-2 kernel: [ 602.212102] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:12 BXT-2 kernel: [ 602.212144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:12 BXT-2 kernel: [ 602.212200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.212244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:12 BXT-2 kernel: [ 602.212285] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:12 BXT-2 kernel: [ 602.212326] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.212368] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.212409] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.212451] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.212497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.212550] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.212594] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.212756] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.212792] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.213079] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.213132] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.213171] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.213330] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.214802] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.215128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.215173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:12 BXT-2 kernel: [ 602.215266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.215310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.215354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.215398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:12 BXT-2 kernel: [ 602.215442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.215484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.215527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.215571] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.215622] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:12 BXT-2 kernel: [ 602.215667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:12 BXT-2 kernel: [ 602.215711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.215788] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:12 BXT-2 kernel: [ 602.215832] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.218450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.218495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.218540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:12 BXT-2 kernel: [ 602.219317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.219357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.220088] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:12 BXT-2 kernel: [ 602.220130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:12 BXT-2 kernel: [ 602.221236] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:12 BXT-2 kernel: [ 602.223347] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:12 BXT-2 kernel: [ 602.224411] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.241374] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.241455] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.241672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.241813] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:12 BXT-2 kernel: [ 602.241894] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:12 BXT-2 kernel: [ 602.242200] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:32:12 BXT-2 kernel: [ 602.242531] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.242637] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:32:12 BXT-2 kernel: [ 602.242723] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.244138] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:32:12 BXT-2 kernel: [ 602.245207] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:12 BXT-2 kernel: [ 602.245406] PM: resume of devices complete after 151.445 msecs >May 24 03:32:12 BXT-2 kernel: [ 602.247419] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:12 BXT-2 kernel: [ 602.247489] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:12 BXT-2 kernel: [ 602.247555] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:12 BXT-2 kernel: [ 602.247621] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:12 BXT-2 kernel: [ 602.248095] PM: Finishing wakeup. >May 24 03:32:12 BXT-2 kernel: [ 602.248102] OOM killer enabled. >May 24 03:32:12 BXT-2 kernel: [ 602.248106] Restarting tasks ... >May 24 03:32:12 BXT-2 kernel: [ 602.248192] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:12 BXT-2 kernel: [ 602.248354] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:12 BXT-2 kernel: [ 602.252634] done. >May 24 03:32:12 BXT-2 kernel: [ 602.253530] video LNXVIDEO:00: Restoring backlight state >May 24 03:32:12 BXT-2 kernel: [ 602.267095] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:32:12 BXT-2 NetworkManager[807]: <info> [1495614732.2574] device (enp3s0): link disconnected >May 24 03:32:12 BXT-2 kernel: [ 602.280684] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:12 BXT-2 kernel: [ 602.299728] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.299797] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.324535] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:12 BXT-2 kernel: [ 602.324916] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:12 BXT-2 kernel: [ 602.391522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.391659] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.410014] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:12 BXT-2 kernel: [ 602.410127] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.410269] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.410595] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.410640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:12 BXT-2 kernel: [ 602.410683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.410725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.410768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.410811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:12 BXT-2 kernel: [ 602.410858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.410900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.410943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.410986] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.411033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:12 BXT-2 kernel: [ 602.411078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:12 BXT-2 kernel: [ 602.411122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.411225] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.411270] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.411324] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.411385] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.411437] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.411479] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:12 BXT-2 kernel: [ 602.411519] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:12 BXT-2 kernel: [ 602.412066] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.413087] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:12 BXT-2 kernel: [ 602.417892] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:32:12 BXT-2 kernel: [ 602.428990] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.429051] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.429178] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:12 BXT-2 kernel: [ 602.429522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:12 BXT-2 kernel: [ 602.429568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:12 BXT-2 kernel: [ 602.429612] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:12 BXT-2 kernel: [ 602.429654] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:12 BXT-2 kernel: [ 602.429698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.429743] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:12 BXT-2 kernel: [ 602.429785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.429828] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:12 BXT-2 kernel: [ 602.429871] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.429912] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:12 BXT-2 kernel: [ 602.429921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.429962] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:12 BXT-2 kernel: [ 602.429968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.430011] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.430054] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:12 BXT-2 kernel: [ 602.430096] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:12 BXT-2 kernel: [ 602.430139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:12 BXT-2 kernel: [ 602.430215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.430260] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:12 BXT-2 kernel: [ 602.430302] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:12 BXT-2 kernel: [ 602.430345] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.430388] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.430430] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.430473] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.430573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.430632] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.430722] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.431354] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.431393] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.431683] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.431738] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.431779] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.431836] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.432255] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.432580] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.432624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:12 BXT-2 kernel: [ 602.432667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.432709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.432752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.432795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:12 BXT-2 kernel: [ 602.432838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.432880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.432922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.432965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:12 BXT-2 kernel: [ 602.433012] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:12 BXT-2 kernel: [ 602.433056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.433129] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:12 BXT-2 kernel: [ 602.433172] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.434735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.434778] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.434822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:12 BXT-2 kernel: [ 602.435601] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.435644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.436374] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:12 BXT-2 kernel: [ 602.436417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:12 BXT-2 kernel: [ 602.437489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:12 BXT-2 kernel: [ 602.439249] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:12 BXT-2 kernel: [ 602.440331] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.457183] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.457270] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.457442] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.540669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.540799] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.558564] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:12 BXT-2 kernel: [ 602.558676] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.558766] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.559074] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.559118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:12 BXT-2 kernel: [ 602.559161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.559258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.559301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.559344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:12 BXT-2 kernel: [ 602.559393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.559436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.559479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.559523] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.559571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:12 BXT-2 kernel: [ 602.559616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:12 BXT-2 kernel: [ 602.559662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.559721] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.559765] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.559819] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.559882] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.559934] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.559977] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:12 BXT-2 kernel: [ 602.560016] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:12 BXT-2 kernel: [ 602.560607] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.564664] [drm] RC6 on >May 24 03:32:12 BXT-2 kernel: [ 602.571204] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:32:12 BXT-2 kernel: [ 602.592025] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:12 BXT-2 kernel: [ 602.592068] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:12 BXT-2 kernel: [ 602.592112] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:12 BXT-2 kernel: [ 602.592154] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:12 BXT-2 kernel: [ 602.592305] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:12 BXT-2 kernel: [ 602.592348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.592391] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:12 BXT-2 kernel: [ 602.592432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.592474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:12 BXT-2 kernel: [ 602.592515] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.592556] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:12 BXT-2 kernel: [ 602.592563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.592604] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:12 BXT-2 kernel: [ 602.592608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.592650] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.592692] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:12 BXT-2 kernel: [ 602.592733] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:12 BXT-2 kernel: [ 602.592775] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:12 BXT-2 kernel: [ 602.592815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.592861] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:12 BXT-2 kernel: [ 602.592902] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:12 BXT-2 kernel: [ 602.592943] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.592985] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.593028] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.593069] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:12 BXT-2 kernel: [ 602.593114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.593164] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.593234] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.593355] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:12 BXT-2 kernel: [ 602.593391] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:12 BXT-2 kernel: [ 602.593680] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:12 BXT-2 kernel: [ 602.593734] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.593773] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:12 BXT-2 kernel: [ 602.593828] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:12 BXT-2 kernel: [ 602.594115] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.594429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:12 BXT-2 kernel: [ 602.594473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:12 BXT-2 kernel: [ 602.594515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.594557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.594598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.594641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:12 BXT-2 kernel: [ 602.594682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:12 BXT-2 kernel: [ 602.594723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:12 BXT-2 kernel: [ 602.594765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:12 BXT-2 kernel: [ 602.594806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:12 BXT-2 kernel: [ 602.594851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:12 BXT-2 kernel: [ 602.594895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.594967] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:12 BXT-2 kernel: [ 602.595009] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.596461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.596502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.596545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:12 BXT-2 kernel: [ 602.597319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.597359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:12 BXT-2 kernel: [ 602.598089] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:12 BXT-2 kernel: [ 602.598130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:12 BXT-2 kernel: [ 602.599244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:12 BXT-2 kernel: [ 602.601325] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:12 BXT-2 kernel: [ 602.602455] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:12 BXT-2 kernel: [ 602.612185] ata1.00: configured for UDMA/133 >May 24 03:32:12 BXT-2 kernel: [ 602.619337] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.619391] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.619569] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:12 BXT-2 kernel: [ 602.619921] Console: switching to colour frame buffer device 240x67 >May 24 03:32:12 BXT-2 kernel: [ 602.649822] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x1000181a, pins 0x00000020 >May 24 03:32:12 BXT-2 kernel: [ 602.649873] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long >May 24 03:32:12 BXT-2 kernel: [ 602.649917] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0 >May 24 03:32:12 BXT-2 kernel: [ 602.650045] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long >May 24 03:32:12 BXT-2 kernel: [ 602.651150] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions >May 24 03:32:12 BXT-2 kernel: [ 602.651358] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event. >May 24 03:32:12 BXT-2 kernel: [ 602.651557] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.653671] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:12 BXT-2 kernel: [ 602.852933] Console: switching to colour dummy device 80x25 >May 24 03:32:12 BXT-2 kernel: [ 602.873771] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.873832] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.874383] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:12 BXT-2 kernel: [ 602.874740] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:32:12 BXT-2 kernel: [ 602.874776] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.874830] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.875354] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:12 BXT-2 kernel: [ 602.876236] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:12 BXT-2 kernel: [ 602.876282] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:12 BXT-2 kernel: [ 602.876326] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:12 BXT-2 kernel: [ 602.876368] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:12 BXT-2 kernel: [ 602.876864] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:12 BXT-2 kernel: [ 602.876907] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:12 BXT-2 kernel: [ 602.881807] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:12 BXT-2 kernel: [ 602.881871] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:12 BXT-2 kernel: [ 602.881879] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881884] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881889] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881894] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881899] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881904] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881909] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:12 BXT-2 kernel: [ 602.881915] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881920] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.881925] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:12 BXT-2 kernel: [ 602.881930] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:12 BXT-2 kernel: [ 602.881935] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:12 BXT-2 kernel: [ 602.888742] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.888801] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:12 BXT-2 kernel: [ 602.889339] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:12 BXT-2 kernel: [ 602.889690] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:32:12 BXT-2 kernel: [ 602.890054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.890107] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.890629] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:12 BXT-2 kernel: [ 602.891519] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:12 BXT-2 kernel: [ 602.891564] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:12 BXT-2 kernel: [ 602.891606] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:12 BXT-2 kernel: [ 602.891648] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:12 BXT-2 kernel: [ 602.892125] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:12 BXT-2 kernel: [ 602.892167] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:12 BXT-2 kernel: [ 602.896908] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:12 BXT-2 kernel: [ 602.896973] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:12 BXT-2 kernel: [ 602.896980] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.896985] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.896990] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.896995] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.897000] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.897006] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.897011] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:12 BXT-2 kernel: [ 602.897016] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.897021] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:12 BXT-2 kernel: [ 602.897026] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:12 BXT-2 kernel: [ 602.897031] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:12 BXT-2 kernel: [ 602.897036] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:12 BXT-2 kernel: [ 602.898246] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:12 BXT-2 kernel: [ 602.914042] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:12 BXT-2 kernel: [ 602.914104] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:12 BXT-2 kernel: [ 602.935920] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:12 BXT-2 kernel: [ 602.936460] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:13 BXT-2 kernel: [ 603.002907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.003044] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.020563] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.020679] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.020774] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.021088] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.021133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.021176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.021267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.021311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.021356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.021405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.021448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.021493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.021537] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.021584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.021629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.021676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.021734] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.021777] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.021831] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.021893] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.021945] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.021989] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:13 BXT-2 kernel: [ 603.022028] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:13 BXT-2 kernel: [ 603.022609] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.023644] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:13 BXT-2 kernel: [ 603.028497] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x10001819, pins 0x00000020 >May 24 03:32:13 BXT-2 kernel: [ 603.028548] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short >May 24 03:32:13 BXT-2 kernel: [ 603.028650] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short >May 24 03:32:13 BXT-2 kernel: [ 603.028696] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.028733] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.029076] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:13 BXT-2 kernel: [ 603.029126] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.029166] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.029394] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.032419] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:13 BXT-2 kernel: [ 603.033474] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.033521] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.033576] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.033617] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.033661] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:13 BXT-2 kernel: [ 603.033700] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:13 BXT-2 kernel: [ 603.035110] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.035229] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions >May 24 03:32:13 BXT-2 kernel: [ 603.035279] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event. >May 24 03:32:13 BXT-2 kernel: [ 603.035328] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:13 BXT-2 kernel: [ 603.035460] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.035592] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.035925] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:13 BXT-2 kernel: [ 603.035977] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.036018] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.036271] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.039856] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:13 BXT-2 kernel: [ 603.041077] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:13 BXT-2 kernel: [ 603.041124] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.041167] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.041741] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.042647] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:13 BXT-2 kernel: [ 603.043046] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:13 BXT-2 kernel: [ 603.046564] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.046736] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.050341] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.052651] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.054322] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.056139] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.057469] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.058827] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.060093] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.061345] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.062830] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.064216] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.065707] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.067108] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.068489] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.069869] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.071259] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.072775] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.074075] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.075330] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.076582] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.077893] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.079281] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.080691] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.082162] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.083545] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.084955] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.086343] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.087727] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.089175] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.089962] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:13 BXT-2 kernel: [ 603.090443] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.090489] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.090638] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.090680] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.090724] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:13 BXT-2 kernel: [ 603.090764] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:13 BXT-2 kernel: [ 603.091385] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.091638] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:52:DP-1] status updated from disconnected to connected >May 24 03:32:13 BXT-2 kernel: [ 603.091838] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.091973] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:13 BXT-2 kernel: [ 603.092017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:13 BXT-2 kernel: [ 603.092062] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:13 BXT-2 kernel: [ 603.092107] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:13 BXT-2 kernel: [ 603.092149] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.092627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.092804] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:13 BXT-2 kernel: [ 603.092848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.092892] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:13 BXT-2 kernel: [ 603.092934] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.092976] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:13 BXT-2 kernel: [ 603.092985] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.093027] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:13 BXT-2 kernel: [ 603.093033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.093077] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.093119] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:13 BXT-2 kernel: [ 603.093162] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:13 BXT-2 kernel: [ 603.093819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:13 BXT-2 kernel: [ 603.093864] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.093910] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:13 BXT-2 kernel: [ 603.093952] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:13 BXT-2 kernel: [ 603.093996] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.094038] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.094082] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.094124] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.094707] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.094765] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.094809] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.095694] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.095735] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.096031] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:13 BXT-2 kernel: [ 603.096087] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.096127] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.096576] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.096849] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.097167] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.097557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.097602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.097644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.097687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.097731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.097773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.097816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.097859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.097902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.097952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.097997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.098073] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.098117] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.100284] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.100331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.100376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:13 BXT-2 kernel: [ 603.101380] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:13 BXT-2 kernel: [ 603.101430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:13 BXT-2 kernel: [ 603.102500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:13 BXT-2 kernel: [ 603.104231] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:13 BXT-2 kernel: [ 603.105267] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.122154] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.122256] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.122427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.205744] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.205881] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.223666] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.223780] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.223871] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.224272] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.224318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.224361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.224404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.224447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.224491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.224539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.224582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.224625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.224669] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.224716] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.224762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.224807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.224875] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.224918] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.224972] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.225035] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.225087] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.225130] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:13 BXT-2 kernel: [ 603.225169] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:13 BXT-2 kernel: [ 603.225752] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.234436] [drm] GPU HANG: ecode 9:0:0xffdffffe, reason: Manually setting wedged to 18446744073709551615, action: reset >May 24 03:32:13 BXT-2 kernel: [ 603.234598] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. >May 24 03:32:13 BXT-2 kernel: [ 603.234602] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel >May 24 03:32:13 BXT-2 kernel: [ 603.234605] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. >May 24 03:32:13 BXT-2 kernel: [ 603.234607] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. >May 24 03:32:13 BXT-2 kernel: [ 603.234610] [drm] GPU crash dump saved to /sys/class/drm/card0/error >May 24 03:32:13 BXT-2 kernel: [ 603.234974] [drm:i915_reset_and_wakeup [i915]] resetting chip >May 24 03:32:13 BXT-2 kernel: [ 603.235296] drm/i915: Resetting chip after gpu hang >May 24 03:32:13 BXT-2 kernel: [ 603.240424] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:32:13 BXT-2 kernel: [ 603.240495] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:32:13 BXT-2 kernel: [ 603.240619] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:32:13 BXT-2 kernel: [ 603.240744] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:32:13 BXT-2 kernel: [ 603.240867] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:32:13 BXT-2 kernel: [ 603.250626] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:13 BXT-2 kernel: [ 603.267401] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.267463] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.267592] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:13 BXT-2 kernel: [ 603.267636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:13 BXT-2 kernel: [ 603.267681] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:13 BXT-2 kernel: [ 603.267725] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:13 BXT-2 kernel: [ 603.267767] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.267811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.267854] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:13 BXT-2 kernel: [ 603.267897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.267940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:13 BXT-2 kernel: [ 603.267982] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.268024] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:13 BXT-2 kernel: [ 603.268031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.268072] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:13 BXT-2 kernel: [ 603.268078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.268121] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.268164] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:13 BXT-2 kernel: [ 603.268276] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:13 BXT-2 kernel: [ 603.268320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:13 BXT-2 kernel: [ 603.268364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.268411] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:13 BXT-2 kernel: [ 603.268454] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:13 BXT-2 kernel: [ 603.268500] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.268545] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.268590] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.268635] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.268699] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.268751] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.268797] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.269412] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.269451] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.269741] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:13 BXT-2 kernel: [ 603.269795] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.269836] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.269892] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.270248] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.270585] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.270630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.270674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.270716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.270759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.270802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.270844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.270887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.270930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.270973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.271020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.271065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.271139] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.271220] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.272704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.272750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.272809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:13 BXT-2 kernel: [ 603.273650] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:13 BXT-2 kernel: [ 603.273698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:13 BXT-2 kernel: [ 603.274776] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:13 BXT-2 kernel: [ 603.276876] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:13 BXT-2 kernel: [ 603.277945] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.294821] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.294876] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.295045] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.378407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.378540] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.396468] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.396581] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.396673] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.396999] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.397044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.397087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.397130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.397173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.397312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.397360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.397403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.397446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.397489] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.397536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.397582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.397628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.397688] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.397732] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.397786] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.397850] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.397904] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.397947] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:13 BXT-2 kernel: [ 603.397986] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:13 BXT-2 kernel: [ 603.398571] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.399569] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:13 BXT-2 kernel: [ 603.417032] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.417097] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.417277] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:13 BXT-2 kernel: [ 603.417321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:13 BXT-2 kernel: [ 603.417366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:13 BXT-2 kernel: [ 603.417409] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:13 BXT-2 kernel: [ 603.417451] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.417496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.417539] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:13 BXT-2 kernel: [ 603.417581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.417624] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:13 BXT-2 kernel: [ 603.417666] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.417708] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:13 BXT-2 kernel: [ 603.417715] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.417757] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:13 BXT-2 kernel: [ 603.417763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.417806] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.417848] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:13 BXT-2 kernel: [ 603.417891] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:13 BXT-2 kernel: [ 603.417933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:13 BXT-2 kernel: [ 603.417975] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.418019] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:13 BXT-2 kernel: [ 603.418061] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:13 BXT-2 kernel: [ 603.418104] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.418147] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.418211] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.418254] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.418317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.418370] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.418413] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.420136] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.420201] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.420498] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:13 BXT-2 kernel: [ 603.420556] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.420596] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.420652] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.420948] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.421274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.421319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.421363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.421406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.421449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.421493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.421536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.421580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.421624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.421668] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.421715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.421760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.421834] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.421878] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.423896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.423942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.423986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:13 BXT-2 kernel: [ 603.425254] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:13 BXT-2 kernel: [ 603.425302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:13 BXT-2 kernel: [ 603.426435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:13 BXT-2 kernel: [ 603.428262] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:13 BXT-2 kernel: [ 603.429357] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.446275] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.446332] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.446502] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.529794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.529924] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.547560] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.547673] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.547763] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.548081] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.548125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.548168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.548272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.548317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.548362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.548410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.548453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.548495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.548539] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.548586] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.548632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.548677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.548739] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.548782] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.548836] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.548899] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.548952] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.548996] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:13 BXT-2 kernel: [ 603.549034] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:13 BXT-2 kernel: [ 603.549621] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.573072] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:13 BXT-2 kernel: [ 603.573115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:13 BXT-2 kernel: [ 603.573159] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:13 BXT-2 kernel: [ 603.573259] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:13 BXT-2 kernel: [ 603.573300] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.573343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.573386] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:13 BXT-2 kernel: [ 603.573427] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.573469] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:13 BXT-2 kernel: [ 603.573510] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.573551] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:13 BXT-2 kernel: [ 603.573558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.573599] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:13 BXT-2 kernel: [ 603.573603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.573645] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.573686] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:13 BXT-2 kernel: [ 603.573728] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:13 BXT-2 kernel: [ 603.573769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:13 BXT-2 kernel: [ 603.573810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.573853] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:13 BXT-2 kernel: [ 603.573894] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:13 BXT-2 kernel: [ 603.573935] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.573977] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.574018] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.574059] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.574103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.574155] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.574213] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.574340] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:13 BXT-2 kernel: [ 603.574375] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:13 BXT-2 kernel: [ 603.574663] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:13 BXT-2 kernel: [ 603.574718] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.574757] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:13 BXT-2 kernel: [ 603.574812] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:13 BXT-2 kernel: [ 603.575066] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.575381] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.575423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.575465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.575506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.575548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.575589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.575630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.575672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.575713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.575754] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.575800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.575843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.575916] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.575957] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.577438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.577479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.577522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:13 BXT-2 kernel: [ 603.578280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.578320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.579036] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:13 BXT-2 kernel: [ 603.579077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:13 BXT-2 kernel: [ 603.580112] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:13 BXT-2 kernel: [ 603.582220] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:13 BXT-2 kernel: [ 603.583530] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.600407] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.600459] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.600634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.600987] Console: switching to colour frame buffer device 240x67 >May 24 03:32:13 BXT-2 kernel: [ 603.617104] [drm:drm_fb_helper_hotplug_event] >May 24 03:32:13 BXT-2 kernel: [ 603.617112] [drm:drm_setup_crtcs] >May 24 03:32:13 BXT-2 kernel: [ 603.617122] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:13 BXT-2 kernel: [ 603.617181] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:13 BXT-2 kernel: [ 603.617904] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:13 BXT-2 kernel: [ 603.619013] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:13 BXT-2 kernel: [ 603.619062] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.619105] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.619147] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.619822] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:13 BXT-2 kernel: [ 603.620435] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:13 BXT-2 kernel: [ 603.621299] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.622547] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.624196] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.625450] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.626704] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.627961] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.629369] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.630673] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.631920] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.633294] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.634683] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.636070] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.637457] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.638838] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.640223] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.641632] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.642944] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.644210] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.645459] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.646707] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.647963] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.649355] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.650732] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.652099] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.653486] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.654861] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.656361] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.657986] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.659858] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:13 BXT-2 kernel: [ 603.660678] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:13 BXT-2 kernel: [ 603.661743] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.661752] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:13 BXT-2 kernel: [ 603.661758] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:13 BXT-2 kernel: [ 603.661762] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:13 BXT-2 kernel: [ 603.661874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:13 BXT-2 kernel: [ 603.661881] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661886] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661891] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:13 BXT-2 kernel: [ 603.661896] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:13 BXT-2 kernel: [ 603.661901] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661907] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:13 BXT-2 kernel: [ 603.661912] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:13 BXT-2 kernel: [ 603.661917] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661922] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661927] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:13 BXT-2 kernel: [ 603.661932] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661938] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661943] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661948] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661953] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661958] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.661963] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661968] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.661974] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.661979] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.661984] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.661989] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.661994] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.661999] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.662004] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.662009] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.662015] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662020] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662025] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662030] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662035] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662040] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662045] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.662050] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:13 BXT-2 kernel: [ 603.662058] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.662118] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.663303] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:13 BXT-2 kernel: [ 603.664482] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:13 BXT-2 kernel: [ 603.664529] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.664572] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:13 BXT-2 kernel: [ 603.664614] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:13 BXT-2 kernel: [ 603.665150] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:13 BXT-2 kernel: [ 603.665580] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:13 BXT-2 kernel: [ 603.670446] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:13 BXT-2 kernel: [ 603.670516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:13 BXT-2 kernel: [ 603.670523] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670528] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670534] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670539] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670544] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670549] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670554] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.670559] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670565] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.670570] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.670575] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:13 BXT-2 kernel: [ 603.670580] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:13 BXT-2 kernel: [ 603.670604] [drm:drm_setup_crtcs] connector 52 enabled? yes >May 24 03:32:13 BXT-2 kernel: [ 603.670608] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:32:13 BXT-2 kernel: [ 603.670667] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:32:13 BXT-2 kernel: [ 603.670677] [drm:drm_setup_crtcs] looking for cmdline mode on connector 52 >May 24 03:32:13 BXT-2 kernel: [ 603.670681] [drm:drm_setup_crtcs] looking for preferred mode on connector 52 0 >May 24 03:32:13 BXT-2 kernel: [ 603.670685] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:32:13 BXT-2 kernel: [ 603.670689] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:32:13 BXT-2 kernel: [ 603.670692] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:32:13 BXT-2 kernel: [ 603.670696] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:32:13 BXT-2 kernel: [ 603.670700] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:32:13 BXT-2 kernel: [ 603.670758] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:32:13 BXT-2 kernel: [ 603.670769] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 43 (0,0) >May 24 03:32:13 BXT-2 kernel: [ 603.671021] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:13 BXT-2 kernel: [ 603.671065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:13 BXT-2 kernel: [ 603.671109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:13 BXT-2 kernel: [ 603.671152] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:13 BXT-2 kernel: [ 603.671291] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:13 BXT-2 kernel: [ 603.671335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.671381] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:13 BXT-2 kernel: [ 603.671425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.671468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:13 BXT-2 kernel: [ 603.671511] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.671552] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:13 BXT-2 kernel: [ 603.671560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.671602] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:13 BXT-2 kernel: [ 603.671607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.671651] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.671694] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:13 BXT-2 kernel: [ 603.671736] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:13 BXT-2 kernel: [ 603.671779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:13 BXT-2 kernel: [ 603.671821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.671865] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:13 BXT-2 kernel: [ 603.671907] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:13 BXT-2 kernel: [ 603.671952] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:32:13 BXT-2 kernel: [ 603.671995] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:32:13 BXT-2 kernel: [ 603.672038] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.672080] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.672123] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.672172] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:13 BXT-2 kernel: [ 603.672251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:13 BXT-2 kernel: [ 603.672297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:13 BXT-2 kernel: [ 603.672343] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:13 BXT-2 kernel: [ 603.672387] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:13 BXT-2 kernel: [ 603.672433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.672478] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:13 BXT-2 kernel: [ 603.672523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.672568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:13 BXT-2 kernel: [ 603.672613] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.672658] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:13 BXT-2 kernel: [ 603.672667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.672711] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:13 BXT-2 kernel: [ 603.672717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.672760] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:13 BXT-2 kernel: [ 603.672804] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:13 BXT-2 kernel: [ 603.672849] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:13 BXT-2 kernel: [ 603.672891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:13 BXT-2 kernel: [ 603.672933] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:13 BXT-2 kernel: [ 603.672977] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:13 BXT-2 kernel: [ 603.673019] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:13 BXT-2 kernel: [ 603.673062] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.673105] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.673147] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.673229] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:13 BXT-2 kernel: [ 603.673279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:13 BXT-2 kernel: [ 603.673335] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.673378] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.673422] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.673465] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:13 BXT-2 kernel: [ 603.673756] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.685616] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.685788] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.685852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.685895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.685938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.685980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.686023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:13 BXT-2 kernel: [ 603.686065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:13 BXT-2 kernel: [ 603.686179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:13 BXT-2 kernel: [ 603.686265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:13 BXT-2 kernel: [ 603.686310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:13 BXT-2 kernel: [ 603.686357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.686404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.686478] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:13 BXT-2 kernel: [ 603.686521] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.688577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.688624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.688668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:13 BXT-2 kernel: [ 603.707712] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:13 BXT-2 kernel: [ 603.707760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:13 BXT-2 kernel: [ 603.726377] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:13 BXT-2 kernel: [ 603.728019] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:13 BXT-2 kernel: [ 603.729033] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:13 BXT-2 kernel: [ 603.729098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:13 BXT-2 kernel: [ 603.729141] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:13 BXT-2 kernel: [ 603.729321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:13 BXT-2 kernel: [ 603.745928] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:13 BXT-2 kernel: [ 603.745988] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.747831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.747877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.747922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:13 BXT-2 kernel: [ 603.748703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.748746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:13 BXT-2 kernel: [ 603.749516] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:13 BXT-2 kernel: [ 603.749561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:13 BXT-2 kernel: [ 603.750655] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:13 BXT-2 kernel: [ 603.752237] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:13 BXT-2 kernel: [ 603.753342] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:13 BXT-2 kernel: [ 603.770232] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:13 BXT-2 kernel: [ 603.770300] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:13 BXT-2 kernel: [ 603.770480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:13 BXT-2 kernel: [ 603.770644] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:13 BXT-2 kernel: [ 603.770695] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:13 BXT-2 kernel: [ 603.770858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:13 BXT-2 kernel: [ 603.986023] Console: switching to colour dummy device 80x25 >May 24 03:32:14 BXT-2 kernel: [ 604.006725] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.006792] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.007832] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:14 BXT-2 kernel: [ 604.008924] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:14 BXT-2 kernel: [ 604.008974] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.009016] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.009059] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.009618] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:14 BXT-2 kernel: [ 604.010013] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:14 BXT-2 kernel: [ 604.010900] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.012142] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.013493] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.014744] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.015998] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.017251] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.018506] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.019767] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.021033] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.022440] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.023823] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.025199] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.026569] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.027935] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.029338] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.030967] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.032355] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.033836] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.035108] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.036375] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.037833] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.039245] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.040832] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.042216] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.043811] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.045535] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.047304] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.048691] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.050065] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.050858] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:14 BXT-2 kernel: [ 604.051599] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.051605] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:14 BXT-2 kernel: [ 604.051611] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:14 BXT-2 kernel: [ 604.051615] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:14 BXT-2 kernel: [ 604.051855] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:14 BXT-2 kernel: [ 604.051862] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051867] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051872] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:14 BXT-2 kernel: [ 604.051877] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:14 BXT-2 kernel: [ 604.051882] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051887] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:14 BXT-2 kernel: [ 604.051892] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:14 BXT-2 kernel: [ 604.051897] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051902] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051907] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:14 BXT-2 kernel: [ 604.051912] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051917] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051922] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051928] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051933] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051938] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051943] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051948] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051953] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051958] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051963] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051968] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051973] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051978] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051983] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051988] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.051993] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.051998] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.052003] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.052008] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.052013] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.052018] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.052024] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.052029] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:14 BXT-2 kernel: [ 604.052114] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.052174] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.052847] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:14 BXT-2 kernel: [ 604.053785] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:14 BXT-2 kernel: [ 604.053831] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.053874] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:14 BXT-2 kernel: [ 604.053917] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:14 BXT-2 kernel: [ 604.054422] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:14 BXT-2 kernel: [ 604.054466] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:14 BXT-2 kernel: [ 604.059302] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:14 BXT-2 kernel: [ 604.059367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:14 BXT-2 kernel: [ 604.059374] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059379] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059384] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059389] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059394] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059399] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059404] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.059409] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059414] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.059419] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.059424] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.059429] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:14 BXT-2 kernel: [ 604.067229] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.067296] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.067836] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:14 BXT-2 kernel: [ 604.068900] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:14 BXT-2 kernel: [ 604.068946] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.068988] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.069030] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.069622] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:14 BXT-2 kernel: [ 604.070014] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:14 BXT-2 kernel: [ 604.071060] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.072334] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.073673] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.074915] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.076186] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.077461] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.078716] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.079975] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.081223] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.082694] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.084089] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.085485] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.086863] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.088250] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.089759] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.091179] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.092554] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.093882] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.095185] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.096451] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.097711] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.099111] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.100527] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.101979] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.103372] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.104774] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.106203] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.107587] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.109002] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:14 BXT-2 kernel: [ 604.109813] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:14 BXT-2 kernel: [ 604.110600] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.110607] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:14 BXT-2 kernel: [ 604.110612] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:14 BXT-2 kernel: [ 604.110617] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:14 BXT-2 kernel: [ 604.110844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:14 BXT-2 kernel: [ 604.110851] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110856] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110861] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:14 BXT-2 kernel: [ 604.110866] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:14 BXT-2 kernel: [ 604.110872] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110877] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:14 BXT-2 kernel: [ 604.110882] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:14 BXT-2 kernel: [ 604.110887] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110892] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110897] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:14 BXT-2 kernel: [ 604.110902] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110907] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110912] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110917] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110922] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110927] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110932] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110937] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110942] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110948] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110953] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110958] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110963] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110968] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110973] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110978] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.110983] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110988] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110993] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.110998] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.111003] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.111008] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.111013] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.111018] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:14 BXT-2 kernel: [ 604.111633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.111693] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.112996] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:14 BXT-2 kernel: [ 604.113980] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:14 BXT-2 kernel: [ 604.114026] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.114069] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:14 BXT-2 kernel: [ 604.114112] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:14 BXT-2 kernel: [ 604.114616] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:14 BXT-2 kernel: [ 604.114660] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:14 BXT-2 kernel: [ 604.119437] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:14 BXT-2 kernel: [ 604.119501] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:14 BXT-2 kernel: [ 604.119508] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119514] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119519] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119524] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119529] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119534] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119539] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.119544] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119549] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.119554] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.119559] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:14 BXT-2 kernel: [ 604.119564] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:14 BXT-2 kernel: [ 604.120839] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:14 BXT-2 kernel: [ 604.136308] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:14 BXT-2 kernel: [ 604.136464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.136667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:14 BXT-2 kernel: [ 604.136803] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:14 BXT-2 kernel: [ 604.136924] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:14 BXT-2 kernel: [ 604.146531] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:14 BXT-2 kernel: [ 604.146649] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.146738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.146786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.146829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.146872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.146915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.146958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.147001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.147044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.147087] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.147134] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.147180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.147303] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.153523] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:14 BXT-2 kernel: [ 604.153986] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.154036] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.154158] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:14 BXT-2 kernel: [ 604.154274] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:14 BXT-2 kernel: [ 604.154325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:14 BXT-2 kernel: [ 604.154369] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:14 BXT-2 kernel: [ 604.154411] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:14 BXT-2 kernel: [ 604.154456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.154501] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:14 BXT-2 kernel: [ 604.154545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.154589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:14 BXT-2 kernel: [ 604.154632] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.154675] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:14 BXT-2 kernel: [ 604.154684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.154726] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:14 BXT-2 kernel: [ 604.154733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.154777] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.154820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:14 BXT-2 kernel: [ 604.154864] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:14 BXT-2 kernel: [ 604.154907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:14 BXT-2 kernel: [ 604.154950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.154996] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:14 BXT-2 kernel: [ 604.155039] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:14 BXT-2 kernel: [ 604.155084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:32:14 BXT-2 kernel: [ 604.155128] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:32:14 BXT-2 kernel: [ 604.155172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.155253] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.155296] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.155342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.155396] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.155440] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.157372] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.170444] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.170556] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.170610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.170654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.170697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.170739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.170782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.170828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.170871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.170914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.170957] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.171004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.171049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.171093] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.171166] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.171258] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.173293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.173338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.173382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:14 BXT-2 kernel: [ 604.192499] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:14 BXT-2 kernel: [ 604.192547] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:14 BXT-2 kernel: [ 604.210811] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:14 BXT-2 kernel: [ 604.212914] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:14 BXT-2 kernel: [ 604.213942] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.214011] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.214053] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:14 BXT-2 kernel: [ 604.214142] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:14 BXT-2 kernel: [ 604.230813] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.230885] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.231056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.247394] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:14 BXT-2 kernel: [ 604.314520] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.314684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.314861] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:14 BXT-2 kernel: [ 604.315796] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.331551] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.331665] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.331754] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.332186] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.332278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.332327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.332373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.332415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.332459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.332502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.332544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.332587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.332630] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.332680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.332726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.332771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.332835] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.332879] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.332934] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.332995] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.333040] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.333084] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:14 BXT-2 kernel: [ 604.333122] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:14 BXT-2 kernel: [ 604.333704] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.334774] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:14 BXT-2 kernel: [ 604.353530] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.353599] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.353732] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:14 BXT-2 kernel: [ 604.353776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:14 BXT-2 kernel: [ 604.353822] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:14 BXT-2 kernel: [ 604.353866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:14 BXT-2 kernel: [ 604.353908] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:14 BXT-2 kernel: [ 604.353953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.353996] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:14 BXT-2 kernel: [ 604.354039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.354082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:14 BXT-2 kernel: [ 604.354124] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.354166] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:14 BXT-2 kernel: [ 604.354224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.354268] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:14 BXT-2 kernel: [ 604.354276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.354319] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.354362] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:14 BXT-2 kernel: [ 604.354405] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:14 BXT-2 kernel: [ 604.354448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:14 BXT-2 kernel: [ 604.354491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.354537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:14 BXT-2 kernel: [ 604.354580] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:14 BXT-2 kernel: [ 604.354626] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.354671] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.354714] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.354759] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.354824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.354879] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.354922] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.355661] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.355701] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.355996] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:14 BXT-2 kernel: [ 604.356051] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.356091] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.356148] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.356970] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.357464] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.357512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.357556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.357599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.357642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.357685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.357728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.357770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.357813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.357856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.357905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.357949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.358025] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.358068] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.360848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.360897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.360942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:14 BXT-2 kernel: [ 604.364552] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x10001819, pins 0x00000020 >May 24 03:32:14 BXT-2 kernel: [ 604.364599] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short >May 24 03:32:14 BXT-2 kernel: [ 604.364706] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short >May 24 03:32:14 BXT-2 kernel: [ 604.365344] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:14 BXT-2 kernel: [ 604.380257] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:14 BXT-2 kernel: [ 604.380305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:14 BXT-2 kernel: [ 604.398535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:14 BXT-2 kernel: [ 604.400633] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:14 BXT-2 kernel: [ 604.401700] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.401779] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.401822] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:14 BXT-2 kernel: [ 604.401877] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:14 BXT-2 kernel: [ 604.418612] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.418670] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.418843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.502109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.502302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.502357] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:14 BXT-2 kernel: [ 604.502446] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.520467] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.520582] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.520673] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.521003] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.521047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.521094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.521137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.521180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.521283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.521329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.521374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.521419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.521462] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.521513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.521558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.521603] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.521664] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.521708] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.521762] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.521824] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.521869] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.521912] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:14 BXT-2 kernel: [ 604.521950] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:14 BXT-2 kernel: [ 604.522579] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.525328] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:14 BXT-2 kernel: [ 604.541765] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.541829] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.541959] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:14 BXT-2 kernel: [ 604.542003] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:14 BXT-2 kernel: [ 604.542047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:14 BXT-2 kernel: [ 604.542091] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:14 BXT-2 kernel: [ 604.542133] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.542178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.542640] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:14 BXT-2 kernel: [ 604.542685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.542728] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:14 BXT-2 kernel: [ 604.542770] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.542812] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:14 BXT-2 kernel: [ 604.542823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.542864] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:14 BXT-2 kernel: [ 604.542870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.542913] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.542956] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:14 BXT-2 kernel: [ 604.542999] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:14 BXT-2 kernel: [ 604.543041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:14 BXT-2 kernel: [ 604.543083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.543128] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:14 BXT-2 kernel: [ 604.543170] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:14 BXT-2 kernel: [ 604.543818] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.543862] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.543905] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.543947] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.544016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.544071] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.544115] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.545012] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.545052] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.545515] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:14 BXT-2 kernel: [ 604.545965] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.546006] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.546063] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.546583] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.546907] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.546951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.546993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.547038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.547080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.547123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.547166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.547563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.547606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.547649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.547698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.547742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.547817] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.547860] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.549574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.549619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.549663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:14 BXT-2 kernel: [ 604.550994] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:14 BXT-2 kernel: [ 604.551040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:14 BXT-2 kernel: [ 604.554252] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:14 BXT-2 kernel: [ 604.556297] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:14 BXT-2 kernel: [ 604.557385] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.574313] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.574370] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.574541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.657799] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.657928] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.675464] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.675578] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.675668] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.675991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.676036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.676079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.676122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.676165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.676255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.676303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.676346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.676388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.676432] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.676480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.676525] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.676570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.676633] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.676676] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.676729] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.676791] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.676835] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.676879] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:14 BXT-2 kernel: [ 604.676918] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:14 BXT-2 kernel: [ 604.677528] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.679477] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:14 BXT-2 kernel: [ 604.697567] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.697632] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.697762] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:14 BXT-2 kernel: [ 604.697805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:14 BXT-2 kernel: [ 604.697850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:14 BXT-2 kernel: [ 604.697894] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:14 BXT-2 kernel: [ 604.697936] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.697980] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.698023] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:14 BXT-2 kernel: [ 604.698065] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.698108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:14 BXT-2 kernel: [ 604.698151] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.698266] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:14 BXT-2 kernel: [ 604.698274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.698316] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:14 BXT-2 kernel: [ 604.698322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.698365] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.698407] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:14 BXT-2 kernel: [ 604.698450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:14 BXT-2 kernel: [ 604.698492] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:14 BXT-2 kernel: [ 604.698535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.698579] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:14 BXT-2 kernel: [ 604.698621] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:14 BXT-2 kernel: [ 604.698664] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.698707] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.698750] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.698792] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.698858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.698911] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.698954] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.701153] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.701266] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.701556] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:14 BXT-2 kernel: [ 604.701611] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.701652] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.701709] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.701950] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.702522] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.702569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.702614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.702657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.702700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.702744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.702787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.702830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.702873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.702917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.702966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.703011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.703087] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.703130] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.704915] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.704961] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.705007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:14 BXT-2 kernel: [ 604.705985] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:14 BXT-2 kernel: [ 604.706029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:14 BXT-2 kernel: [ 604.707317] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:14 BXT-2 kernel: [ 604.709426] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:14 BXT-2 kernel: [ 604.710561] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.727477] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.727535] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.727706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.810948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.811077] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.828534] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.828649] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.828739] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.829069] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.829113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.829157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.829253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.829296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.829339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.829389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.829434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.829477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.829520] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.829568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.829616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.829661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.829725] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.829769] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.829823] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.829884] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.829929] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.829973] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:14 BXT-2 kernel: [ 604.830012] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:14 BXT-2 kernel: [ 604.830595] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.858269] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:14 BXT-2 kernel: [ 604.858324] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:14 BXT-2 kernel: [ 604.858376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:14 BXT-2 kernel: [ 604.858427] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:14 BXT-2 kernel: [ 604.858475] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:14 BXT-2 kernel: [ 604.858526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.858579] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:14 BXT-2 kernel: [ 604.858627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.858677] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:14 BXT-2 kernel: [ 604.858723] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.858763] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:14 BXT-2 kernel: [ 604.858771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.858813] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:14 BXT-2 kernel: [ 604.858818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.858866] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.858915] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:14 BXT-2 kernel: [ 604.858963] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:14 BXT-2 kernel: [ 604.859011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:14 BXT-2 kernel: [ 604.859060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.859111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:14 BXT-2 kernel: [ 604.859157] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:14 BXT-2 kernel: [ 604.859234] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.859283] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.859331] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.859376] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.859429] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:14 BXT-2 kernel: [ 604.859471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:14 BXT-2 kernel: [ 604.859515] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:14 BXT-2 kernel: [ 604.859557] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:14 BXT-2 kernel: [ 604.859598] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:14 BXT-2 kernel: [ 604.859641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.859684] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:14 BXT-2 kernel: [ 604.859726] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.859768] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:14 BXT-2 kernel: [ 604.859808] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.859849] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:14 BXT-2 kernel: [ 604.859857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.859897] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:14 BXT-2 kernel: [ 604.859902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.859944] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:14 BXT-2 kernel: [ 604.859985] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:14 BXT-2 kernel: [ 604.860027] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:14 BXT-2 kernel: [ 604.860068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:14 BXT-2 kernel: [ 604.860109] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:14 BXT-2 kernel: [ 604.860153] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:14 BXT-2 kernel: [ 604.860243] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:14 BXT-2 kernel: [ 604.860286] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.860329] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.860371] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.860412] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:14 BXT-2 kernel: [ 604.860460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.860515] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.860558] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:14 BXT-2 kernel: [ 604.860601] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.860643] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.860811] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:14 BXT-2 kernel: [ 604.860847] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:14 BXT-2 kernel: [ 604.861136] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:14 BXT-2 kernel: [ 604.861216] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.861255] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:14 BXT-2 kernel: [ 604.861310] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:14 BXT-2 kernel: [ 604.861623] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.861940] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:14 BXT-2 kernel: [ 604.861982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.862024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.862066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.862107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.862149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:14 BXT-2 kernel: [ 604.862216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:14 BXT-2 kernel: [ 604.862258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:14 BXT-2 kernel: [ 604.862299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:14 BXT-2 kernel: [ 604.862341] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:14 BXT-2 kernel: [ 604.862387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.862431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.862504] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:14 BXT-2 kernel: [ 604.862546] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.863980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.864021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.864064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:14 BXT-2 kernel: [ 604.883720] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:14 BXT-2 kernel: [ 604.883765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:14 BXT-2 kernel: [ 604.901805] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:14 BXT-2 kernel: [ 604.903980] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:14 BXT-2 kernel: [ 604.905198] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:14 BXT-2 kernel: [ 604.905359] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:14 BXT-2 kernel: [ 604.905402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:14 BXT-2 kernel: [ 604.905529] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:14 BXT-2 kernel: [ 604.906588] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:14 BXT-2 kernel: [ 604.906631] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.908155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.908282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.908331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:14 BXT-2 kernel: [ 604.909160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.909263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:14 BXT-2 kernel: [ 604.910036] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:14 BXT-2 kernel: [ 604.910079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:14 BXT-2 kernel: [ 604.911364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:14 BXT-2 kernel: [ 604.913247] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:14 BXT-2 kernel: [ 604.914461] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:14 BXT-2 kernel: [ 604.931420] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:14 BXT-2 kernel: [ 604.931473] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:14 BXT-2 kernel: [ 604.931650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:14 BXT-2 kernel: [ 604.931821] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:14 BXT-2 kernel: [ 604.931872] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:14 BXT-2 kernel: [ 604.932042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:14 BXT-2 kernel: [ 604.932455] Console: switching to colour frame buffer device 240x67 >May 24 03:32:15 BXT-2 kernel: [ 605.165984] Console: switching to colour dummy device 80x25 >May 24 03:32:15 BXT-2 kernel: [ 605.187697] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.187764] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.188545] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:15 BXT-2 kernel: [ 605.189438] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:15 BXT-2 kernel: [ 605.189484] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.189527] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.189569] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.190051] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:15 BXT-2 kernel: [ 605.190656] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:15 BXT-2 kernel: [ 605.191532] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.192849] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.194095] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.195355] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.196697] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.197947] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.199239] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.200498] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.201749] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.203137] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.204677] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.206269] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.207970] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.209441] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.210943] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.212366] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.213915] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.215248] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.216526] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.217986] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.219253] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.220896] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.222320] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.223960] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.225980] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.227365] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.229219] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.230640] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.232093] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.232885] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:15 BXT-2 kernel: [ 605.233617] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.233624] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:15 BXT-2 kernel: [ 605.233629] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:15 BXT-2 kernel: [ 605.233633] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:15 BXT-2 kernel: [ 605.233858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:15 BXT-2 kernel: [ 605.233865] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233871] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233876] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:15 BXT-2 kernel: [ 605.233881] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:15 BXT-2 kernel: [ 605.233886] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233891] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:15 BXT-2 kernel: [ 605.233896] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:15 BXT-2 kernel: [ 605.233901] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233906] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233911] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:15 BXT-2 kernel: [ 605.233916] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233921] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233926] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233931] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233937] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233942] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.233947] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233952] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.233957] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.233962] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.233967] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.233972] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.233977] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233982] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233987] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233992] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.233997] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234002] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234007] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234012] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234017] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234022] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234027] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.234032] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:15 BXT-2 kernel: [ 605.234121] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.234180] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.234879] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:15 BXT-2 kernel: [ 605.236125] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:15 BXT-2 kernel: [ 605.236173] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.236268] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:15 BXT-2 kernel: [ 605.236311] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:15 BXT-2 kernel: [ 605.236819] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:15 BXT-2 kernel: [ 605.236863] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:15 BXT-2 kernel: [ 605.241695] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:15 BXT-2 kernel: [ 605.241757] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:15 BXT-2 kernel: [ 605.241764] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241770] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241775] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241780] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241785] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241790] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241795] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.241800] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241805] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.241810] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.241815] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.241820] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:15 BXT-2 kernel: [ 605.248784] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.248853] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.249440] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:15 BXT-2 kernel: [ 605.250377] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:15 BXT-2 kernel: [ 605.250425] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.250467] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.250510] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.251025] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:15 BXT-2 kernel: [ 605.251559] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:15 BXT-2 kernel: [ 605.252529] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.253918] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.257719] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.258963] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.260228] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.261466] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.262716] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.263973] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.265515] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.266945] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.268341] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.269714] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.271091] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.272483] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.273894] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.275287] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.276977] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.278264] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.279524] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.280862] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.282122] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.283522] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.284946] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.286336] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.287723] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.289116] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.290520] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.291951] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.293342] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:15 BXT-2 kernel: [ 605.294199] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:15 BXT-2 kernel: [ 605.294936] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.294943] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:15 BXT-2 kernel: [ 605.294949] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:15 BXT-2 kernel: [ 605.294953] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:15 BXT-2 kernel: [ 605.295248] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:15 BXT-2 kernel: [ 605.295255] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295260] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295266] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:15 BXT-2 kernel: [ 605.295271] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:15 BXT-2 kernel: [ 605.295276] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295281] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:15 BXT-2 kernel: [ 605.295286] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:15 BXT-2 kernel: [ 605.295291] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295298] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295303] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:15 BXT-2 kernel: [ 605.295308] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295313] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295318] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295323] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295330] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295335] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295340] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295345] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295350] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295355] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295361] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295366] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295372] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295377] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295382] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295387] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.295393] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295398] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295403] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295408] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295413] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295418] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295423] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.295428] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:15 BXT-2 kernel: [ 605.295834] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.295894] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.296564] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:15 BXT-2 kernel: [ 605.297450] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:15 BXT-2 kernel: [ 605.297497] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.297541] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:15 BXT-2 kernel: [ 605.297583] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:15 BXT-2 kernel: [ 605.298082] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:15 BXT-2 kernel: [ 605.298125] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:15 BXT-2 kernel: [ 605.305842] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:15 BXT-2 kernel: [ 605.305906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:15 BXT-2 kernel: [ 605.305913] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305918] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305923] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305928] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305933] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305938] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305943] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.305948] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305953] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.305958] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.305964] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:15 BXT-2 kernel: [ 605.305969] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:15 BXT-2 kernel: [ 605.307932] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:15 BXT-2 kernel: [ 605.324145] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:15 BXT-2 kernel: [ 605.324316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.324502] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:15 BXT-2 kernel: [ 605.324557] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:15 BXT-2 kernel: [ 605.324649] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:15 BXT-2 kernel: [ 605.340609] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:15 BXT-2 kernel: [ 605.340721] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.340811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.340858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.340900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.340943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.340986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.341029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.341072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.341114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.341157] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.341722] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.341768] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.341813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.347975] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:15 BXT-2 kernel: [ 605.348637] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.348702] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.348880] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:15 BXT-2 kernel: [ 605.348943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:15 BXT-2 kernel: [ 605.348999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:15 BXT-2 kernel: [ 605.349054] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:15 BXT-2 kernel: [ 605.349107] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:15 BXT-2 kernel: [ 605.349160] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.349722] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:15 BXT-2 kernel: [ 605.349766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.349810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:15 BXT-2 kernel: [ 605.349852] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.349895] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:15 BXT-2 kernel: [ 605.349904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.349946] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:15 BXT-2 kernel: [ 605.349952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.349996] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.350039] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:15 BXT-2 kernel: [ 605.350082] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:15 BXT-2 kernel: [ 605.350126] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:15 BXT-2 kernel: [ 605.350169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.350811] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:15 BXT-2 kernel: [ 605.350855] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:15 BXT-2 kernel: [ 605.350903] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:32:15 BXT-2 kernel: [ 605.350949] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:32:15 BXT-2 kernel: [ 605.350994] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.351037] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.351080] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.351127] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.351182] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.351694] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.352618] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.366529] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.366757] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.366813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.366857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.366899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.366942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.366985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.367032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.367075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.367117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.367160] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.367269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.367319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.367366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.367440] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.367483] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.368905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.368947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.368993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:15 BXT-2 kernel: [ 605.387961] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:15 BXT-2 kernel: [ 605.388011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:15 BXT-2 kernel: [ 605.407206] r8169 0000:03:00.0 enp3s0: link up >May 24 03:32:15 BXT-2 kernel: [ 605.407476] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:15 BXT-2 NetworkManager[807]: <info> [1495614735.4088] device (enp3s0): link connected >May 24 03:32:15 BXT-2 kernel: [ 605.410815] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:15 BXT-2 kernel: [ 605.411833] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.411902] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.411945] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:15 BXT-2 kernel: [ 605.412001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:15 BXT-2 kernel: [ 605.428738] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.428807] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.428977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.445319] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:15 BXT-2 kernel: [ 605.512327] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.512456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.512511] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:15 BXT-2 kernel: [ 605.512604] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.530555] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.530669] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.530761] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.531079] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.531124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.531171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.531279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.531322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.531370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.531414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.531457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.531499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.531542] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.531590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.531636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.531681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.531743] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:15 BXT-2 kernel: [ 605.531788] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.531842] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.531903] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.531949] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:15 BXT-2 kernel: [ 605.531993] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:15 BXT-2 kernel: [ 605.532032] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:15 BXT-2 kernel: [ 605.532617] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:15 BXT-2 kernel: [ 605.533657] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:15 BXT-2 kernel: [ 605.554000] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.554063] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.554191] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:15 BXT-2 kernel: [ 605.554483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:15 BXT-2 kernel: [ 605.554529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:15 BXT-2 kernel: [ 605.554573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:15 BXT-2 kernel: [ 605.554615] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:15 BXT-2 kernel: [ 605.554659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.554704] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:15 BXT-2 kernel: [ 605.554746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.554789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:15 BXT-2 kernel: [ 605.554832] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.554873] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:15 BXT-2 kernel: [ 605.554881] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.554923] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:15 BXT-2 kernel: [ 605.554929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.554972] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.555015] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:15 BXT-2 kernel: [ 605.555057] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:15 BXT-2 kernel: [ 605.555100] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:15 BXT-2 kernel: [ 605.555142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.555887] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:15 BXT-2 kernel: [ 605.555930] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:15 BXT-2 kernel: [ 605.555973] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.556016] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.556058] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.556101] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.556171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.556558] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.556602] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.557334] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:15 BXT-2 kernel: [ 605.557373] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:15 BXT-2 kernel: [ 605.557662] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:15 BXT-2 kernel: [ 605.557715] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.557756] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.557812] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:15 BXT-2 kernel: [ 605.558096] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.558680] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.558725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.558768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.558811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.558853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.558897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.558939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.558982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.559024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.559067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.559115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.559160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.559705] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.559749] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.561177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.561258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.561302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:15 BXT-2 kernel: [ 605.580666] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:15 BXT-2 kernel: [ 605.580715] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:15 BXT-2 kernel: [ 605.599143] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:15 BXT-2 kernel: [ 605.601265] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:15 BXT-2 kernel: [ 605.602279] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.602344] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.602387] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:15 BXT-2 kernel: [ 605.602442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:15 BXT-2 kernel: [ 605.619142] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.619256] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.619428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.702689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.702808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.702863] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:15 BXT-2 kernel: [ 605.702949] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.720498] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.720610] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.720699] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.721016] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.721090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.721141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.721206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.721250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.721297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.721342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.721385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.721430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.721474] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:15 BXT-2 kernel: [ 605.721523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.721568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.721613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.721674] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:15 BXT-2 kernel: [ 605.721718] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.721771] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.721832] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.721878] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:15 BXT-2 kernel: [ 605.721922] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:15 BXT-2 kernel: [ 605.721960] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:15 BXT-2 kernel: [ 605.723130] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:15 BXT-2 kernel: [ 605.724751] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:15 BXT-2 kernel: [ 605.745118] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.745359] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.745485] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:15 BXT-2 kernel: [ 605.745529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:15 BXT-2 kernel: [ 605.745575] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:15 BXT-2 kernel: [ 605.745618] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:15 BXT-2 kernel: [ 605.745660] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.745705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.745748] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:15 BXT-2 kernel: [ 605.745790] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.745834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:15 BXT-2 kernel: [ 605.745876] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.745917] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:15 BXT-2 kernel: [ 605.745924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.745966] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:15 BXT-2 kernel: [ 605.745972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.746015] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.746057] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:15 BXT-2 kernel: [ 605.746100] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:15 BXT-2 kernel: [ 605.746142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:15 BXT-2 kernel: [ 605.746929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.746977] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:15 BXT-2 kernel: [ 605.747018] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:15 BXT-2 kernel: [ 605.747062] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.747105] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.747147] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.747530] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.747602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.747656] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.747699] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.748524] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:15 BXT-2 kernel: [ 605.748564] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:15 BXT-2 kernel: [ 605.748852] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:15 BXT-2 kernel: [ 605.748906] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.748946] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.749002] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:15 BXT-2 kernel: [ 605.749559] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.749884] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.749928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.749971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.750014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.750057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.750100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.750142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.750533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.750576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.750619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.750668] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.750712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.750786] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.750829] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.752553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.752597] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.752641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:15 BXT-2 kernel: [ 605.753425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.753469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.754370] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:15 BXT-2 kernel: [ 605.754414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:15 BXT-2 kernel: [ 605.755590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:15 BXT-2 kernel: [ 605.757687] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:15 BXT-2 kernel: [ 605.758716] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.775633] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.775690] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.775862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.859132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.859342] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.877497] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.877612] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.877703] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.878031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.878075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.878119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.878162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.878260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.878303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.878351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.878394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.878437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.878480] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.878528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.878573] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.878618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.878681] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:15 BXT-2 kernel: [ 605.878724] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.878778] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.878839] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.878883] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:15 BXT-2 kernel: [ 605.878926] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:15 BXT-2 kernel: [ 605.878965] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:15 BXT-2 kernel: [ 605.879591] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:15 BXT-2 kernel: [ 605.882379] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:15 BXT-2 kernel: [ 605.900556] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.900606] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.900736] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:15 BXT-2 kernel: [ 605.900779] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:15 BXT-2 kernel: [ 605.900824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:15 BXT-2 kernel: [ 605.900868] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:15 BXT-2 kernel: [ 605.900910] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:15 BXT-2 kernel: [ 605.900954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.900997] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:15 BXT-2 kernel: [ 605.901039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.901082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:15 BXT-2 kernel: [ 605.901125] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.901167] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:15 BXT-2 kernel: [ 605.901223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.901267] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:15 BXT-2 kernel: [ 605.901274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.901319] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:15 BXT-2 kernel: [ 605.901363] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:15 BXT-2 kernel: [ 605.901409] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:15 BXT-2 kernel: [ 605.901453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:15 BXT-2 kernel: [ 605.901496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:15 BXT-2 kernel: [ 605.901542] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:15 BXT-2 kernel: [ 605.901584] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:15 BXT-2 kernel: [ 605.901630] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.901673] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.901716] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.901759] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:15 BXT-2 kernel: [ 605.901820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.901873] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.901917] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.902544] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:15 BXT-2 kernel: [ 605.902584] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:15 BXT-2 kernel: [ 605.902873] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:15 BXT-2 kernel: [ 605.902927] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.902969] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:15 BXT-2 kernel: [ 605.903026] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:15 BXT-2 kernel: [ 605.903668] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.903992] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:15 BXT-2 kernel: [ 605.904035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:15 BXT-2 kernel: [ 605.904078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.904121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.904164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.904271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:15 BXT-2 kernel: [ 605.904314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:15 BXT-2 kernel: [ 605.904357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:15 BXT-2 kernel: [ 605.904403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:15 BXT-2 kernel: [ 605.904448] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:15 BXT-2 kernel: [ 605.904497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:15 BXT-2 kernel: [ 605.904543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.904853] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:15 BXT-2 kernel: [ 605.904896] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:15 BXT-2 kernel: [ 605.906465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.906510] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.906554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:15 BXT-2 kernel: [ 605.907491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.907534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:15 BXT-2 kernel: [ 605.908440] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:15 BXT-2 kernel: [ 605.908484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:15 BXT-2 kernel: [ 605.909653] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:15 BXT-2 kernel: [ 605.911758] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:15 BXT-2 kernel: [ 605.912816] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:15 BXT-2 kernel: [ 605.929703] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:15 BXT-2 kernel: [ 605.929761] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:15 BXT-2 kernel: [ 605.929932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.013265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.013406] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.031515] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.031628] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.031717] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.032046] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.032090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.032134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.032177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.032297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.032341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.032391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.032434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.032479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.032522] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.032570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.032617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.032663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.032726] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:16 BXT-2 kernel: [ 606.032769] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.032824] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.032887] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.032933] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:16 BXT-2 kernel: [ 606.032977] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:16 BXT-2 kernel: [ 606.033016] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:16 BXT-2 kernel: [ 606.033611] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:16 BXT-2 kernel: [ 606.062198] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:16 BXT-2 kernel: [ 606.062299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:16 BXT-2 kernel: [ 606.062343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:16 BXT-2 kernel: [ 606.062386] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:16 BXT-2 kernel: [ 606.062427] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:16 BXT-2 kernel: [ 606.062470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.062513] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:16 BXT-2 kernel: [ 606.062555] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.062596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:16 BXT-2 kernel: [ 606.062637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.062678] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:16 BXT-2 kernel: [ 606.062685] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.062726] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:16 BXT-2 kernel: [ 606.062731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.062772] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.062814] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:16 BXT-2 kernel: [ 606.062856] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:16 BXT-2 kernel: [ 606.062897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:16 BXT-2 kernel: [ 606.062938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.062982] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:16 BXT-2 kernel: [ 606.063022] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:16 BXT-2 kernel: [ 606.063064] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.063106] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.063147] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.063208] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.063255] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:16 BXT-2 kernel: [ 606.063296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:16 BXT-2 kernel: [ 606.063338] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:16 BXT-2 kernel: [ 606.063380] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:16 BXT-2 kernel: [ 606.063421] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.063463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.063504] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:16 BXT-2 kernel: [ 606.063545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.063587] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:16 BXT-2 kernel: [ 606.063628] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.063668] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:16 BXT-2 kernel: [ 606.063674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.063714] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:16 BXT-2 kernel: [ 606.063719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.063760] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.063801] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:16 BXT-2 kernel: [ 606.063843] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:16 BXT-2 kernel: [ 606.063884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:16 BXT-2 kernel: [ 606.063925] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.063967] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:16 BXT-2 kernel: [ 606.064008] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:16 BXT-2 kernel: [ 606.064049] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.064091] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.064132] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.064174] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.064615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.064668] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.064710] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:16 BXT-2 kernel: [ 606.064752] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.064794] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.064938] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:16 BXT-2 kernel: [ 606.064974] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:16 BXT-2 kernel: [ 606.065311] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:16 BXT-2 kernel: [ 606.065366] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.065405] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.065460] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:16 BXT-2 kernel: [ 606.065733] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.066064] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.066107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.066148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.066241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.066283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.066324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.066366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.066407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.066449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.066491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.066537] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.066581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.066655] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:16 BXT-2 kernel: [ 606.066697] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.068118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.068159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.068274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:16 BXT-2 kernel: [ 606.087460] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:16 BXT-2 kernel: [ 606.087504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:16 BXT-2 kernel: [ 606.105804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:16 BXT-2 kernel: [ 606.107905] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:16 BXT-2 kernel: [ 606.109077] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:16 BXT-2 kernel: [ 606.109147] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.109217] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:16 BXT-2 kernel: [ 606.109273] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:16 BXT-2 kernel: [ 606.109440] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.109482] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.110913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.110955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.110999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:16 BXT-2 kernel: [ 606.111786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.111827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.112569] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:16 BXT-2 kernel: [ 606.112611] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:16 BXT-2 kernel: [ 606.113669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:16 BXT-2 kernel: [ 606.115759] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:16 BXT-2 kernel: [ 606.116967] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.133850] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.133904] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:16 BXT-2 kernel: [ 606.134083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.134317] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.134369] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.134540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.134926] Console: switching to colour frame buffer device 240x67 >May 24 03:32:16 BXT-2 kernel: [ 606.367660] Console: switching to colour dummy device 80x25 >May 24 03:32:16 BXT-2 kernel: [ 606.389680] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.389746] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.390388] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:16 BXT-2 kernel: [ 606.391274] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:16 BXT-2 kernel: [ 606.391320] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.391362] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.391405] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.391907] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:16 BXT-2 kernel: [ 606.392319] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:16 BXT-2 kernel: [ 606.393405] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.395040] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.396322] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.397636] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.399254] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.400791] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.402257] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.403506] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.405165] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.406541] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.407993] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.409372] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.410829] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.412234] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.413920] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.415354] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.416884] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.418253] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.419545] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.421061] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.422346] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.423882] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.425293] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.426949] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.428428] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.429813] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.431196] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.432568] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.433927] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.434718] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:16 BXT-2 kernel: [ 606.435478] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.435484] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:16 BXT-2 kernel: [ 606.435490] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:16 BXT-2 kernel: [ 606.435494] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:16 BXT-2 kernel: [ 606.435718] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:16 BXT-2 kernel: [ 606.435725] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435730] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435736] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:16 BXT-2 kernel: [ 606.435741] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:16 BXT-2 kernel: [ 606.435746] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435751] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:16 BXT-2 kernel: [ 606.435756] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:16 BXT-2 kernel: [ 606.435761] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435766] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435771] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:16 BXT-2 kernel: [ 606.435776] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435781] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435786] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435791] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435796] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435802] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435807] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435812] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435817] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435822] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435827] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435832] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435837] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435842] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435847] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435852] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.435857] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435862] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435867] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435872] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435877] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435882] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435887] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.435892] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:16 BXT-2 kernel: [ 606.436238] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.436303] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.436833] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:16 BXT-2 kernel: [ 606.437718] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:16 BXT-2 kernel: [ 606.437763] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.437806] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:16 BXT-2 kernel: [ 606.437849] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:16 BXT-2 kernel: [ 606.438392] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:16 BXT-2 kernel: [ 606.438435] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:16 BXT-2 kernel: [ 606.443127] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:16 BXT-2 kernel: [ 606.443243] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:16 BXT-2 kernel: [ 606.443251] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443256] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443261] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443266] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443272] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443279] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443285] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.443290] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443295] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.443300] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.443306] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.443313] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:16 BXT-2 kernel: [ 606.450365] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.450435] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.450982] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:16 BXT-2 kernel: [ 606.451924] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:16 BXT-2 kernel: [ 606.451972] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.452015] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.452057] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.452630] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:16 BXT-2 kernel: [ 606.453037] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:16 BXT-2 kernel: [ 606.454002] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.455293] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.456646] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.458003] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.459281] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.460525] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.461808] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.463056] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.464315] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.465697] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.467072] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.468455] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.469835] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.471227] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.472662] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.474042] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.475408] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.477444] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.478823] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.480080] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.481338] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.482720] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.484095] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.485476] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.487240] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.488762] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.490198] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.491824] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.493291] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:16 BXT-2 kernel: [ 606.494455] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:16 BXT-2 kernel: [ 606.495311] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.495318] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:16 BXT-2 kernel: [ 606.495324] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:16 BXT-2 kernel: [ 606.495328] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:16 BXT-2 kernel: [ 606.495568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:16 BXT-2 kernel: [ 606.495576] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495581] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495586] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:16 BXT-2 kernel: [ 606.495591] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:16 BXT-2 kernel: [ 606.495596] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495601] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:16 BXT-2 kernel: [ 606.495606] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:16 BXT-2 kernel: [ 606.495611] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495616] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495621] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:16 BXT-2 kernel: [ 606.495626] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495632] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495637] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495642] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495647] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495652] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495657] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495662] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495667] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495672] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495677] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495682] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495687] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495692] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495697] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495702] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.495707] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495712] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495717] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495722] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495727] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495732] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495737] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.495742] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:16 BXT-2 kernel: [ 606.496120] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.496182] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.496972] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:16 BXT-2 kernel: [ 606.497988] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:16 BXT-2 kernel: [ 606.498035] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.498077] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:16 BXT-2 kernel: [ 606.498120] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:16 BXT-2 kernel: [ 606.498661] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:16 BXT-2 kernel: [ 606.498707] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:16 BXT-2 kernel: [ 606.503493] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:16 BXT-2 kernel: [ 606.503558] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:16 BXT-2 kernel: [ 606.503565] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503570] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503575] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503580] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503585] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503590] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503595] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.503601] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503606] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.503611] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.503616] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:16 BXT-2 kernel: [ 606.503621] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:16 BXT-2 kernel: [ 606.504887] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:16 BXT-2 kernel: [ 606.520889] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:16 BXT-2 kernel: [ 606.521028] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.521276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:16 BXT-2 kernel: [ 606.521334] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:16 BXT-2 kernel: [ 606.521691] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:16 BXT-2 kernel: [ 606.527505] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:16 BXT-2 kernel: [ 606.527616] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.527706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.527753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.527796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.527838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.527882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.527924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.527967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.528010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.528053] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.528100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.528145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.528231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.533781] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:16 BXT-2 kernel: [ 606.534476] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.534527] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.534649] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:16 BXT-2 kernel: [ 606.534693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:16 BXT-2 kernel: [ 606.534737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:16 BXT-2 kernel: [ 606.534781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:16 BXT-2 kernel: [ 606.534823] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:16 BXT-2 kernel: [ 606.534866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.534909] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:16 BXT-2 kernel: [ 606.534952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.534995] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:16 BXT-2 kernel: [ 606.535037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.535078] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:16 BXT-2 kernel: [ 606.535085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.535127] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:16 BXT-2 kernel: [ 606.535132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.535175] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.535266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:16 BXT-2 kernel: [ 606.535311] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:16 BXT-2 kernel: [ 606.535356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:16 BXT-2 kernel: [ 606.535400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.535446] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:16 BXT-2 kernel: [ 606.535491] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:16 BXT-2 kernel: [ 606.535538] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:32:16 BXT-2 kernel: [ 606.535584] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:32:16 BXT-2 kernel: [ 606.535629] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.535674] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.535916] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.535963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.536017] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.536060] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.536713] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.552470] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.552585] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.552638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.552682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.552725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.552768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.552811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.552857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.552900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.552943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.552986] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.553034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.553079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.553123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.553589] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.553635] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.555798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.555846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.555890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:16 BXT-2 kernel: [ 606.574914] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:16 BXT-2 kernel: [ 606.574962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:16 BXT-2 kernel: [ 606.594094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:16 BXT-2 kernel: [ 606.596198] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:16 BXT-2 kernel: [ 606.597232] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.597296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.597339] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:16 BXT-2 kernel: [ 606.597395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:16 BXT-2 kernel: [ 606.614131] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.614333] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.614510] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.630723] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:16 BXT-2 kernel: [ 606.731086] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.731299] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.731354] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:16 BXT-2 kernel: [ 606.731448] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.749475] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.749589] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.749680] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.750000] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.750044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.750091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.750133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.750176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.750266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.750313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.750358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.750403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.750448] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.750497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.750543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.750590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.750654] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:16 BXT-2 kernel: [ 606.750697] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.750752] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.750817] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.750862] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:16 BXT-2 kernel: [ 606.750906] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:16 BXT-2 kernel: [ 606.750945] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:16 BXT-2 kernel: [ 606.751525] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:16 BXT-2 kernel: [ 606.752630] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:16 BXT-2 kernel: [ 606.774527] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.774590] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.774718] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:16 BXT-2 kernel: [ 606.774762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:16 BXT-2 kernel: [ 606.774806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:16 BXT-2 kernel: [ 606.774850] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:16 BXT-2 kernel: [ 606.774892] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:16 BXT-2 kernel: [ 606.774936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.774979] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:16 BXT-2 kernel: [ 606.775022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.775065] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:16 BXT-2 kernel: [ 606.775107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.775149] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:16 BXT-2 kernel: [ 606.775198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.775241] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:16 BXT-2 kernel: [ 606.775255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.775301] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.775347] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:16 BXT-2 kernel: [ 606.775392] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:16 BXT-2 kernel: [ 606.775438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:16 BXT-2 kernel: [ 606.775483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.775531] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:16 BXT-2 kernel: [ 606.775574] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:16 BXT-2 kernel: [ 606.775620] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.775664] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.775710] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.775754] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.775818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.775871] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.775914] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.776530] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:16 BXT-2 kernel: [ 606.776568] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:16 BXT-2 kernel: [ 606.776858] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:16 BXT-2 kernel: [ 606.776911] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.776951] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.777008] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:16 BXT-2 kernel: [ 606.777346] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.777664] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.777708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.777751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.777794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.777836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.777881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.777923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.777966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.778008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.778051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.778097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.778142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.778272] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.778316] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.779759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.779802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:16 BXT-2 kernel: [ 606.779846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:16 BXT-2 kernel: [ 606.798935] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:16 BXT-2 kernel: [ 606.798983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:16 BXT-2 kernel: [ 606.817928] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:16 BXT-2 kernel: [ 606.820029] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:16 BXT-2 kernel: [ 606.821056] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.821122] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.821164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:16 BXT-2 kernel: [ 606.821272] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:16 BXT-2 kernel: [ 606.838001] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.838059] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.838307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.954851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.954973] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.955028] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:16 BXT-2 kernel: [ 606.955129] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.971547] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.971665] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.971757] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.972089] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.972133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.972181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.972310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.972353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.972396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.972439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.972482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.972525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.972568] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:16 BXT-2 kernel: [ 606.972620] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.972665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.972710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.972774] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:16 BXT-2 kernel: [ 606.972818] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.972873] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.972934] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.972980] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:16 BXT-2 kernel: [ 606.973023] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:16 BXT-2 kernel: [ 606.973062] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:16 BXT-2 kernel: [ 606.973651] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:16 BXT-2 kernel: [ 606.974829] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:16 BXT-2 kernel: [ 606.992460] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:16 BXT-2 kernel: [ 606.992522] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:16 BXT-2 kernel: [ 606.992652] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:16 BXT-2 kernel: [ 606.992697] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:16 BXT-2 kernel: [ 606.992742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:16 BXT-2 kernel: [ 606.992786] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:16 BXT-2 kernel: [ 606.992828] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:16 BXT-2 kernel: [ 606.992872] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.992915] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:16 BXT-2 kernel: [ 606.992958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.993001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:16 BXT-2 kernel: [ 606.993043] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.993085] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:16 BXT-2 kernel: [ 606.993092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.993133] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:16 BXT-2 kernel: [ 606.993139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.993881] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:16 BXT-2 kernel: [ 606.993925] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:16 BXT-2 kernel: [ 606.993968] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:16 BXT-2 kernel: [ 606.994010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:16 BXT-2 kernel: [ 606.994052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:16 BXT-2 kernel: [ 606.994097] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:16 BXT-2 kernel: [ 606.994139] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:16 BXT-2 kernel: [ 606.994466] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.994510] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.994553] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.994595] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:16 BXT-2 kernel: [ 606.994662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.994715] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.994759] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:16 BXT-2 kernel: [ 606.995891] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:16 BXT-2 kernel: [ 606.995932] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:16 BXT-2 kernel: [ 606.996368] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:16 BXT-2 kernel: [ 606.996842] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.996883] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:16 BXT-2 kernel: [ 606.996939] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:16 BXT-2 kernel: [ 606.997425] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.997993] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:16 BXT-2 kernel: [ 606.998038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:16 BXT-2 kernel: [ 606.998082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.998125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.998167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.998574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:16 BXT-2 kernel: [ 606.998617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:16 BXT-2 kernel: [ 606.998660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:16 BXT-2 kernel: [ 606.998703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:16 BXT-2 kernel: [ 606.998745] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:16 BXT-2 kernel: [ 606.998796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:16 BXT-2 kernel: [ 606.998841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:16 BXT-2 kernel: [ 606.998916] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:16 BXT-2 kernel: [ 606.998959] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.006586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.006632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.006676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:17 BXT-2 kernel: [ 607.007745] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:17 BXT-2 kernel: [ 607.007789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:17 BXT-2 kernel: [ 607.008817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:17 BXT-2 kernel: [ 607.010910] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:17 BXT-2 kernel: [ 607.011959] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.028950] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.029008] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.029179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.145870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.146047] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.163491] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:17 BXT-2 kernel: [ 607.163606] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.163697] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.164022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.164067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.164111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.164154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.164256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.164299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:17 BXT-2 kernel: [ 607.164348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.164391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.164433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.164477] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.164525] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:17 BXT-2 kernel: [ 607.164571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.164616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.164682] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:17 BXT-2 kernel: [ 607.164725] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.164779] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.164841] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.164886] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:17 BXT-2 kernel: [ 607.164930] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:17 BXT-2 kernel: [ 607.164969] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:17 BXT-2 kernel: [ 607.165589] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:17 BXT-2 kernel: [ 607.167078] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:17 BXT-2 kernel: [ 607.187030] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.187095] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.187270] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:17 BXT-2 kernel: [ 607.187320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:17 BXT-2 kernel: [ 607.187365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:17 BXT-2 kernel: [ 607.187409] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:17 BXT-2 kernel: [ 607.187451] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.187497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.187541] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:17 BXT-2 kernel: [ 607.187744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.187788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:17 BXT-2 kernel: [ 607.187831] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.187873] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:17 BXT-2 kernel: [ 607.187882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.187925] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:17 BXT-2 kernel: [ 607.187931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.187975] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.188018] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:17 BXT-2 kernel: [ 607.188061] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:17 BXT-2 kernel: [ 607.188105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:17 BXT-2 kernel: [ 607.188148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.188228] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:17 BXT-2 kernel: [ 607.188270] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:17 BXT-2 kernel: [ 607.188313] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.188356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.188399] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.188442] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.188510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.188563] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.188607] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.189224] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:17 BXT-2 kernel: [ 607.189262] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:17 BXT-2 kernel: [ 607.189556] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:17 BXT-2 kernel: [ 607.189610] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.189651] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.189708] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:17 BXT-2 kernel: [ 607.190363] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.190690] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.190734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.190778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.190820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.190863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.190906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:17 BXT-2 kernel: [ 607.190949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.190992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.191035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.191079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:17 BXT-2 kernel: [ 607.191127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.191172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.191839] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:17 BXT-2 kernel: [ 607.191882] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.193736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.193782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.193826] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:17 BXT-2 kernel: [ 607.194619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.194662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.195398] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:17 BXT-2 kernel: [ 607.195444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:17 BXT-2 kernel: [ 607.197766] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:17 BXT-2 kernel: [ 607.199868] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:17 BXT-2 kernel: [ 607.200930] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.217831] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.217889] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.218061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.334714] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.334848] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.352609] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:17 BXT-2 kernel: [ 607.352721] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.352810] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.353128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.353172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.353270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.353313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.353359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.353402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:17 BXT-2 kernel: [ 607.353449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.353492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.353535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.353578] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.353627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:17 BXT-2 kernel: [ 607.353672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.353717] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.353781] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:17 BXT-2 kernel: [ 607.353825] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.353879] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.353943] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.353988] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:17 BXT-2 kernel: [ 607.354032] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:17 BXT-2 kernel: [ 607.354071] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:17 BXT-2 kernel: [ 607.354657] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:17 BXT-2 kernel: [ 607.381304] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:17 BXT-2 kernel: [ 607.381347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:17 BXT-2 kernel: [ 607.381392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:17 BXT-2 kernel: [ 607.381434] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:17 BXT-2 kernel: [ 607.381475] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:17 BXT-2 kernel: [ 607.381519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.381561] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:17 BXT-2 kernel: [ 607.381602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.381644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:17 BXT-2 kernel: [ 607.381685] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.381726] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:17 BXT-2 kernel: [ 607.381733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.381774] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:17 BXT-2 kernel: [ 607.381779] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.381821] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.381862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:17 BXT-2 kernel: [ 607.381904] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:17 BXT-2 kernel: [ 607.381945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:17 BXT-2 kernel: [ 607.381986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.382029] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:17 BXT-2 kernel: [ 607.382070] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:17 BXT-2 kernel: [ 607.382113] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.382154] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.382242] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.382283] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.382328] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:17 BXT-2 kernel: [ 607.382370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:17 BXT-2 kernel: [ 607.382412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:17 BXT-2 kernel: [ 607.382454] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:17 BXT-2 kernel: [ 607.382495] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.382536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.382578] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:17 BXT-2 kernel: [ 607.382619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.382661] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:17 BXT-2 kernel: [ 607.382702] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.382742] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:17 BXT-2 kernel: [ 607.382747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.382787] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:17 BXT-2 kernel: [ 607.382792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.382833] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.382875] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:17 BXT-2 kernel: [ 607.382916] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:17 BXT-2 kernel: [ 607.382957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:17 BXT-2 kernel: [ 607.382997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.383040] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:17 BXT-2 kernel: [ 607.383081] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:17 BXT-2 kernel: [ 607.383122] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.383163] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.383246] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.383288] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.383332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.383383] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.383426] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:17 BXT-2 kernel: [ 607.383469] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.383510] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.383662] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:17 BXT-2 kernel: [ 607.383698] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:17 BXT-2 kernel: [ 607.383986] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:17 BXT-2 kernel: [ 607.384040] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.384079] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:17 BXT-2 kernel: [ 607.384135] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:17 BXT-2 kernel: [ 607.384424] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.384748] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.384790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.384832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.384874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.384915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.384956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:17 BXT-2 kernel: [ 607.384998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.385039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.385080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.385123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:17 BXT-2 kernel: [ 607.385169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.385279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.385352] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:17 BXT-2 kernel: [ 607.385394] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.386798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.386839] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.386882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:17 BXT-2 kernel: [ 607.405911] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:17 BXT-2 kernel: [ 607.405956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:17 BXT-2 kernel: [ 607.424011] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:17 BXT-2 kernel: [ 607.426090] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:17 BXT-2 kernel: [ 607.427278] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:17 BXT-2 kernel: [ 607.427353] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.427395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:17 BXT-2 kernel: [ 607.427451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:17 BXT-2 kernel: [ 607.427632] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:17 BXT-2 kernel: [ 607.427675] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.429094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.429136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.429179] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:17 BXT-2 kernel: [ 607.429991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.430032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.430761] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:17 BXT-2 kernel: [ 607.430802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:17 BXT-2 kernel: [ 607.431839] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:17 BXT-2 kernel: [ 607.433922] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:17 BXT-2 kernel: [ 607.435094] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.451960] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.452013] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:17 BXT-2 kernel: [ 607.452224] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.452395] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.452446] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.452613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.452973] Console: switching to colour frame buffer device 240x67 >May 24 03:32:17 BXT-2 kernel: [ 607.784206] Console: switching to colour dummy device 80x25 >May 24 03:32:17 BXT-2 kernel: [ 607.803780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.803845] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.804447] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:17 BXT-2 kernel: [ 607.805476] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:17 BXT-2 kernel: [ 607.805524] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.805567] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.805609] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.806115] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:17 BXT-2 kernel: [ 607.806737] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:17 BXT-2 kernel: [ 607.807649] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.808900] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.810143] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.811446] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.812699] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.813952] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.815237] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.816483] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.817839] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.819229] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.820804] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.822195] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.823567] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.825111] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.826505] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.828096] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.829483] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.830743] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.832020] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.833282] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.834525] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.836088] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.837489] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.838870] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.840261] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.841842] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.843235] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.844862] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.846260] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.847044] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:17 BXT-2 kernel: [ 607.847945] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.847952] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:17 BXT-2 kernel: [ 607.847958] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:17 BXT-2 kernel: [ 607.847962] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:17 BXT-2 kernel: [ 607.848540] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:17 BXT-2 kernel: [ 607.848548] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848554] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848559] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:17 BXT-2 kernel: [ 607.848564] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:17 BXT-2 kernel: [ 607.848569] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848574] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:17 BXT-2 kernel: [ 607.848579] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:17 BXT-2 kernel: [ 607.848584] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848589] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848594] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:17 BXT-2 kernel: [ 607.848599] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848604] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848609] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848614] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848619] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848624] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848629] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848634] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848639] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848644] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848650] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848655] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848660] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848665] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848670] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848675] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.848680] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848685] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848690] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848695] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848700] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848705] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848710] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.848715] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:17 BXT-2 kernel: [ 607.848798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.848856] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.850991] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:17 BXT-2 kernel: [ 607.852149] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:17 BXT-2 kernel: [ 607.852237] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.852280] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:17 BXT-2 kernel: [ 607.852322] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:17 BXT-2 kernel: [ 607.852802] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:17 BXT-2 kernel: [ 607.852845] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:17 BXT-2 kernel: [ 607.858096] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:17 BXT-2 kernel: [ 607.858232] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:17 BXT-2 kernel: [ 607.858239] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858245] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858250] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858255] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858260] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858265] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858270] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.858275] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858281] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.858286] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.858291] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.858296] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:17 BXT-2 kernel: [ 607.865517] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.865586] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.866143] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:17 BXT-2 kernel: [ 607.867118] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:17 BXT-2 kernel: [ 607.867167] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.867273] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.867317] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.867821] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:17 BXT-2 kernel: [ 607.868302] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:17 BXT-2 kernel: [ 607.869407] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.870698] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.872066] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.873343] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.874845] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.876117] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.877411] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.878885] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.880366] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.882027] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.883434] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.884922] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.888984] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.890371] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.891747] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.893448] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.894815] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.896061] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.897302] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.898542] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.899804] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.901203] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.902646] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.904212] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.905669] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.907204] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.908660] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.910085] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.911452] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:17 BXT-2 kernel: [ 607.912281] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:17 BXT-2 kernel: [ 607.912999] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.913005] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:17 BXT-2 kernel: [ 607.913011] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:17 BXT-2 kernel: [ 607.913015] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:17 BXT-2 kernel: [ 607.913427] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:17 BXT-2 kernel: [ 607.913435] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913440] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913446] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:17 BXT-2 kernel: [ 607.913451] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:17 BXT-2 kernel: [ 607.913456] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913461] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:17 BXT-2 kernel: [ 607.913466] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:17 BXT-2 kernel: [ 607.913471] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913476] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913481] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:17 BXT-2 kernel: [ 607.913486] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913491] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913496] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913501] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913506] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913511] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913516] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913522] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913527] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913532] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913537] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913542] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913547] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913552] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913557] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913562] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.913567] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913572] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913577] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913582] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913587] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913592] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913597] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.913602] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:17 BXT-2 kernel: [ 607.914350] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.914413] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.914957] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:17 BXT-2 kernel: [ 607.915907] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:17 BXT-2 kernel: [ 607.915954] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:17 BXT-2 kernel: [ 607.915996] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:17 BXT-2 kernel: [ 607.916038] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:17 BXT-2 kernel: [ 607.916581] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:17 BXT-2 kernel: [ 607.916626] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:17 BXT-2 kernel: [ 607.921795] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:17 BXT-2 kernel: [ 607.921863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:17 BXT-2 kernel: [ 607.921870] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921876] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921881] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921886] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921891] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921896] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921901] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.921906] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921911] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.921916] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.921921] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:17 BXT-2 kernel: [ 607.921926] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:17 BXT-2 kernel: [ 607.923534] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:17 BXT-2 kernel: [ 607.939072] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:17 BXT-2 kernel: [ 607.939275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.939466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:17 BXT-2 kernel: [ 607.939522] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:17 BXT-2 kernel: [ 607.939614] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:17 BXT-2 kernel: [ 607.945476] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:17 BXT-2 kernel: [ 607.945592] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.945681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.945728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.945771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.945814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.945859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:17 BXT-2 kernel: [ 607.945901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.945944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.945987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.946031] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.946078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:17 BXT-2 kernel: [ 607.946123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.946168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.951945] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:17 BXT-2 kernel: [ 607.952742] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:17 BXT-2 kernel: [ 607.952775] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:17 BXT-2 kernel: [ 607.952894] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:17 BXT-2 kernel: [ 607.952937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:17 BXT-2 kernel: [ 607.952982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:17 BXT-2 kernel: [ 607.953025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:17 BXT-2 kernel: [ 607.953067] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:17 BXT-2 kernel: [ 607.953111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.953153] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:17 BXT-2 kernel: [ 607.953240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.953288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:17 BXT-2 kernel: [ 607.953333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.953377] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:17 BXT-2 kernel: [ 607.953386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.953428] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:17 BXT-2 kernel: [ 607.953710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.953767] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:17 BXT-2 kernel: [ 607.953810] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:17 BXT-2 kernel: [ 607.953853] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:17 BXT-2 kernel: [ 607.953896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:17 BXT-2 kernel: [ 607.953939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:17 BXT-2 kernel: [ 607.953985] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:17 BXT-2 kernel: [ 607.954027] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:17 BXT-2 kernel: [ 607.954073] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:32:17 BXT-2 kernel: [ 607.954116] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:32:17 BXT-2 kernel: [ 607.954160] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.954234] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.954279] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:17 BXT-2 kernel: [ 607.954328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:17 BXT-2 kernel: [ 607.954384] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.954604] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.955263] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:17 BXT-2 kernel: [ 607.969720] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:17 BXT-2 kernel: [ 607.969833] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.969886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:17 BXT-2 kernel: [ 607.969930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.969972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.970015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.970058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:17 BXT-2 kernel: [ 607.970104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:17 BXT-2 kernel: [ 607.970147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:17 BXT-2 kernel: [ 607.970234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:17 BXT-2 kernel: [ 607.970284] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:17 BXT-2 kernel: [ 607.970333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:17 BXT-2 kernel: [ 607.970380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.970781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:17 BXT-2 kernel: [ 607.970858] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:17 BXT-2 kernel: [ 607.970901] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:17 BXT-2 kernel: [ 607.972860] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.972907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:17 BXT-2 kernel: [ 607.972952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:17 BXT-2 kernel: [ 607.992257] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:17 BXT-2 kernel: [ 607.992305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:18 BXT-2 kernel: [ 608.010539] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:18 BXT-2 kernel: [ 608.012646] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:18 BXT-2 kernel: [ 608.013668] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.013732] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.013775] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:18 BXT-2 kernel: [ 608.013831] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:18 BXT-2 kernel: [ 608.030526] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:18 BXT-2 kernel: [ 608.030595] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.030766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.047090] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:18 BXT-2 kernel: [ 608.147439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.147554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.147609] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:18 BXT-2 kernel: [ 608.147697] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.165475] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.165589] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.165680] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.166001] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.166045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.166092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.166134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.166177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.166261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.166313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.166359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.166405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.166451] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:18 BXT-2 kernel: [ 608.166501] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.166547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.166596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.166660] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.166703] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.166757] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.166818] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.166863] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.166906] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:18 BXT-2 kernel: [ 608.166945] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:18 BXT-2 kernel: [ 608.167540] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.169136] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:18 BXT-2 kernel: [ 608.187206] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.187265] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:18 BXT-2 kernel: [ 608.187390] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:18 BXT-2 kernel: [ 608.187434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:18 BXT-2 kernel: [ 608.187480] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:18 BXT-2 kernel: [ 608.187525] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:18 BXT-2 kernel: [ 608.187568] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:18 BXT-2 kernel: [ 608.187612] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.187656] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:18 BXT-2 kernel: [ 608.187701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.187744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:18 BXT-2 kernel: [ 608.187786] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.187828] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:18 BXT-2 kernel: [ 608.187835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.187877] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:18 BXT-2 kernel: [ 608.187882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.187925] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.187970] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:18 BXT-2 kernel: [ 608.188012] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:18 BXT-2 kernel: [ 608.188055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:18 BXT-2 kernel: [ 608.188097] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.188141] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:18 BXT-2 kernel: [ 608.188224] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:18 BXT-2 kernel: [ 608.188271] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.188316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.188361] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.188406] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.188468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.188522] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.188566] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.189163] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.189238] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.189535] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:18 BXT-2 kernel: [ 608.189591] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.189633] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.189691] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.189996] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.190373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.190418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.190461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.190506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.190549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.190593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.190636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.190680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.190723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.190766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.190815] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.190860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.190936] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.190979] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.192647] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.192694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.192738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:18 BXT-2 kernel: [ 608.212080] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:18 BXT-2 kernel: [ 608.212128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:18 BXT-2 kernel: [ 608.231115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:18 BXT-2 kernel: [ 608.233217] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:18 BXT-2 kernel: [ 608.234268] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.234360] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.234403] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:18 BXT-2 kernel: [ 608.234459] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:18 BXT-2 kernel: [ 608.251183] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:18 BXT-2 kernel: [ 608.251285] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.251457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.368146] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.368359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.368435] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:18 BXT-2 kernel: [ 608.368562] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.386494] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.386610] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.386701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.387021] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.387066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.387114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.387157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.387595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.387640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.387682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.387725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.387768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.387811] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:18 BXT-2 kernel: [ 608.387862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.387908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.387953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.388014] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.388057] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.388111] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.388173] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.388246] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.388289] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:18 BXT-2 kernel: [ 608.388328] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:18 BXT-2 kernel: [ 608.388882] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.390725] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:18 BXT-2 kernel: [ 608.410250] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.410316] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.410442] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:18 BXT-2 kernel: [ 608.410486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:18 BXT-2 kernel: [ 608.410530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:18 BXT-2 kernel: [ 608.410574] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:18 BXT-2 kernel: [ 608.410616] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:18 BXT-2 kernel: [ 608.410660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.410703] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:18 BXT-2 kernel: [ 608.410746] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.410789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:18 BXT-2 kernel: [ 608.410831] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.410873] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:18 BXT-2 kernel: [ 608.410879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.410921] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:18 BXT-2 kernel: [ 608.410927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.410970] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.411012] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:18 BXT-2 kernel: [ 608.411055] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:18 BXT-2 kernel: [ 608.411097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:18 BXT-2 kernel: [ 608.411139] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.411238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:18 BXT-2 kernel: [ 608.411282] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:18 BXT-2 kernel: [ 608.411325] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.411368] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.411412] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.411455] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.411518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.411571] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.411615] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.412218] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.412256] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.412547] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:18 BXT-2 kernel: [ 608.412604] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.412646] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.412706] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.412977] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.413307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.413351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.413395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.413438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.413481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.413525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.413568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.413611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.413654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.413697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.413744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.413789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.413864] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.413907] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.415378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.415424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.415469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:18 BXT-2 kernel: [ 608.416526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.416572] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.417650] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:18 BXT-2 kernel: [ 608.417697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:18 BXT-2 kernel: [ 608.418750] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:18 BXT-2 kernel: [ 608.420835] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:18 BXT-2 kernel: [ 608.421840] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.438722] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.438779] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.438951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.555578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.555708] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.573456] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.573569] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.573660] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.573983] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.574027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.574070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.574113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.574156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.574281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.574330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.574374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.574416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.574460] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.574508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.574553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.574598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.574657] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.574701] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.574754] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.574817] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.574861] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.574904] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:18 BXT-2 kernel: [ 608.574943] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:18 BXT-2 kernel: [ 608.575531] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.577859] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:18 BXT-2 kernel: [ 608.600724] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.600789] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.600913] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:18 BXT-2 kernel: [ 608.600957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:18 BXT-2 kernel: [ 608.601001] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:18 BXT-2 kernel: [ 608.601045] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:18 BXT-2 kernel: [ 608.601087] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:18 BXT-2 kernel: [ 608.601131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.601174] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:18 BXT-2 kernel: [ 608.601276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.601320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:18 BXT-2 kernel: [ 608.601362] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.601407] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:18 BXT-2 kernel: [ 608.601413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.601455] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:18 BXT-2 kernel: [ 608.601461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.601504] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.601547] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:18 BXT-2 kernel: [ 608.601590] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:18 BXT-2 kernel: [ 608.601632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:18 BXT-2 kernel: [ 608.601676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.601723] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:18 BXT-2 kernel: [ 608.601765] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:18 BXT-2 kernel: [ 608.601808] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.601852] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.601894] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.601938] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.602004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.602058] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.602101] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.602722] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.602760] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.603049] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:18 BXT-2 kernel: [ 608.603104] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.603144] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.603237] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.603872] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.604245] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.604426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.604470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.604512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.604555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.604598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.604641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.604684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.604726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.604769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.604817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.604862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.604937] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.604980] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.606740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.606785] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.606829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:18 BXT-2 kernel: [ 608.607770] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:18 BXT-2 kernel: [ 608.607815] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:18 BXT-2 kernel: [ 608.608878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:18 BXT-2 kernel: [ 608.610972] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:18 BXT-2 kernel: [ 608.611954] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.628822] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.628879] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.629049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.745742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.745880] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.763733] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.763985] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.764079] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.764413] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.764460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.764504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.764547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.764591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.764634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.764684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.764727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.764770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.764814] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.764862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.764909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.764954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.765017] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.765060] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.765114] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.765176] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.765239] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.765283] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:18 BXT-2 kernel: [ 608.765324] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:18 BXT-2 kernel: [ 608.765882] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.790253] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:18 BXT-2 kernel: [ 608.790296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:18 BXT-2 kernel: [ 608.790339] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:18 BXT-2 kernel: [ 608.790381] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:18 BXT-2 kernel: [ 608.790422] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:18 BXT-2 kernel: [ 608.790465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.790508] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:18 BXT-2 kernel: [ 608.790549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.790591] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:18 BXT-2 kernel: [ 608.790632] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.790672] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:18 BXT-2 kernel: [ 608.790680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.790721] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:18 BXT-2 kernel: [ 608.790725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.790767] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.790808] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:18 BXT-2 kernel: [ 608.790850] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:18 BXT-2 kernel: [ 608.790891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:18 BXT-2 kernel: [ 608.790932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.790975] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:18 BXT-2 kernel: [ 608.791016] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:18 BXT-2 kernel: [ 608.791058] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.791099] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.791140] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.791195] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.791241] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:18 BXT-2 kernel: [ 608.791282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:18 BXT-2 kernel: [ 608.791323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:18 BXT-2 kernel: [ 608.791365] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:18 BXT-2 kernel: [ 608.791406] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:18 BXT-2 kernel: [ 608.791447] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.791489] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:18 BXT-2 kernel: [ 608.791530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.791571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:18 BXT-2 kernel: [ 608.791612] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.791652] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:18 BXT-2 kernel: [ 608.791657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.791697] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:18 BXT-2 kernel: [ 608.791702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.791744] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:18 BXT-2 kernel: [ 608.791785] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:18 BXT-2 kernel: [ 608.791826] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:18 BXT-2 kernel: [ 608.791867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:18 BXT-2 kernel: [ 608.791908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:18 BXT-2 kernel: [ 608.791950] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:18 BXT-2 kernel: [ 608.791991] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:18 BXT-2 kernel: [ 608.792032] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.792073] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.792114] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.792155] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:18 BXT-2 kernel: [ 608.792246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.792296] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.792339] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:18 BXT-2 kernel: [ 608.792381] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.792422] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.792576] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:18 BXT-2 kernel: [ 608.792611] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:18 BXT-2 kernel: [ 608.792899] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:18 BXT-2 kernel: [ 608.792953] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.792992] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:18 BXT-2 kernel: [ 608.793047] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:18 BXT-2 kernel: [ 608.793338] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.793655] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:18 BXT-2 kernel: [ 608.793698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.793739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.793781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.793822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.793863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:18 BXT-2 kernel: [ 608.793905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:18 BXT-2 kernel: [ 608.793946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:18 BXT-2 kernel: [ 608.793987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:18 BXT-2 kernel: [ 608.794029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:18 BXT-2 kernel: [ 608.794074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.794118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.794238] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:18 BXT-2 kernel: [ 608.794280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.795705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.795746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.795789] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:18 BXT-2 kernel: [ 608.814719] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:18 BXT-2 kernel: [ 608.814763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:18 BXT-2 kernel: [ 608.832819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:18 BXT-2 kernel: [ 608.834902] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:18 BXT-2 kernel: [ 608.836048] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:18 BXT-2 kernel: [ 608.836113] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:18 BXT-2 kernel: [ 608.836154] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:18 BXT-2 kernel: [ 608.836236] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:18 BXT-2 kernel: [ 608.836417] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:18 BXT-2 kernel: [ 608.836459] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.837922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.837965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.838008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:18 BXT-2 kernel: [ 608.838794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.838834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:18 BXT-2 kernel: [ 608.839565] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:18 BXT-2 kernel: [ 608.839606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:18 BXT-2 kernel: [ 608.840644] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:18 BXT-2 kernel: [ 608.842720] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:18 BXT-2 kernel: [ 608.843878] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:18 BXT-2 kernel: [ 608.860736] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:18 BXT-2 kernel: [ 608.860790] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:18 BXT-2 kernel: [ 608.860966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:18 BXT-2 kernel: [ 608.861137] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:18 BXT-2 kernel: [ 608.861230] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:18 BXT-2 kernel: [ 608.861398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:18 BXT-2 kernel: [ 608.861756] Console: switching to colour frame buffer device 240x67 >May 24 03:32:19 BXT-2 kernel: [ 609.209139] Console: switching to colour dummy device 80x25 >May 24 03:32:19 BXT-2 kernel: [ 609.229780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:19 BXT-2 kernel: [ 609.229847] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:19 BXT-2 kernel: [ 609.230577] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:19 BXT-2 kernel: [ 609.231466] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:19 BXT-2 kernel: [ 609.231512] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.231555] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.231597] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.232086] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:19 BXT-2 kernel: [ 609.232539] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:19 BXT-2 kernel: [ 609.233403] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.234717] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.235982] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.237237] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.238481] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.240025] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.241301] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.242554] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.244008] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.245403] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.246789] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.248187] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.249578] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.251023] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.252413] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.253800] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.255185] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.256440] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.257701] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.258959] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.260229] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.261663] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.263050] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.264438] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.265831] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.267224] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.268834] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.270229] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.271813] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.272612] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:19 BXT-2 kernel: [ 609.273541] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:19 BXT-2 kernel: [ 609.273548] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:19 BXT-2 kernel: [ 609.273553] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:19 BXT-2 kernel: [ 609.273558] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:19 BXT-2 kernel: [ 609.273786] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:19 BXT-2 kernel: [ 609.273794] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273799] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273804] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:19 BXT-2 kernel: [ 609.273809] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:19 BXT-2 kernel: [ 609.273814] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273819] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:19 BXT-2 kernel: [ 609.273824] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:19 BXT-2 kernel: [ 609.273829] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273834] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273839] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:19 BXT-2 kernel: [ 609.273844] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273850] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273855] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273860] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273865] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273870] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273875] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273880] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273885] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273890] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273895] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273900] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273905] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273910] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273915] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273920] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.273925] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273930] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273935] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273940] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273945] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273950] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273955] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.273960] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:19 BXT-2 kernel: [ 609.274045] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:19 BXT-2 kernel: [ 609.274103] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:19 BXT-2 kernel: [ 609.276262] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:19 BXT-2 kernel: [ 609.277116] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:19 BXT-2 kernel: [ 609.277160] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.277559] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:19 BXT-2 kernel: [ 609.277602] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:19 BXT-2 kernel: [ 609.278125] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:19 BXT-2 kernel: [ 609.278168] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:19 BXT-2 kernel: [ 609.283396] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:19 BXT-2 kernel: [ 609.283458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:19 BXT-2 kernel: [ 609.283466] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283471] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283476] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283481] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283486] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283491] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283496] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.283501] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283506] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.283511] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.283516] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.283521] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:19 BXT-2 kernel: [ 609.290966] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:19 BXT-2 kernel: [ 609.291034] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:19 BXT-2 kernel: [ 609.291694] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:19 BXT-2 kernel: [ 609.292635] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:19 BXT-2 kernel: [ 609.292680] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.292722] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.292764] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.293417] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:19 BXT-2 kernel: [ 609.293815] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:19 BXT-2 kernel: [ 609.294897] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.296185] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.297455] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.298716] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.299971] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.301220] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.302465] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.304014] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.305296] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.306981] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.308410] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.310001] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.311423] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.312980] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.314398] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.315980] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.317392] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.318835] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.320113] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.321898] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.323181] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.324674] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.326053] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.327534] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.329048] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.330434] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.331811] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.333192] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.334554] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:19 BXT-2 kernel: [ 609.335351] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:19 BXT-2 kernel: [ 609.336091] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:19 BXT-2 kernel: [ 609.336097] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:19 BXT-2 kernel: [ 609.336102] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:19 BXT-2 kernel: [ 609.336107] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:19 BXT-2 kernel: [ 609.336377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:19 BXT-2 kernel: [ 609.336385] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336391] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336396] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:19 BXT-2 kernel: [ 609.336402] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:19 BXT-2 kernel: [ 609.336407] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336412] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:19 BXT-2 kernel: [ 609.336417] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:19 BXT-2 kernel: [ 609.336422] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336427] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336433] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:19 BXT-2 kernel: [ 609.336438] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336443] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336449] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336454] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336459] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336465] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336470] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336475] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336480] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336485] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336491] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336497] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336502] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336507] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336512] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336517] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.336522] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336527] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336532] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336538] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336543] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336548] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336553] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.336558] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:19 BXT-2 kernel: [ 609.336979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:19 BXT-2 kernel: [ 609.337039] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:19 BXT-2 kernel: [ 609.337592] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:19 BXT-2 kernel: [ 609.338483] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:19 BXT-2 kernel: [ 609.338530] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:19 BXT-2 kernel: [ 609.338573] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:19 BXT-2 kernel: [ 609.338616] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:19 BXT-2 kernel: [ 609.339108] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:19 BXT-2 kernel: [ 609.339151] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:19 BXT-2 kernel: [ 609.343986] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:19 BXT-2 kernel: [ 609.344052] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:19 BXT-2 kernel: [ 609.344059] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344064] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344069] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344074] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344079] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344085] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344090] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.344095] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344100] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:19 BXT-2 kernel: [ 609.344105] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.344110] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:19 BXT-2 kernel: [ 609.344115] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:39 BXT-2 kernel: [ 609.573295] PM: Syncing filesystems ... done. >May 24 03:32:39 BXT-2 kernel: [ 609.641285] PM: Preparing system for sleep (mem) >May 24 03:32:39 BXT-2 kernel: [ 609.641824] Freezing user space processes ... >May 24 03:32:39 BXT-2 kernel: [ 610.404015] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 611.335328] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 612.248611] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 613.163132] hpet1: lost 7160 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 614.096613] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 615.029736] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 615.964595] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 616.899667] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 617.835727] hpet1: lost 7160 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 618.771186] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 619.705829] hpet1: lost 7160 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 620.639219] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 621.573510] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 622.505528] hpet1: lost 7160 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 623.439056] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 624.372115] hpet1: lost 7161 rtc interrupts >May 24 03:32:39 BXT-2 kernel: [ 629.646090] Freezing of tasks failed after 20.004 seconds (1 tasks refusing to freeze, wq_busy=0): >May 24 03:32:39 BXT-2 kernel: [ 629.646217] fstrim D 0 21920 21919 0x00000004 >May 24 03:32:39 BXT-2 kernel: [ 629.646248] Call Trace: >May 24 03:32:39 BXT-2 kernel: [ 629.646260] __schedule+0x402/0xb30 >May 24 03:32:39 BXT-2 kernel: [ 629.646268] ? ___preempt_schedule+0x16/0x18 >May 24 03:32:39 BXT-2 kernel: [ 629.646274] schedule+0x3b/0x90 >May 24 03:32:39 BXT-2 kernel: [ 629.646279] schedule_timeout+0x251/0x4a0 >May 24 03:32:39 BXT-2 kernel: [ 629.646285] ? trace_hardirqs_on_caller+0x118/0x180 >May 24 03:32:39 BXT-2 kernel: [ 629.646290] ? trace_hardirqs_on+0xd/0x10 >May 24 03:32:39 BXT-2 kernel: [ 629.646298] io_schedule_timeout+0x19/0x40 >May 24 03:32:39 BXT-2 kernel: [ 629.646302] ? io_schedule_timeout+0x19/0x40 >May 24 03:32:39 BXT-2 kernel: [ 629.646306] wait_for_common_io.constprop.1+0x101/0x180 >May 24 03:32:39 BXT-2 kernel: [ 629.646314] ? wake_up_q+0x70/0x70 >May 24 03:32:39 BXT-2 kernel: [ 629.646320] wait_for_completion_io+0x13/0x20 >May 24 03:32:39 BXT-2 kernel: [ 629.646325] submit_bio_wait+0x54/0x60 >May 24 03:32:39 BXT-2 kernel: [ 629.646334] blkdev_issue_discard+0x6c/0xb0 >May 24 03:32:39 BXT-2 kernel: [ 629.646339] ? ext4_trim_fs+0x434/0xc60 >May 24 03:32:39 BXT-2 kernel: [ 629.646347] ext4_trim_fs+0x4c3/0xc60 >May 24 03:32:39 BXT-2 kernel: [ 629.646350] ? ext4_trim_fs+0x4c3/0xc60 >May 24 03:32:39 BXT-2 kernel: [ 629.646363] ext4_ioctl+0xcb8/0x1180 >May 24 03:32:39 BXT-2 kernel: [ 629.646374] do_vfs_ioctl+0x90/0x6d0 >May 24 03:32:39 BXT-2 kernel: [ 629.646379] ? SyS_newfstat+0x35/0x50 >May 24 03:32:39 BXT-2 kernel: [ 629.646384] ? trace_hardirqs_on_caller+0x118/0x180 >May 24 03:32:39 BXT-2 kernel: [ 629.646390] SyS_ioctl+0x3c/0x70 >May 24 03:32:39 BXT-2 kernel: [ 629.646396] entry_SYSCALL_64_fastpath+0x1c/0xb1 >May 24 03:32:39 BXT-2 kernel: [ 629.646401] RIP: 0033:0x7f8d3df9d8b7 >May 24 03:32:39 BXT-2 kernel: [ 629.646404] RSP: 002b:00007ffd6b5e6cd8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 >May 24 03:32:39 BXT-2 kernel: [ 629.646410] RAX: ffffffffffffffda RBX: 00007ffd6b5e6e90 RCX: 00007f8d3df9d8b7 >May 24 03:32:39 BXT-2 kernel: [ 629.646413] RDX: 00007ffd6b5e6ce0 RSI: 00000000c0185879 RDI: 0000000000000004 >May 24 03:32:39 BXT-2 kernel: [ 629.646416] RBP: 0000562ae26c8050 R08: 0000562ae26ce2e0 R09: 0000000000000000 >May 24 03:32:39 BXT-2 kernel: [ 629.646419] R10: 000000000000000a R11: 0000000000000246 R12: 0000562ae26c8030 >May 24 03:32:39 BXT-2 kernel: [ 629.646422] R13: 00007ffd6b5e6e18 R14: 0000000000000000 R15: 0000562ae26c9a90 >May 24 03:32:39 BXT-2 kernel: [ 629.646437] OOM killer enabled. >May 24 03:32:39 BXT-2 kernel: [ 629.646440] Restarting tasks ... done. >May 24 03:32:39 BXT-2 kernel: [ 629.648598] video LNXVIDEO:00: Restoring backlight state >May 24 03:32:39 BXT-2 kernel: [ 629.694712] Console: switching to colour frame buffer device 240x67 >May 24 03:32:40 BXT-2 kernel: [ 630.119629] Console: switching to colour dummy device 80x25 >May 24 03:32:40 BXT-2 kernel: [ 630.139037] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.139106] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.139854] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:40 BXT-2 kernel: [ 630.141258] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:40 BXT-2 kernel: [ 630.141306] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.141349] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.141392] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.141892] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:40 BXT-2 kernel: [ 630.142789] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:40 BXT-2 kernel: [ 630.144256] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.145586] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.147254] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.149415] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.150964] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.152245] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.153606] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.155196] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.156487] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.157901] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.159443] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.161062] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.162490] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.164264] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.166091] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.167539] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.169462] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.171113] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.172446] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.174259] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.175591] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.177093] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.178597] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.180605] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.182299] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.184005] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.185452] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.186874] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.188652] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.189604] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:40 BXT-2 kernel: [ 630.190406] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.190413] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:40 BXT-2 kernel: [ 630.190419] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:40 BXT-2 kernel: [ 630.190423] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:40 BXT-2 kernel: [ 630.190665] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:40 BXT-2 kernel: [ 630.190672] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190677] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190683] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:40 BXT-2 kernel: [ 630.190688] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:40 BXT-2 kernel: [ 630.190693] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190698] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:40 BXT-2 kernel: [ 630.190703] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:40 BXT-2 kernel: [ 630.190708] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190713] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190718] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:40 BXT-2 kernel: [ 630.190723] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190728] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190733] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190738] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190744] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190749] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190754] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190759] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190764] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190769] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190774] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190779] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190784] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190789] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190794] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190799] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.190804] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190810] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190814] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190819] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190824] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190829] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190834] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.190839] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:40 BXT-2 kernel: [ 630.190930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.190989] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.192917] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:40 BXT-2 kernel: [ 630.193957] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:40 BXT-2 kernel: [ 630.194004] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.194876] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:40 BXT-2 kernel: [ 630.194919] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:40 BXT-2 kernel: [ 630.195458] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:40 BXT-2 kernel: [ 630.195505] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:40 BXT-2 kernel: [ 630.200927] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:40 BXT-2 kernel: [ 630.201001] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:40 BXT-2 kernel: [ 630.201009] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201014] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201019] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201024] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201029] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201034] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201039] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.201044] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201050] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.201055] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.201060] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.201065] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:40 BXT-2 kernel: [ 630.209246] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.209314] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.210482] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:40 BXT-2 kernel: [ 630.211545] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:40 BXT-2 kernel: [ 630.211593] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.211635] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.211678] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.212301] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:40 BXT-2 kernel: [ 630.212796] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:40 BXT-2 kernel: [ 630.213807] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.215133] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.216547] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.218038] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.219344] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.220699] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.222063] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.223371] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.224975] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.226433] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.228038] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.229595] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.231290] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.232968] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.234397] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.235972] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.237384] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.238991] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.240358] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.241910] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.243249] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.244721] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.246138] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.247545] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.249126] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.250515] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.251938] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.253325] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.255079] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:40 BXT-2 kernel: [ 630.255883] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:40 BXT-2 kernel: [ 630.256742] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.256750] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:40 BXT-2 kernel: [ 630.256755] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:40 BXT-2 kernel: [ 630.256759] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:40 BXT-2 kernel: [ 630.256994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:40 BXT-2 kernel: [ 630.257001] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257006] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257012] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:40 BXT-2 kernel: [ 630.257017] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:40 BXT-2 kernel: [ 630.257022] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257027] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:40 BXT-2 kernel: [ 630.257032] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:40 BXT-2 kernel: [ 630.257037] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257042] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257047] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:40 BXT-2 kernel: [ 630.257052] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257057] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257062] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257067] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257073] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257078] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257083] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257088] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257093] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257098] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257103] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257108] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257113] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257118] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257123] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257128] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.257133] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257138] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257143] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257181] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257187] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257192] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257197] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.257202] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:40 BXT-2 kernel: [ 630.257590] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.257649] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.259572] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:40 BXT-2 kernel: [ 630.260466] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:40 BXT-2 kernel: [ 630.260512] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.260555] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:40 BXT-2 kernel: [ 630.260597] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:40 BXT-2 kernel: [ 630.261097] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:40 BXT-2 kernel: [ 630.261141] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:40 BXT-2 kernel: [ 630.266813] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:40 BXT-2 kernel: [ 630.266881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:40 BXT-2 kernel: [ 630.266888] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266893] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266899] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266904] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266909] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266914] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266919] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.266924] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266929] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.266934] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.266939] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:40 BXT-2 kernel: [ 630.266944] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:40 BXT-2 kernel: [ 630.268557] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:40 BXT-2 kernel: [ 630.290456] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:40 BXT-2 kernel: [ 630.290619] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.290815] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:40 BXT-2 kernel: [ 630.290871] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:40 BXT-2 kernel: [ 630.290966] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:40 BXT-2 kernel: [ 630.303461] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:40 BXT-2 kernel: [ 630.303575] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.303664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.303711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.303754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.303797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.303840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.303883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.303925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.303968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.304010] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.304058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.304103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.304148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.310882] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:40 BXT-2 kernel: [ 630.311384] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.313600] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.313732] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:40 BXT-2 kernel: [ 630.313776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:40 BXT-2 kernel: [ 630.313821] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:40 BXT-2 kernel: [ 630.313866] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:40 BXT-2 kernel: [ 630.313908] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:40 BXT-2 kernel: [ 630.314062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.314105] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:40 BXT-2 kernel: [ 630.314148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.314255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:40 BXT-2 kernel: [ 630.314300] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.314354] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:40 BXT-2 kernel: [ 630.314368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.314410] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:40 BXT-2 kernel: [ 630.314416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.314459] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.314505] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:40 BXT-2 kernel: [ 630.314550] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:40 BXT-2 kernel: [ 630.314594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:40 BXT-2 kernel: [ 630.314637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.314683] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:40 BXT-2 kernel: [ 630.314727] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:40 BXT-2 kernel: [ 630.314772] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:32:40 BXT-2 kernel: [ 630.314815] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:32:40 BXT-2 kernel: [ 630.314858] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.314901] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.314944] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.314990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.315043] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.315085] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.316863] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.328525] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.328637] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.328691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.328735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.328778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.328821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.328864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.328910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.328953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.328996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.329039] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.329086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.329131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.329176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.329780] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.329823] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.331345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.331389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.331433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:40 BXT-2 kernel: [ 630.350534] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:40 BXT-2 kernel: [ 630.350582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:40 BXT-2 kernel: [ 630.368833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:40 BXT-2 kernel: [ 630.370932] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:40 BXT-2 kernel: [ 630.371924] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.371988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.372031] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:40 BXT-2 kernel: [ 630.372087] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:40 BXT-2 kernel: [ 630.388822] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.388892] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.389064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.405431] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:40 BXT-2 kernel: [ 630.472581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.472703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.472758] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:40 BXT-2 kernel: [ 630.472853] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.490502] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.490615] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.490704] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.491022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.491065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.491112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.491155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.491251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.491295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.491338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.491383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.491426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.491470] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.491520] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.491565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.491610] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.491672] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.491716] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.491769] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.491831] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.491876] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.491919] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:40 BXT-2 kernel: [ 630.491959] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:40 BXT-2 kernel: [ 630.492541] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.493613] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:40 BXT-2 kernel: [ 630.511414] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.511475] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.511606] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:40 BXT-2 kernel: [ 630.511650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:40 BXT-2 kernel: [ 630.511695] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:40 BXT-2 kernel: [ 630.511739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:40 BXT-2 kernel: [ 630.511781] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:40 BXT-2 kernel: [ 630.511825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.511868] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:40 BXT-2 kernel: [ 630.511911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.511954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:40 BXT-2 kernel: [ 630.511996] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.512039] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:40 BXT-2 kernel: [ 630.512045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.512087] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:40 BXT-2 kernel: [ 630.512093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.512136] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.512179] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:40 BXT-2 kernel: [ 630.512407] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:40 BXT-2 kernel: [ 630.512450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:40 BXT-2 kernel: [ 630.512492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.512537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:40 BXT-2 kernel: [ 630.512579] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:40 BXT-2 kernel: [ 630.512622] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.512665] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.512708] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.512751] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.512815] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.512868] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.512912] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.513609] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.513648] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.513936] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:40 BXT-2 kernel: [ 630.513989] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.514030] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.514086] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.515576] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.515900] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.515944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.515988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.516030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.516073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.516117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.516159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.516351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.516394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.516644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.516693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.516738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.516812] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.516855] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.518736] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.518781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.518825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:40 BXT-2 kernel: [ 630.538273] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:40 BXT-2 kernel: [ 630.538321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:40 BXT-2 kernel: [ 630.559263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:40 BXT-2 kernel: [ 630.561367] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:40 BXT-2 kernel: [ 630.562441] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.562510] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.562553] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:40 BXT-2 kernel: [ 630.562609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:40 BXT-2 kernel: [ 630.579321] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.579380] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.579552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.662871] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.662998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.663053] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:40 BXT-2 kernel: [ 630.663137] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.679452] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.679565] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.679657] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.679977] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.680021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.680068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.680111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.680154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.680243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.680286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.680329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.680372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.680415] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:40 BXT-2 kernel: [ 630.680463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.680508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.680553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.680614] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.680657] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.680711] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.680773] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.680817] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.680860] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:40 BXT-2 kernel: [ 630.680899] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:40 BXT-2 kernel: [ 630.682067] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.683245] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:40 BXT-2 kernel: [ 630.705056] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.705125] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.705705] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:40 BXT-2 kernel: [ 630.705751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:40 BXT-2 kernel: [ 630.705796] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:40 BXT-2 kernel: [ 630.705840] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:40 BXT-2 kernel: [ 630.705882] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.705927] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.705971] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:40 BXT-2 kernel: [ 630.706013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.706057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:40 BXT-2 kernel: [ 630.706099] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.706141] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:40 BXT-2 kernel: [ 630.706880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.706938] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:40 BXT-2 kernel: [ 630.706944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.706988] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.707031] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:40 BXT-2 kernel: [ 630.707073] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:40 BXT-2 kernel: [ 630.707116] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:40 BXT-2 kernel: [ 630.707158] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.707959] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:40 BXT-2 kernel: [ 630.708002] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:40 BXT-2 kernel: [ 630.708047] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.708090] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.708133] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.708177] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.708788] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.708844] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.708888] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.709791] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.709831] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.710120] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:40 BXT-2 kernel: [ 630.710173] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.710492] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.710832] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.711093] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.711603] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.711650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.711694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.711737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.711780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.711823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.711866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.711909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.711952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.711995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.712043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.712088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.712162] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.712499] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.713955] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.714000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.714045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:40 BXT-2 kernel: [ 630.715073] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:40 BXT-2 kernel: [ 630.715120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:40 BXT-2 kernel: [ 630.716178] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:40 BXT-2 kernel: [ 630.718307] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:40 BXT-2 kernel: [ 630.719391] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.736324] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.736383] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.736555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.819830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.819967] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.837564] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.837677] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.837767] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.838084] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.838128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.838171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.838259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.838303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.838350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.838397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.838441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.838485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.838528] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.838577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.838623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.838668] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.838736] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.838779] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.838834] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.838897] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.838942] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.838987] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:40 BXT-2 kernel: [ 630.839027] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:40 BXT-2 kernel: [ 630.839605] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.840640] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:40 BXT-2 kernel: [ 630.862754] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.862820] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.862947] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:40 BXT-2 kernel: [ 630.862991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:40 BXT-2 kernel: [ 630.863035] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:40 BXT-2 kernel: [ 630.863079] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:40 BXT-2 kernel: [ 630.863121] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:40 BXT-2 kernel: [ 630.863165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.863261] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:40 BXT-2 kernel: [ 630.863306] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.863352] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:40 BXT-2 kernel: [ 630.863395] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.863437] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:40 BXT-2 kernel: [ 630.863446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.863488] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:40 BXT-2 kernel: [ 630.863498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.863541] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:40 BXT-2 kernel: [ 630.863587] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:40 BXT-2 kernel: [ 630.863629] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:40 BXT-2 kernel: [ 630.863672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:40 BXT-2 kernel: [ 630.863714] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:40 BXT-2 kernel: [ 630.863759] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:40 BXT-2 kernel: [ 630.863801] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:40 BXT-2 kernel: [ 630.863844] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.863887] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.863930] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.863974] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:40 BXT-2 kernel: [ 630.864039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.864094] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.864137] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.864796] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.864835] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.865128] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:40 BXT-2 kernel: [ 630.865214] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.865255] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.865311] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.865997] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.866429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.866479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.866524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.866824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.866867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.866910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.866953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.866997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.867040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.867083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.867132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.867177] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.867473] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.867517] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.868963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.869007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:40 BXT-2 kernel: [ 630.869051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:40 BXT-2 kernel: [ 630.869905] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:40 BXT-2 kernel: [ 630.869950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:40 BXT-2 kernel: [ 630.871154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:40 BXT-2 kernel: [ 630.873292] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:40 BXT-2 kernel: [ 630.874362] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.891260] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.891318] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.891490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.974806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.974943] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:40 BXT-2 kernel: [ 630.992525] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:40 BXT-2 kernel: [ 630.992639] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.992728] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.993047] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:40 BXT-2 kernel: [ 630.993093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:40 BXT-2 kernel: [ 630.993137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.993180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.993297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.993340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:40 BXT-2 kernel: [ 630.993389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:40 BXT-2 kernel: [ 630.993432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:40 BXT-2 kernel: [ 630.993474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:40 BXT-2 kernel: [ 630.993518] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:40 BXT-2 kernel: [ 630.993565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:40 BXT-2 kernel: [ 630.993612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:40 BXT-2 kernel: [ 630.993657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:40 BXT-2 kernel: [ 630.993725] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:40 BXT-2 kernel: [ 630.993769] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.993825] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:40 BXT-2 kernel: [ 630.993888] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:40 BXT-2 kernel: [ 630.993933] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:40 BXT-2 kernel: [ 630.993978] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:40 BXT-2 kernel: [ 630.994017] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:40 BXT-2 kernel: [ 630.994597] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:40 BXT-2 kernel: [ 630.995774] [drm:i915_reset_and_wakeup [i915]] resetting chip >May 24 03:32:40 BXT-2 kernel: [ 630.995874] drm/i915: Resetting chip after gpu hang >May 24 03:32:41 BXT-2 kernel: [ 630.999099] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:32:41 BXT-2 kernel: [ 630.999170] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:32:41 BXT-2 kernel: [ 630.999338] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:32:41 BXT-2 kernel: [ 630.999462] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:32:41 BXT-2 kernel: [ 630.999585] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:32:41 BXT-2 kernel: [ 631.000834] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:41 BXT-2 kernel: [ 631.017520] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.017585] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.017718] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:41 BXT-2 kernel: [ 631.017762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:41 BXT-2 kernel: [ 631.017807] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:41 BXT-2 kernel: [ 631.017851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:41 BXT-2 kernel: [ 631.017893] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:41 BXT-2 kernel: [ 631.017937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.017980] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:41 BXT-2 kernel: [ 631.018023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.018066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:41 BXT-2 kernel: [ 631.018108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.018150] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:41 BXT-2 kernel: [ 631.018702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.018757] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:41 BXT-2 kernel: [ 631.018763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.018806] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.018849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:41 BXT-2 kernel: [ 631.018892] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:41 BXT-2 kernel: [ 631.018934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:41 BXT-2 kernel: [ 631.018977] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.019022] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:41 BXT-2 kernel: [ 631.019064] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:41 BXT-2 kernel: [ 631.019107] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.019150] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.019602] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.019645] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.019712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.019765] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.019808] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.021078] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.021119] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.021587] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:41 BXT-2 kernel: [ 631.022029] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.022070] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.022127] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.022593] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.022916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.022960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.023004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.023046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.023089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.023132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.023175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.023244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.023287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.023329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.023376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.023421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.023494] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.023538] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.024991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.025036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.025080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:41 BXT-2 kernel: [ 631.044188] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:41 BXT-2 kernel: [ 631.044276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:41 BXT-2 kernel: [ 631.063189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:41 BXT-2 kernel: [ 631.065275] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:41 BXT-2 kernel: [ 631.066611] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.066710] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.066753] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:41 BXT-2 kernel: [ 631.066809] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:41 BXT-2 kernel: [ 631.083710] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.083768] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.083939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.167090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.167260] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.167320] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:41 BXT-2 kernel: [ 631.167408] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.185466] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.185579] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.185668] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.185991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.186034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.186081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.186123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.186166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.186261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.186313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.186358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.186403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.186450] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.186499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.186547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.186594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.186655] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.186699] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.186753] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.186817] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.186862] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.186906] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:41 BXT-2 kernel: [ 631.186946] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:41 BXT-2 kernel: [ 631.187531] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.188538] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:41 BXT-2 kernel: [ 631.211098] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.211202] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.211337] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:41 BXT-2 kernel: [ 631.211381] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:41 BXT-2 kernel: [ 631.211426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:41 BXT-2 kernel: [ 631.211470] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:41 BXT-2 kernel: [ 631.211512] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:41 BXT-2 kernel: [ 631.211559] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.211602] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:41 BXT-2 kernel: [ 631.211645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.211689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:41 BXT-2 kernel: [ 631.211732] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.211775] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:41 BXT-2 kernel: [ 631.211782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.211825] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:41 BXT-2 kernel: [ 631.211831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.211876] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.211919] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:41 BXT-2 kernel: [ 631.211962] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:41 BXT-2 kernel: [ 631.212006] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:41 BXT-2 kernel: [ 631.212049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.212094] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:41 BXT-2 kernel: [ 631.212137] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:41 BXT-2 kernel: [ 631.212181] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.212249] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.212293] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.212336] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.212402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.212456] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.212500] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.213223] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.213262] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.213551] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:41 BXT-2 kernel: [ 631.213605] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.213645] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.213702] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.213950] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.214284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.214329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.214372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.214416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.214459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.214502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.214545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.214589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.214633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.214677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.214725] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.214770] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.214847] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.214891] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.216321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.216365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.216410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:41 BXT-2 kernel: [ 631.235550] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:41 BXT-2 kernel: [ 631.235598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:41 BXT-2 kernel: [ 631.255558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:41 BXT-2 kernel: [ 631.257663] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:41 BXT-2 kernel: [ 631.258719] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.258803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.258846] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD >May 24 03:32:41 BXT-2 kernel: [ 631.258902] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:41 BXT-2 kernel: [ 631.275632] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.275690] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.275862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.359130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.359305] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.359360] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:41 BXT-2 kernel: [ 631.359449] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.377533] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.377646] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.377736] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.378067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.378112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.378160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.378266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.378309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.378355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.378398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.378441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.378484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.378527] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.378577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.378623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.378670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.378735] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.378779] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.378843] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.378908] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.378954] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.378997] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:41 BXT-2 kernel: [ 631.379036] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:41 BXT-2 kernel: [ 631.379628] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.380974] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:41 BXT-2 kernel: [ 631.403853] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.403902] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.404035] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:41 BXT-2 kernel: [ 631.404078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:41 BXT-2 kernel: [ 631.404123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:41 BXT-2 kernel: [ 631.404168] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:41 BXT-2 kernel: [ 631.404583] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:41 BXT-2 kernel: [ 631.404630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.404675] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:41 BXT-2 kernel: [ 631.404718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.404761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:41 BXT-2 kernel: [ 631.404804] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.404846] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:41 BXT-2 kernel: [ 631.404855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.404897] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:41 BXT-2 kernel: [ 631.404903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.404946] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.404988] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:41 BXT-2 kernel: [ 631.405031] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:41 BXT-2 kernel: [ 631.405074] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:41 BXT-2 kernel: [ 631.405116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.405161] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:41 BXT-2 kernel: [ 631.405339] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:41 BXT-2 kernel: [ 631.405383] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.405426] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.405470] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.405513] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.405580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.405634] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.405677] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.406351] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.406391] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.406680] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:41 BXT-2 kernel: [ 631.406734] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.406774] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.406832] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.407091] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.407599] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.407646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.407690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.407734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.407776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.407819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.407862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.407905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.407948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.407991] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.408039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.408085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.408162] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.408542] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.410710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.410757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.410802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:41 BXT-2 kernel: [ 631.411847] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:41 BXT-2 kernel: [ 631.411896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:41 BXT-2 kernel: [ 631.412979] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:41 BXT-2 kernel: [ 631.415084] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:41 BXT-2 kernel: [ 631.416145] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.433120] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.433180] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.433654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.516608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.516744] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.534474] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.534590] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.534681] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.535109] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.535155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.535251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.535294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.535337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.535379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.535429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.535472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.535515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.535558] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.535605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.535651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.535696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.535760] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.535803] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.535857] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.535920] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.535966] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.536009] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:41 BXT-2 kernel: [ 631.536048] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:41 BXT-2 kernel: [ 631.536674] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.538759] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:41 BXT-2 kernel: [ 631.558726] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.558790] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.558918] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:41 BXT-2 kernel: [ 631.558962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:41 BXT-2 kernel: [ 631.559006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:41 BXT-2 kernel: [ 631.559050] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:41 BXT-2 kernel: [ 631.559092] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:41 BXT-2 kernel: [ 631.559136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.559179] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:41 BXT-2 kernel: [ 631.559656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.559700] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:41 BXT-2 kernel: [ 631.559742] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.559784] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:41 BXT-2 kernel: [ 631.559793] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.559835] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:41 BXT-2 kernel: [ 631.559841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.559884] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.559927] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:41 BXT-2 kernel: [ 631.559970] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:41 BXT-2 kernel: [ 631.560012] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:41 BXT-2 kernel: [ 631.560054] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.560099] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:41 BXT-2 kernel: [ 631.560141] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:41 BXT-2 kernel: [ 631.560714] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.560757] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.560800] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.560843] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.560911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.560965] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.561008] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.561646] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.561686] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.561974] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:41 BXT-2 kernel: [ 631.562028] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.562068] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.562124] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.562700] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.563022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.563067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.563110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.563154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.563539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.563592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.563644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.563701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.563754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.563807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.563875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.563932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.564027] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.564079] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.578421] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.578467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.578512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:41 BXT-2 kernel: [ 631.579573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.579619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.580477] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:41 BXT-2 kernel: [ 631.580525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:41 BXT-2 kernel: [ 631.581876] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:41 BXT-2 kernel: [ 631.583275] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:41 BXT-2 kernel: [ 631.584482] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.601424] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.601483] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.601654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.684915] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.685046] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.702559] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.702673] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.702763] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.703083] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.703127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.703171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.703297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.703341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.703384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.703432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.703475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.703518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.703562] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.703609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.703655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.703701] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.703764] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.703807] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.703861] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.703924] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.703968] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.704011] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:41 BXT-2 kernel: [ 631.704050] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:41 BXT-2 kernel: [ 631.704635] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.740143] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:41 BXT-2 kernel: [ 631.740238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:41 BXT-2 kernel: [ 631.740283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:41 BXT-2 kernel: [ 631.740327] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:41 BXT-2 kernel: [ 631.740368] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:41 BXT-2 kernel: [ 631.740412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.740455] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:41 BXT-2 kernel: [ 631.740497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.740540] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:41 BXT-2 kernel: [ 631.740582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.740623] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:41 BXT-2 kernel: [ 631.740630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.740671] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:41 BXT-2 kernel: [ 631.740676] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.740719] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.740761] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:41 BXT-2 kernel: [ 631.740803] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:41 BXT-2 kernel: [ 631.740845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:41 BXT-2 kernel: [ 631.740887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.740932] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:41 BXT-2 kernel: [ 631.740974] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:41 BXT-2 kernel: [ 631.741016] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.741059] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.741101] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.741143] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.741239] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:41 BXT-2 kernel: [ 631.741281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:41 BXT-2 kernel: [ 631.741325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:41 BXT-2 kernel: [ 631.741368] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:41 BXT-2 kernel: [ 631.741410] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:41 BXT-2 kernel: [ 631.741453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.741497] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:41 BXT-2 kernel: [ 631.741539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.741582] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:41 BXT-2 kernel: [ 631.741623] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.741664] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:41 BXT-2 kernel: [ 631.741672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.741713] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:41 BXT-2 kernel: [ 631.741718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.741760] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:41 BXT-2 kernel: [ 631.741802] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:41 BXT-2 kernel: [ 631.741844] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:41 BXT-2 kernel: [ 631.741886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:41 BXT-2 kernel: [ 631.741928] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:41 BXT-2 kernel: [ 631.741972] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:41 BXT-2 kernel: [ 631.742013] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:41 BXT-2 kernel: [ 631.742056] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.742098] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.742140] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.742263] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:41 BXT-2 kernel: [ 631.742313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.742370] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.742414] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:41 BXT-2 kernel: [ 631.742458] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.742500] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.742656] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:41 BXT-2 kernel: [ 631.742693] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:41 BXT-2 kernel: [ 631.742987] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:41 BXT-2 kernel: [ 631.743044] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.743084] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:41 BXT-2 kernel: [ 631.743141] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:41 BXT-2 kernel: [ 631.743463] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.743788] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:41 BXT-2 kernel: [ 631.743832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.743875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.743917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.743959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.744001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:41 BXT-2 kernel: [ 631.744043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:41 BXT-2 kernel: [ 631.744085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:41 BXT-2 kernel: [ 631.744127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:41 BXT-2 kernel: [ 631.744170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:41 BXT-2 kernel: [ 631.744282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.744328] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.744404] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:41 BXT-2 kernel: [ 631.744446] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.745904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.745947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.745991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:41 BXT-2 kernel: [ 631.772881] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:41 BXT-2 kernel: [ 631.772926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:41 BXT-2 kernel: [ 631.790988] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:41 BXT-2 kernel: [ 631.793080] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:41 BXT-2 kernel: [ 631.794271] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:41 BXT-2 kernel: [ 631.794382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:41 BXT-2 kernel: [ 631.794424] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:41 BXT-2 kernel: [ 631.794482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:41 BXT-2 kernel: [ 631.794663] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:41 BXT-2 kernel: [ 631.794706] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.796123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.796164] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.796243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:41 BXT-2 kernel: [ 631.797014] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.797055] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:41 BXT-2 kernel: [ 631.797788] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:41 BXT-2 kernel: [ 631.797830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:41 BXT-2 kernel: [ 631.798872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:41 BXT-2 kernel: [ 631.800953] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:41 BXT-2 kernel: [ 631.802127] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:41 BXT-2 kernel: [ 631.818981] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:41 BXT-2 kernel: [ 631.819034] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:41 BXT-2 kernel: [ 631.819292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:41 BXT-2 kernel: [ 631.820237] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:41 BXT-2 kernel: [ 631.820289] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:41 BXT-2 kernel: [ 631.820463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:41 BXT-2 kernel: [ 631.820815] Console: switching to colour frame buffer device 240x67 >May 24 03:32:42 BXT-2 kernel: [ 632.165399] Console: switching to colour dummy device 80x25 >May 24 03:32:42 BXT-2 kernel: [ 632.186751] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.186819] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.187557] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:42 BXT-2 kernel: [ 632.188531] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:42 BXT-2 kernel: [ 632.188579] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.188622] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.188664] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.189171] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:42 BXT-2 kernel: [ 632.190059] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:42 BXT-2 kernel: [ 632.191083] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.192352] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.193671] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.195099] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.196362] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.197652] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.198902] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.200172] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.201404] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.202794] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.204173] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.205559] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.207000] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.208412] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.209801] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.211186] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.212553] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.213886] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.215189] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.216439] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.217705] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.219105] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.220491] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.221879] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.223272] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.224725] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.226110] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.227495] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.228874] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.229673] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:42 BXT-2 kernel: [ 632.230436] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.230443] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:42 BXT-2 kernel: [ 632.230449] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:42 BXT-2 kernel: [ 632.230453] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:42 BXT-2 kernel: [ 632.230682] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:42 BXT-2 kernel: [ 632.230689] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230695] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230700] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:42 BXT-2 kernel: [ 632.230705] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:42 BXT-2 kernel: [ 632.230710] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230715] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:42 BXT-2 kernel: [ 632.230720] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:42 BXT-2 kernel: [ 632.230725] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230730] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230735] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:42 BXT-2 kernel: [ 632.230740] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230745] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230750] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230755] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230760] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230765] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230770] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230776] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230781] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230786] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230791] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230796] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230801] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230806] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230811] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230816] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.230821] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230826] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230831] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230836] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230841] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230846] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230851] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.230856] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:42 BXT-2 kernel: [ 632.230942] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.231001] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.232912] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:42 BXT-2 kernel: [ 632.233803] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:42 BXT-2 kernel: [ 632.233848] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.233891] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:42 BXT-2 kernel: [ 632.233933] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:42 BXT-2 kernel: [ 632.234459] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:42 BXT-2 kernel: [ 632.234503] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:42 BXT-2 kernel: [ 632.239285] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:42 BXT-2 kernel: [ 632.239345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:42 BXT-2 kernel: [ 632.239352] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239357] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239362] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239367] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239372] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239377] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239382] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.239388] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239393] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.239398] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.239403] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.239408] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:42 BXT-2 kernel: [ 632.246798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.246872] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.247971] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:42 BXT-2 kernel: [ 632.249364] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:42 BXT-2 kernel: [ 632.249414] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.249458] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.249501] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.249997] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:42 BXT-2 kernel: [ 632.251230] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:42 BXT-2 kernel: [ 632.252094] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.253391] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.255082] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.256356] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.258038] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.259316] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.260599] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.262186] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.263619] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.265337] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.266930] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.268320] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.269723] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.271107] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.272493] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.273892] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.275807] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.277068] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.278319] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.279565] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.280836] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.282222] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.283592] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.285025] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.286416] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.287800] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.289186] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.290559] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.291991] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:42 BXT-2 kernel: [ 632.292787] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:42 BXT-2 kernel: [ 632.293600] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.293607] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:42 BXT-2 kernel: [ 632.293612] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:42 BXT-2 kernel: [ 632.293616] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:42 BXT-2 kernel: [ 632.293851] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:42 BXT-2 kernel: [ 632.293857] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293863] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293868] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:42 BXT-2 kernel: [ 632.293873] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:42 BXT-2 kernel: [ 632.293878] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293883] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:42 BXT-2 kernel: [ 632.293888] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:42 BXT-2 kernel: [ 632.293893] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293898] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293903] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:42 BXT-2 kernel: [ 632.293908] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293913] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293918] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293923] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293928] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293933] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293938] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293943] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293948] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293954] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293959] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293964] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293969] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293974] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293979] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293984] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.293989] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293994] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.293999] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.294004] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.294009] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.294014] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.294019] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.294024] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:42 BXT-2 kernel: [ 632.295788] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.295849] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.296438] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:42 BXT-2 kernel: [ 632.297360] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:42 BXT-2 kernel: [ 632.297405] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.297448] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:42 BXT-2 kernel: [ 632.297490] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:42 BXT-2 kernel: [ 632.297973] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:42 BXT-2 kernel: [ 632.298015] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:42 BXT-2 kernel: [ 632.302983] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:42 BXT-2 kernel: [ 632.303047] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:42 BXT-2 kernel: [ 632.303054] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303059] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303065] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303070] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303075] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303080] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303085] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.303090] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303095] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.303100] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.303105] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:42 BXT-2 kernel: [ 632.303110] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:42 BXT-2 kernel: [ 632.304786] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:42 BXT-2 kernel: [ 632.320136] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:42 BXT-2 kernel: [ 632.320314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.320499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:42 BXT-2 kernel: [ 632.320554] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:42 BXT-2 kernel: [ 632.320645] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:42 BXT-2 kernel: [ 632.328536] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:42 BXT-2 kernel: [ 632.328648] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.328737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.328790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.328832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.328875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.328918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.328961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.329003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.329046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.329089] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.329136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.329692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.329740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.335670] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:42 BXT-2 kernel: [ 632.336446] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:42 BXT-2 kernel: [ 632.336603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.336776] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:42 BXT-2 kernel: [ 632.352524] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:42 BXT-2 kernel: [ 632.352635] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.352723] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.353045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.353090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.353133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.353176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.353565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.353609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.353658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.353701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.353743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.353786] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.353833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.353879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.353923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.353985] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.354028] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.354081] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.354141] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:42 BXT-2 kernel: [ 632.354685] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.354729] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:42 BXT-2 kernel: [ 632.354767] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:42 BXT-2 kernel: [ 632.355932] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.357171] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.357220] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.357339] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:42 BXT-2 kernel: [ 632.357384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:42 BXT-2 kernel: [ 632.357429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:42 BXT-2 kernel: [ 632.357472] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:42 BXT-2 kernel: [ 632.357514] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:42 BXT-2 kernel: [ 632.357557] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.357600] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:42 BXT-2 kernel: [ 632.357643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.357686] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:42 BXT-2 kernel: [ 632.357728] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.357770] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:42 BXT-2 kernel: [ 632.357777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.357818] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:42 BXT-2 kernel: [ 632.357824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.357867] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.357910] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:42 BXT-2 kernel: [ 632.357952] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:42 BXT-2 kernel: [ 632.357995] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:42 BXT-2 kernel: [ 632.358037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.358082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:42 BXT-2 kernel: [ 632.358123] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:42 BXT-2 kernel: [ 632.358166] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.359045] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.359088] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.359154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.359399] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.359444] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.360023] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.360061] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.360568] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:42 BXT-2 kernel: [ 632.360971] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.361012] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.361068] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.361552] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.361871] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.361915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.361958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.362001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.362043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.362087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.362129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.362172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.362595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.362638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.362687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.362731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.362806] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.362849] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.364514] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.364558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.364602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:42 BXT-2 kernel: [ 632.383547] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:42 BXT-2 kernel: [ 632.383595] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:42 BXT-2 kernel: [ 632.401731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:42 BXT-2 kernel: [ 632.403847] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:42 BXT-2 kernel: [ 632.404931] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.405031] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.405074] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:42 BXT-2 kernel: [ 632.405130] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:42 BXT-2 kernel: [ 632.421835] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.421894] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.422068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.505364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.505485] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.505539] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:42 BXT-2 kernel: [ 632.505624] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.523492] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.523606] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.523687] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.524008] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.524052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.524100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.524142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.524242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.524286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.524329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.524371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.524414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.524458] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.524506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.524552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.524597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.524661] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.524705] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.524759] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.524820] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.524864] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.524908] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:42 BXT-2 kernel: [ 632.524947] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:42 BXT-2 kernel: [ 632.525543] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.528592] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:42 BXT-2 kernel: [ 632.552478] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.552523] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.552647] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:42 BXT-2 kernel: [ 632.552691] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:42 BXT-2 kernel: [ 632.552736] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:42 BXT-2 kernel: [ 632.552780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:42 BXT-2 kernel: [ 632.552821] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:42 BXT-2 kernel: [ 632.552866] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.552908] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:42 BXT-2 kernel: [ 632.552951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.552994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:42 BXT-2 kernel: [ 632.553037] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.553078] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:42 BXT-2 kernel: [ 632.553085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.553127] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:42 BXT-2 kernel: [ 632.553133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.553176] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.553883] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:42 BXT-2 kernel: [ 632.553926] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:42 BXT-2 kernel: [ 632.553969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:42 BXT-2 kernel: [ 632.554011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.554056] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:42 BXT-2 kernel: [ 632.554098] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:42 BXT-2 kernel: [ 632.554142] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.554470] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.554513] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.554580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.554634] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.554678] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.555473] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.555512] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.555807] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:42 BXT-2 kernel: [ 632.555862] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.555902] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.555959] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.556571] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.556919] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.556963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.557006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.557049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.557092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.557135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.557178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.557575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.557618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.557662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.557711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.557755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.557832] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.557875] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.559571] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.559615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.559659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:42 BXT-2 kernel: [ 632.578713] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:42 BXT-2 kernel: [ 632.578759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:42 BXT-2 kernel: [ 632.597761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:42 BXT-2 kernel: [ 632.599860] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:42 BXT-2 kernel: [ 632.600885] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.600954] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.600997] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:42 BXT-2 kernel: [ 632.601052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:42 BXT-2 kernel: [ 632.617755] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.617813] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.617984] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.701320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.701439] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.701494] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:42 BXT-2 kernel: [ 632.701582] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.719591] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.719703] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.719784] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.720110] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.720153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.720253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.720295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.720341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.720384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.720427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.720470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.720513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.720556] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:42 BXT-2 kernel: [ 632.720604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.720651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.720696] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.720762] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.720806] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.720860] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.720922] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.720966] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.721010] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:42 BXT-2 kernel: [ 632.721049] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:42 BXT-2 kernel: [ 632.721648] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.723210] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:42 BXT-2 kernel: [ 632.741302] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.741370] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.741500] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:42 BXT-2 kernel: [ 632.741544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:42 BXT-2 kernel: [ 632.741589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:42 BXT-2 kernel: [ 632.741633] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:42 BXT-2 kernel: [ 632.741676] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.741720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.741764] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:42 BXT-2 kernel: [ 632.741807] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.741850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:42 BXT-2 kernel: [ 632.741893] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.741934] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:42 BXT-2 kernel: [ 632.741943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.741985] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:42 BXT-2 kernel: [ 632.741991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.742034] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.742077] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:42 BXT-2 kernel: [ 632.742119] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:42 BXT-2 kernel: [ 632.742162] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:42 BXT-2 kernel: [ 632.742984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.743031] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:42 BXT-2 kernel: [ 632.743073] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:42 BXT-2 kernel: [ 632.743118] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.743161] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.743459] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.743529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.743583] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.743626] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.744532] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.744585] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.744922] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:42 BXT-2 kernel: [ 632.745006] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.745056] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.745130] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.745825] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.746162] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.746249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.746292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.746335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.746378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.746421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.746465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.746508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.746552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.746595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.746646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.746691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.746767] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.746811] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.748992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.749038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.749082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:42 BXT-2 kernel: [ 632.749993] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:42 BXT-2 kernel: [ 632.750041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:42 BXT-2 kernel: [ 632.751266] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:42 BXT-2 kernel: [ 632.753372] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:42 BXT-2 kernel: [ 632.754396] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.771303] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.771361] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.771531] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.854824] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.854955] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.872608] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.872721] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.872802] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.873123] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.873168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.873268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.873312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.873357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.873401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.873449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.873492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.873535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.873579] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.873626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.873672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.873717] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.873778] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.873822] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.873876] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.873937] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.873981] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.874025] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:42 BXT-2 kernel: [ 632.874064] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:42 BXT-2 kernel: [ 632.874665] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.876180] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:42 BXT-2 kernel: [ 632.893713] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.893776] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.893904] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:42 BXT-2 kernel: [ 632.893947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:42 BXT-2 kernel: [ 632.893992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:42 BXT-2 kernel: [ 632.894036] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:42 BXT-2 kernel: [ 632.894077] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:42 BXT-2 kernel: [ 632.894121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.894165] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:42 BXT-2 kernel: [ 632.894624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.894667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:42 BXT-2 kernel: [ 632.894710] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.894751] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:42 BXT-2 kernel: [ 632.894760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.894801] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:42 BXT-2 kernel: [ 632.894807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.894850] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:42 BXT-2 kernel: [ 632.894893] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:42 BXT-2 kernel: [ 632.894936] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:42 BXT-2 kernel: [ 632.894978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:42 BXT-2 kernel: [ 632.895020] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:42 BXT-2 kernel: [ 632.895065] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:42 BXT-2 kernel: [ 632.895106] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:42 BXT-2 kernel: [ 632.895150] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.895734] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.895777] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:42 BXT-2 kernel: [ 632.895845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.895899] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.895942] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.896783] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:42 BXT-2 kernel: [ 632.896822] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:42 BXT-2 kernel: [ 632.897110] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:42 BXT-2 kernel: [ 632.897163] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.897407] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:42 BXT-2 kernel: [ 632.897465] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:42 BXT-2 kernel: [ 632.897748] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.898189] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:42 BXT-2 kernel: [ 632.898488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:42 BXT-2 kernel: [ 632.898532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.898575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.898618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.898661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:42 BXT-2 kernel: [ 632.898703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:42 BXT-2 kernel: [ 632.898746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:42 BXT-2 kernel: [ 632.898789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:42 BXT-2 kernel: [ 632.898832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:42 BXT-2 kernel: [ 632.898881] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:42 BXT-2 kernel: [ 632.898926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.899001] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:42 BXT-2 kernel: [ 632.899044] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:42 BXT-2 kernel: [ 632.900964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.901008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:42 BXT-2 kernel: [ 632.901052] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:42 BXT-2 kernel: [ 632.901890] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:42 BXT-2 kernel: [ 632.901935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:42 BXT-2 kernel: [ 632.903002] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:42 BXT-2 kernel: [ 632.905107] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:42 BXT-2 kernel: [ 632.906290] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:42 BXT-2 kernel: [ 632.923170] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:42 BXT-2 kernel: [ 632.923255] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:42 BXT-2 kernel: [ 632.923429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.006679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.006808] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.024486] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:43 BXT-2 kernel: [ 633.024599] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.024681] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.025273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.025322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.025366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.025409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.025452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.025495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.025545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.025588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.025632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.025676] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.025724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.025771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.025816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.025882] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:43 BXT-2 kernel: [ 633.025925] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.025980] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.026042] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:43 BXT-2 kernel: [ 633.026086] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:43 BXT-2 kernel: [ 633.026129] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:43 BXT-2 kernel: [ 633.026168] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:43 BXT-2 kernel: [ 633.026769] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:43 BXT-2 kernel: [ 633.055162] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:43 BXT-2 kernel: [ 633.055548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:43 BXT-2 kernel: [ 633.055593] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:43 BXT-2 kernel: [ 633.055635] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:43 BXT-2 kernel: [ 633.055676] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:43 BXT-2 kernel: [ 633.055719] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.055761] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:43 BXT-2 kernel: [ 633.055803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.055845] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:43 BXT-2 kernel: [ 633.055885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.055926] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:43 BXT-2 kernel: [ 633.055934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.055974] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:43 BXT-2 kernel: [ 633.055979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.056020] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.056062] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:43 BXT-2 kernel: [ 633.056103] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:43 BXT-2 kernel: [ 633.056144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:43 BXT-2 kernel: [ 633.056202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.056245] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:43 BXT-2 kernel: [ 633.056286] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:43 BXT-2 kernel: [ 633.056328] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.056369] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.056410] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.056451] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.056497] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:43 BXT-2 kernel: [ 633.056538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:43 BXT-2 kernel: [ 633.056581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:43 BXT-2 kernel: [ 633.056623] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:43 BXT-2 kernel: [ 633.056663] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.056705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.056747] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:43 BXT-2 kernel: [ 633.056787] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.056829] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:43 BXT-2 kernel: [ 633.056872] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.056912] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:43 BXT-2 kernel: [ 633.056917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.056957] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:43 BXT-2 kernel: [ 633.056962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.057004] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.057045] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:43 BXT-2 kernel: [ 633.057086] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:43 BXT-2 kernel: [ 633.057127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:43 BXT-2 kernel: [ 633.057168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.057238] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:43 BXT-2 kernel: [ 633.057278] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:43 BXT-2 kernel: [ 633.057321] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.057362] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.057403] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.057445] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.057488] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.057540] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.057583] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:43 BXT-2 kernel: [ 633.057625] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.057666] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:43 BXT-2 kernel: [ 633.057792] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:43 BXT-2 kernel: [ 633.057827] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:43 BXT-2 kernel: [ 633.058114] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:43 BXT-2 kernel: [ 633.058168] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.058257] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.058312] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:43 BXT-2 kernel: [ 633.058601] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.058923] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.058965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.059007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.059048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.059090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.059131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.059172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.059233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.059274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.059316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.059361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.059404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.059476] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:43 BXT-2 kernel: [ 633.059518] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.060937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.060977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.061021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:43 BXT-2 kernel: [ 633.080025] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:43 BXT-2 kernel: [ 633.080067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:43 BXT-2 kernel: [ 633.098231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:43 BXT-2 kernel: [ 633.100308] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:43 BXT-2 kernel: [ 633.101492] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:43 BXT-2 kernel: [ 633.101573] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.101614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:43 BXT-2 kernel: [ 633.101671] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:43 BXT-2 kernel: [ 633.102163] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:43 BXT-2 kernel: [ 633.102251] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.103674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.103717] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.103760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:43 BXT-2 kernel: [ 633.104542] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.104584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.105314] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:43 BXT-2 kernel: [ 633.105357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:43 BXT-2 kernel: [ 633.106436] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:43 BXT-2 kernel: [ 633.108616] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:43 BXT-2 kernel: [ 633.109869] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:43 BXT-2 kernel: [ 633.126770] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.126824] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:43 BXT-2 kernel: [ 633.127002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.127227] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.127279] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:43 BXT-2 kernel: [ 633.127451] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.127822] Console: switching to colour frame buffer device 240x67 >May 24 03:32:43 BXT-2 kernel: [ 633.457832] Console: switching to colour dummy device 80x25 >May 24 03:32:43 BXT-2 kernel: [ 633.475764] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.475831] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.476384] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:43 BXT-2 kernel: [ 633.477263] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:43 BXT-2 kernel: [ 633.477309] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.477354] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.477397] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.477888] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:43 BXT-2 kernel: [ 633.478282] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:43 BXT-2 kernel: [ 633.479258] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.480574] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.481918] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.483173] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.484412] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.485669] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.486924] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.488190] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.489448] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.490840] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.492220] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.493592] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.494946] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.496323] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.497713] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.499091] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.500466] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.501720] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.502966] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.504214] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.505445] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.506827] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.508213] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.509580] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.510942] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.512318] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.513687] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.515068] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.516446] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.517231] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:43 BXT-2 kernel: [ 633.517958] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.517964] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:43 BXT-2 kernel: [ 633.517969] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:43 BXT-2 kernel: [ 633.517974] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:43 BXT-2 kernel: [ 633.518276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:43 BXT-2 kernel: [ 633.518285] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518290] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518295] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:43 BXT-2 kernel: [ 633.518300] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:43 BXT-2 kernel: [ 633.518305] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518310] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:43 BXT-2 kernel: [ 633.518315] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:43 BXT-2 kernel: [ 633.518320] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518325] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518331] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:43 BXT-2 kernel: [ 633.518337] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518342] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518347] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518352] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518357] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518363] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518369] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518374] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518379] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518384] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518389] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518394] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518400] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518405] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518410] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518415] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.518421] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518426] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518432] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518437] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518442] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518447] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518452] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.518457] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:43 BXT-2 kernel: [ 633.518546] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.518606] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.519140] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:43 BXT-2 kernel: [ 633.520086] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:43 BXT-2 kernel: [ 633.520132] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.520174] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:43 BXT-2 kernel: [ 633.520267] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:43 BXT-2 kernel: [ 633.520758] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:43 BXT-2 kernel: [ 633.520800] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:43 BXT-2 kernel: [ 633.525643] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:43 BXT-2 kernel: [ 633.525706] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:43 BXT-2 kernel: [ 633.525713] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525718] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525723] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525728] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525734] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525739] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525744] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.525749] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525754] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.525759] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.525764] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.528588] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:43 BXT-2 kernel: [ 633.535832] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.535899] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.536471] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:43 BXT-2 kernel: [ 633.537343] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:43 BXT-2 kernel: [ 633.537389] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.537433] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.537475] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.537983] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:43 BXT-2 kernel: [ 633.538678] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:43 BXT-2 kernel: [ 633.539533] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.541079] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.542332] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.543566] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.544856] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.546106] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.547360] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.548746] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.549999] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.551384] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.552758] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.554180] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.555563] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.556999] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.558375] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.560025] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.561455] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.562713] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.563973] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.565235] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.566473] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.567847] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.569235] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.570644] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.572188] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.573560] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.574987] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.576386] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.577780] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:43 BXT-2 kernel: [ 633.578579] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:43 BXT-2 kernel: [ 633.579337] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.579344] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:43 BXT-2 kernel: [ 633.579349] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:43 BXT-2 kernel: [ 633.579354] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:43 BXT-2 kernel: [ 633.579588] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:43 BXT-2 kernel: [ 633.579595] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579601] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579606] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:43 BXT-2 kernel: [ 633.579611] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:43 BXT-2 kernel: [ 633.579616] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579621] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:43 BXT-2 kernel: [ 633.579626] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:43 BXT-2 kernel: [ 633.579631] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579636] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579641] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:43 BXT-2 kernel: [ 633.579646] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579651] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579656] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579661] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579666] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579671] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579676] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579681] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579686] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579692] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579697] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579702] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579707] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579712] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579717] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579722] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.579727] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579732] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579737] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579742] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579747] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579752] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579757] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.579762] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:43 BXT-2 kernel: [ 633.580244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.580305] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.580857] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:43 BXT-2 kernel: [ 633.581744] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:43 BXT-2 kernel: [ 633.581790] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:43 BXT-2 kernel: [ 633.581836] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:43 BXT-2 kernel: [ 633.581878] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:43 BXT-2 kernel: [ 633.582390] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:43 BXT-2 kernel: [ 633.582434] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:43 BXT-2 kernel: [ 633.587710] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:43 BXT-2 kernel: [ 633.587776] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:43 BXT-2 kernel: [ 633.587784] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587789] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587794] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587799] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587804] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587809] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587814] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.587819] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587824] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.587829] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.587834] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:43 BXT-2 kernel: [ 633.587839] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:43 BXT-2 kernel: [ 633.589106] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:43 BXT-2 kernel: [ 633.605636] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:43 BXT-2 kernel: [ 633.605791] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.605985] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:43 BXT-2 kernel: [ 633.606041] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:43 BXT-2 kernel: [ 633.606610] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:43 BXT-2 kernel: [ 633.620442] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:43 BXT-2 kernel: [ 633.620554] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.620643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.620690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.620732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.620775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.620818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.620861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.620904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.620946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.620989] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.621036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.621083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.621128] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.626733] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:43 BXT-2 kernel: [ 633.627349] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:43 BXT-2 kernel: [ 633.627499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.627731] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:43 BXT-2 kernel: [ 633.645496] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:43 BXT-2 kernel: [ 633.645608] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.645696] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.646018] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.646062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.646106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.646149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.646239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.646285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.646333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.646379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.646423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.646466] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:43 BXT-2 kernel: [ 633.646515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.646560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.646605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.646666] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:43 BXT-2 kernel: [ 633.646709] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.646762] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.646826] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:43 BXT-2 kernel: [ 633.646871] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:43 BXT-2 kernel: [ 633.646914] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:43 BXT-2 kernel: [ 633.646953] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:43 BXT-2 kernel: [ 633.647536] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:43 BXT-2 kernel: [ 633.648769] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:43 BXT-2 kernel: [ 633.648803] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.648921] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:43 BXT-2 kernel: [ 633.648965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:43 BXT-2 kernel: [ 633.649010] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:43 BXT-2 kernel: [ 633.649053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:43 BXT-2 kernel: [ 633.649095] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:43 BXT-2 kernel: [ 633.649138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.649240] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:43 BXT-2 kernel: [ 633.649283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.649326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:43 BXT-2 kernel: [ 633.649369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.649411] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:43 BXT-2 kernel: [ 633.649419] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.649461] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:43 BXT-2 kernel: [ 633.649468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.649512] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.649555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:43 BXT-2 kernel: [ 633.649598] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:43 BXT-2 kernel: [ 633.649641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:43 BXT-2 kernel: [ 633.649684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.649729] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:43 BXT-2 kernel: [ 633.649772] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:43 BXT-2 kernel: [ 633.649815] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.649859] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.649902] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.649966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.650019] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.650063] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.650622] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:43 BXT-2 kernel: [ 633.650661] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:43 BXT-2 kernel: [ 633.650953] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:43 BXT-2 kernel: [ 633.651006] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.651046] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.651103] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:43 BXT-2 kernel: [ 633.651428] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.651750] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.651793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.651837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.651879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.651922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.651965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.652007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.652050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.652092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.652135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.652225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.652271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.652345] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:43 BXT-2 kernel: [ 633.652389] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.654196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.654296] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.654341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:43 BXT-2 kernel: [ 633.673521] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:43 BXT-2 kernel: [ 633.673568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:43 BXT-2 kernel: [ 633.691826] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:43 BXT-2 kernel: [ 633.693930] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:43 BXT-2 kernel: [ 633.694996] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.695070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.695113] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:43 BXT-2 kernel: [ 633.695169] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:43 BXT-2 kernel: [ 633.711870] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.711930] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:43 BXT-2 kernel: [ 633.712104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.795411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.795530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.795584] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:43 BXT-2 kernel: [ 633.795669] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.813543] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:43 BXT-2 kernel: [ 633.813656] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.813737] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.814059] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.814105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.814152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.814250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.814293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.814339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.814382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.814425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.814468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.814511] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.814559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.814604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.814651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.814713] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:43 BXT-2 kernel: [ 633.814757] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.814811] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.814873] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:43 BXT-2 kernel: [ 633.814917] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:43 BXT-2 kernel: [ 633.814961] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:43 BXT-2 kernel: [ 633.815001] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:43 BXT-2 kernel: [ 633.815585] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:43 BXT-2 kernel: [ 633.816669] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:43 BXT-2 kernel: [ 633.834717] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:43 BXT-2 kernel: [ 633.834784] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.834912] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:43 BXT-2 kernel: [ 633.834956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:43 BXT-2 kernel: [ 633.835000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:43 BXT-2 kernel: [ 633.835044] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:43 BXT-2 kernel: [ 633.835087] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:43 BXT-2 kernel: [ 633.835131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.835174] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:43 BXT-2 kernel: [ 633.835255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.835298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:43 BXT-2 kernel: [ 633.835340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.835382] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:43 BXT-2 kernel: [ 633.835390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.835432] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:43 BXT-2 kernel: [ 633.835441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.835485] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:43 BXT-2 kernel: [ 633.835527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:43 BXT-2 kernel: [ 633.835571] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:43 BXT-2 kernel: [ 633.835614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:43 BXT-2 kernel: [ 633.835657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:43 BXT-2 kernel: [ 633.835703] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:43 BXT-2 kernel: [ 633.835746] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:43 BXT-2 kernel: [ 633.835790] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.835833] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.835876] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:43 BXT-2 kernel: [ 633.835938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.835992] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.836036] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.836657] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:43 BXT-2 kernel: [ 633.836696] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:43 BXT-2 kernel: [ 633.836986] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:43 BXT-2 kernel: [ 633.837040] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.837082] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:43 BXT-2 kernel: [ 633.837139] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:43 BXT-2 kernel: [ 633.837919] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.838273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.838319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.838363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.838406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.838449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.838492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:43 BXT-2 kernel: [ 633.838535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:43 BXT-2 kernel: [ 633.838577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:43 BXT-2 kernel: [ 633.838620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:43 BXT-2 kernel: [ 633.838663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:43 BXT-2 kernel: [ 633.838712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.838757] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:43 BXT-2 kernel: [ 633.838832] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:43 BXT-2 kernel: [ 633.838876] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.840657] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.840703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:43 BXT-2 kernel: [ 633.840747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:43 BXT-2 kernel: [ 633.860548] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:43 BXT-2 kernel: [ 633.860596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:43 BXT-2 kernel: [ 633.879712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:43 BXT-2 kernel: [ 633.881815] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:43 BXT-2 kernel: [ 633.882884] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.882959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:43 BXT-2 kernel: [ 633.883002] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:43 BXT-2 kernel: [ 633.883057] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:43 BXT-2 kernel: [ 633.899771] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:43 BXT-2 kernel: [ 633.899829] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:43 BXT-2 kernel: [ 633.900001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:43 BXT-2 kernel: [ 633.983313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:43 BXT-2 kernel: [ 633.983434] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:43 BXT-2 kernel: [ 633.983489] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:43 BXT-2 kernel: [ 633.983573] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.001551] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:44 BXT-2 kernel: [ 634.001663] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.001745] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.002067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.002111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.002159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.002254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.002299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.002344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.002389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.002434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.002478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.002521] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.002572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.002617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.002662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.002725] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.002768] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.002823] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.002883] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.002927] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.002970] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:44 BXT-2 kernel: [ 634.003008] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:44 BXT-2 kernel: [ 634.003600] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.005461] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:44 BXT-2 kernel: [ 634.023603] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.023670] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.023801] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:44 BXT-2 kernel: [ 634.023845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:44 BXT-2 kernel: [ 634.023890] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:44 BXT-2 kernel: [ 634.023934] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:44 BXT-2 kernel: [ 634.023976] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.024021] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.024064] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:44 BXT-2 kernel: [ 634.024107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.024150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:44 BXT-2 kernel: [ 634.024233] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.024275] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:44 BXT-2 kernel: [ 634.024287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.024331] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:44 BXT-2 kernel: [ 634.024340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.024385] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.024430] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:44 BXT-2 kernel: [ 634.024476] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:44 BXT-2 kernel: [ 634.024521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:44 BXT-2 kernel: [ 634.024566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.024615] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:44 BXT-2 kernel: [ 634.024658] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:44 BXT-2 kernel: [ 634.024705] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.024748] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.024791] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.024853] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.024907] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.024951] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.025581] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.025621] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.025911] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:44 BXT-2 kernel: [ 634.025964] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.026004] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.026061] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.026377] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.026703] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.026747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.026790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.026832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.026875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.026918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.026961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.027004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.027047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.027091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.027137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.027225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.027301] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:44 BXT-2 kernel: [ 634.027346] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.028794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.028838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.028882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:44 BXT-2 kernel: [ 634.029685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.029729] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.030794] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:44 BXT-2 kernel: [ 634.030842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:44 BXT-2 kernel: [ 634.031912] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:44 BXT-2 kernel: [ 634.034013] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:44 BXT-2 kernel: [ 634.035035] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.051969] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.052028] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.052565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.135531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.135665] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.153597] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:44 BXT-2 kernel: [ 634.153713] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.153795] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.154124] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.154169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.154290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.154336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.154379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.154422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.154471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.154514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.154558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.154601] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.154650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.154697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.154743] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.154807] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.154850] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.154906] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.154968] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.155013] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.155057] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:44 BXT-2 kernel: [ 634.155096] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:44 BXT-2 kernel: [ 634.155674] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.156692] [drm:drm_mode_addfb2] [FB:103] >May 24 03:32:44 BXT-2 kernel: [ 634.176630] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.176693] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.176825] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:44 BXT-2 kernel: [ 634.176868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:44 BXT-2 kernel: [ 634.176913] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:44 BXT-2 kernel: [ 634.176957] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:44 BXT-2 kernel: [ 634.177000] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.177044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.177087] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:44 BXT-2 kernel: [ 634.177130] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.177173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:44 BXT-2 kernel: [ 634.177722] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.177765] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:44 BXT-2 kernel: [ 634.177774] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.177816] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:44 BXT-2 kernel: [ 634.177822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.177865] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.177908] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:44 BXT-2 kernel: [ 634.177951] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:44 BXT-2 kernel: [ 634.177994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:44 BXT-2 kernel: [ 634.178036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.178082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:44 BXT-2 kernel: [ 634.178124] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:44 BXT-2 kernel: [ 634.178168] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.178727] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.178770] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.178838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.178894] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.178937] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.179840] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.179881] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.180175] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:44 BXT-2 kernel: [ 634.181069] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.181111] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.181168] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.181722] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.182049] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.182093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.182136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.182179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.182270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.182315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.182360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.182403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.182448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.182492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.182541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.182586] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.182661] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:44 BXT-2 kernel: [ 634.182705] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.185138] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.185228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.185274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:44 BXT-2 kernel: [ 634.186065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.186108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.186936] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:44 BXT-2 kernel: [ 634.186981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:44 BXT-2 kernel: [ 634.188097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:44 BXT-2 kernel: [ 634.190187] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:44 BXT-2 kernel: [ 634.191619] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.208491] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.208551] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.208784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.292049] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.292252] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.308617] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:44 BXT-2 kernel: [ 634.308732] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.308816] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.309136] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.309180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.309282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.309325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.309370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.309413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.309461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.309505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.309547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.309592] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.309640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.309687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.309732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.309793] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.309836] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.309890] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.309952] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.309996] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.310040] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:44 BXT-2 kernel: [ 634.310078] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:44 BXT-2 kernel: [ 634.310679] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.337174] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:44 BXT-2 kernel: [ 634.337245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:44 BXT-2 kernel: [ 634.337289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:44 BXT-2 kernel: [ 634.337333] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:44 BXT-2 kernel: [ 634.337374] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:44 BXT-2 kernel: [ 634.337418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.337462] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:44 BXT-2 kernel: [ 634.337504] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.337545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:44 BXT-2 kernel: [ 634.337587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.337627] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:44 BXT-2 kernel: [ 634.337636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.337677] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:44 BXT-2 kernel: [ 634.337682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.337723] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.337765] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:44 BXT-2 kernel: [ 634.337807] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:44 BXT-2 kernel: [ 634.337848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:44 BXT-2 kernel: [ 634.337889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.337936] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:44 BXT-2 kernel: [ 634.337976] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:44 BXT-2 kernel: [ 634.338018] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.338060] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.338101] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.338142] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.338232] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:44 BXT-2 kernel: [ 634.338273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:44 BXT-2 kernel: [ 634.338315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:44 BXT-2 kernel: [ 634.338357] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:44 BXT-2 kernel: [ 634.338397] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.338439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.338480] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:44 BXT-2 kernel: [ 634.338522] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.338563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:44 BXT-2 kernel: [ 634.338604] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.338645] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:44 BXT-2 kernel: [ 634.338649] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.338690] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:44 BXT-2 kernel: [ 634.338694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.338737] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.338778] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:44 BXT-2 kernel: [ 634.338819] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:44 BXT-2 kernel: [ 634.338860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:44 BXT-2 kernel: [ 634.338901] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.338944] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:44 BXT-2 kernel: [ 634.338984] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:44 BXT-2 kernel: [ 634.339026] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.339067] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.339108] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.339149] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.339224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.339275] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.339319] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:44 BXT-2 kernel: [ 634.339363] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.339405] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:44 BXT-2 kernel: [ 634.339561] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.339597] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.339887] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:44 BXT-2 kernel: [ 634.339942] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.339981] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.340037] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.340338] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.340659] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.340702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.340747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.340790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.340834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.340876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.340920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.340961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.341004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.341047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.341092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.341136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.341250] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:44 BXT-2 kernel: [ 634.341292] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.342718] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.342759] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.342802] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:44 BXT-2 kernel: [ 634.361737] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:44 BXT-2 kernel: [ 634.361783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:44 BXT-2 kernel: [ 634.379948] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:44 BXT-2 kernel: [ 634.382029] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:44 BXT-2 kernel: [ 634.383178] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:44 BXT-2 kernel: [ 634.383290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.383332] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:44 BXT-2 kernel: [ 634.383388] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:44 BXT-2 kernel: [ 634.383566] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:44 BXT-2 kernel: [ 634.383609] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.385025] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.385066] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.385109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:44 BXT-2 kernel: [ 634.385884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.385924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.386655] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:44 BXT-2 kernel: [ 634.386696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:44 BXT-2 kernel: [ 634.387738] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:44 BXT-2 kernel: [ 634.389813] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:44 BXT-2 kernel: [ 634.390977] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:44 BXT-2 kernel: [ 634.407837] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.407890] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:44 BXT-2 kernel: [ 634.408066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.408282] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.408333] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:44 BXT-2 kernel: [ 634.408509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.408873] Console: switching to colour frame buffer device 240x67 >May 24 03:32:44 BXT-2 kernel: [ 634.738421] Console: switching to colour dummy device 80x25 >May 24 03:32:44 BXT-2 kernel: [ 634.759728] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.759798] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.760454] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:44 BXT-2 kernel: [ 634.761371] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:44 BXT-2 kernel: [ 634.761418] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.761462] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.761504] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.761998] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:44 BXT-2 kernel: [ 634.762684] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:44 BXT-2 kernel: [ 634.763550] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.764865] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.766139] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.767420] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.768703] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.769960] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.771221] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.772471] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.773719] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.775103] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.776502] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.777902] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.779293] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.780732] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.782121] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.783510] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.784994] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.786259] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.787546] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.788870] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.790113] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.791505] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.792888] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.794268] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.795717] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.797121] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.798506] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.799890] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.801265] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.802056] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:44 BXT-2 kernel: [ 634.802857] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.802864] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:44 BXT-2 kernel: [ 634.802870] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:44 BXT-2 kernel: [ 634.802874] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:44 BXT-2 kernel: [ 634.803101] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:44 BXT-2 kernel: [ 634.803109] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803114] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803119] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:44 BXT-2 kernel: [ 634.803124] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:44 BXT-2 kernel: [ 634.803129] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803134] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:44 BXT-2 kernel: [ 634.803139] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:44 BXT-2 kernel: [ 634.803642] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803648] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803654] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:44 BXT-2 kernel: [ 634.803659] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803664] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803669] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803674] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803680] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803685] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803690] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803695] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803700] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803705] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803711] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803716] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803721] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803726] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803732] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803737] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.803742] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803747] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803752] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803757] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803762] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803767] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803772] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.803778] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:44 BXT-2 kernel: [ 634.803859] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.803917] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.805269] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:44 BXT-2 kernel: [ 634.806143] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:44 BXT-2 kernel: [ 634.806404] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.806446] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:44 BXT-2 kernel: [ 634.806489] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:44 BXT-2 kernel: [ 634.806992] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:44 BXT-2 kernel: [ 634.807035] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:44 BXT-2 kernel: [ 634.811923] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:44 BXT-2 kernel: [ 634.811987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:44 BXT-2 kernel: [ 634.811994] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.811999] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812004] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812009] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812014] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812019] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812024] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.812030] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812035] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.812040] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.812045] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.812050] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:44 BXT-2 kernel: [ 634.819244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.819311] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.819854] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:44 BXT-2 kernel: [ 634.820984] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:44 BXT-2 kernel: [ 634.821030] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.821073] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.821116] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.821735] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:44 BXT-2 kernel: [ 634.822128] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:44 BXT-2 kernel: [ 634.823314] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.824578] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.825870] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.827121] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.828368] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.829731] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.830984] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.832247] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.833484] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.834861] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.836250] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.837750] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.839136] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.840529] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.841995] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.843381] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.844750] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.846044] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.847319] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.848577] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.849851] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.851231] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.852887] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.854291] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.855735] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.857133] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.860029] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.861432] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.862911] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:44 BXT-2 kernel: [ 634.863716] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:44 BXT-2 kernel: [ 634.864509] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.864516] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:44 BXT-2 kernel: [ 634.864522] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:44 BXT-2 kernel: [ 634.864526] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:44 BXT-2 kernel: [ 634.864758] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:44 BXT-2 kernel: [ 634.864765] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864771] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864776] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:44 BXT-2 kernel: [ 634.864781] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:44 BXT-2 kernel: [ 634.864786] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864791] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:44 BXT-2 kernel: [ 634.864796] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:44 BXT-2 kernel: [ 634.864801] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864806] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864811] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:44 BXT-2 kernel: [ 634.864816] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864821] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864826] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864831] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864836] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864842] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864847] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864852] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864857] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864862] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864867] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864872] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864877] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864882] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864887] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864892] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.864897] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864902] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864907] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864912] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864917] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864922] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864927] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.864932] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:44 BXT-2 kernel: [ 634.865383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.865444] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.866589] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:44 BXT-2 kernel: [ 634.867582] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:44 BXT-2 kernel: [ 634.867630] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:44 BXT-2 kernel: [ 634.867673] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:44 BXT-2 kernel: [ 634.867715] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:44 BXT-2 kernel: [ 634.868280] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:44 BXT-2 kernel: [ 634.868325] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:44 BXT-2 kernel: [ 634.873843] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:44 BXT-2 kernel: [ 634.873911] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:44 BXT-2 kernel: [ 634.873918] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873923] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873928] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873933] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873938] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873943] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873949] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.873954] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873959] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.873964] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.873969] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:44 BXT-2 kernel: [ 634.873974] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:44 BXT-2 kernel: [ 634.875561] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:44 BXT-2 kernel: [ 634.891288] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:44 BXT-2 kernel: [ 634.891445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.891627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:44 BXT-2 kernel: [ 634.891682] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:44 BXT-2 kernel: [ 634.891774] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:44 BXT-2 kernel: [ 634.901514] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:44 BXT-2 kernel: [ 634.901626] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.901716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.901763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.901806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.901849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.901892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.901935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.901977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.902020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.902063] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.902110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.902155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.902255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.907798] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:44 BXT-2 kernel: [ 634.908248] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:44 BXT-2 kernel: [ 634.908393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.908513] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:44 BXT-2 kernel: [ 634.925078] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:44 BXT-2 kernel: [ 634.925242] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.925337] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.925660] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.925704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.925747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.925790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.925833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.925876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.925922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.925965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.926007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.926052] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:44 BXT-2 kernel: [ 634.926099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.926143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.926223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.926286] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.926330] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.926385] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.926448] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:44 BXT-2 kernel: [ 634.926494] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.926538] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:44 BXT-2 kernel: [ 634.926579] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:44 BXT-2 kernel: [ 634.927751] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.929019] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.929071] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.929189] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:44 BXT-2 kernel: [ 634.929269] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:44 BXT-2 kernel: [ 634.929316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:44 BXT-2 kernel: [ 634.929361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:44 BXT-2 kernel: [ 634.929404] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:44 BXT-2 kernel: [ 634.929449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.929493] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:44 BXT-2 kernel: [ 634.929536] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.929580] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:44 BXT-2 kernel: [ 634.929623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.929665] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:44 BXT-2 kernel: [ 634.929674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.929715] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:44 BXT-2 kernel: [ 634.929722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.929765] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:44 BXT-2 kernel: [ 634.929809] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:44 BXT-2 kernel: [ 634.929852] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:44 BXT-2 kernel: [ 634.929895] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:44 BXT-2 kernel: [ 634.929938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:44 BXT-2 kernel: [ 634.929983] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:44 BXT-2 kernel: [ 634.930025] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:44 BXT-2 kernel: [ 634.930069] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.930112] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.930155] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:44 BXT-2 kernel: [ 634.930245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.930301] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.930347] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.930931] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:44 BXT-2 kernel: [ 634.930970] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:44 BXT-2 kernel: [ 634.931296] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:44 BXT-2 kernel: [ 634.931355] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.931397] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:44 BXT-2 kernel: [ 634.931456] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:44 BXT-2 kernel: [ 634.931736] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.932058] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:44 BXT-2 kernel: [ 634.932106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.932149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.932237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.932281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.932325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:44 BXT-2 kernel: [ 634.932368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:44 BXT-2 kernel: [ 634.932412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:44 BXT-2 kernel: [ 634.932456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:44 BXT-2 kernel: [ 634.932499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:44 BXT-2 kernel: [ 634.932547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.932592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:44 BXT-2 kernel: [ 634.932667] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:44 BXT-2 kernel: [ 634.932710] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:44 BXT-2 kernel: [ 634.934159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.934235] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:44 BXT-2 kernel: [ 634.934279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:44 BXT-2 kernel: [ 634.953377] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:44 BXT-2 kernel: [ 634.953424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:44 BXT-2 kernel: [ 634.971504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:44 BXT-2 kernel: [ 634.974095] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:44 BXT-2 kernel: [ 634.975317] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:44 BXT-2 kernel: [ 634.975409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:44 BXT-2 kernel: [ 634.975452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:44 BXT-2 kernel: [ 634.975508] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:44 BXT-2 kernel: [ 634.992242] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:44 BXT-2 kernel: [ 634.992301] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:44 BXT-2 kernel: [ 634.992475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.109100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.109308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.109364] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:45 BXT-2 kernel: [ 635.109451] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.127609] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.127722] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.127803] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.128123] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.128167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.128276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.128324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.128367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.128411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.128455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.128498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.128541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.128586] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:45 BXT-2 kernel: [ 635.128634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.128682] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.128727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.128794] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.128839] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.128894] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.128957] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.129001] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.129046] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:45 BXT-2 kernel: [ 635.129085] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:45 BXT-2 kernel: [ 635.129669] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.130719] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:45 BXT-2 kernel: [ 635.150152] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.150243] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:45 BXT-2 kernel: [ 635.150373] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:45 BXT-2 kernel: [ 635.150417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:45 BXT-2 kernel: [ 635.150462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:45 BXT-2 kernel: [ 635.150506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:45 BXT-2 kernel: [ 635.150548] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:45 BXT-2 kernel: [ 635.150593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.150638] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:45 BXT-2 kernel: [ 635.150680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.150724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:45 BXT-2 kernel: [ 635.150766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.150808] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:45 BXT-2 kernel: [ 635.150815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.150857] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:45 BXT-2 kernel: [ 635.150863] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.150906] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.150948] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:45 BXT-2 kernel: [ 635.150991] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:45 BXT-2 kernel: [ 635.151033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:45 BXT-2 kernel: [ 635.151075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.151120] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:45 BXT-2 kernel: [ 635.151162] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:45 BXT-2 kernel: [ 635.152078] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.152122] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.152165] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.152408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.152466] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.152509] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.153091] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.153129] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.153693] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:45 BXT-2 kernel: [ 635.154041] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.154081] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.154138] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.154612] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.154931] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.154975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.155018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.155061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.155104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.155146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.155510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.155553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.155596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.155639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.155687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.155732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.155807] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.155849] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.157572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.157616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.157660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:45 BXT-2 kernel: [ 635.176889] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:45 BXT-2 kernel: [ 635.176937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:45 BXT-2 kernel: [ 635.194987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:45 BXT-2 kernel: [ 635.197090] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:45 BXT-2 kernel: [ 635.198058] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.198131] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.198174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:45 BXT-2 kernel: [ 635.198514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:45 BXT-2 kernel: [ 635.214942] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:45 BXT-2 kernel: [ 635.215000] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.215172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.331849] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.331972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.332027] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:45 BXT-2 kernel: [ 635.332123] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.349455] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.349569] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.349648] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.349972] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.350017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.350084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.350128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.350170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.350280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.350323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.350368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.350411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.350454] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:45 BXT-2 kernel: [ 635.350505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.350552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.350598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.350662] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.350707] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.350761] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.350824] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.350867] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.350911] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:45 BXT-2 kernel: [ 635.350950] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:45 BXT-2 kernel: [ 635.351544] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.352585] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:45 BXT-2 kernel: [ 635.368698] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.368762] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.368892] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:45 BXT-2 kernel: [ 635.368936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:45 BXT-2 kernel: [ 635.368980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:45 BXT-2 kernel: [ 635.369024] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:45 BXT-2 kernel: [ 635.369066] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:45 BXT-2 kernel: [ 635.369111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.369154] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:45 BXT-2 kernel: [ 635.369468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.369512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:45 BXT-2 kernel: [ 635.369555] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.369598] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:45 BXT-2 kernel: [ 635.369608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.369650] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:45 BXT-2 kernel: [ 635.369655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.369698] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.369742] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:45 BXT-2 kernel: [ 635.369785] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:45 BXT-2 kernel: [ 635.369828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:45 BXT-2 kernel: [ 635.369871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.369916] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:45 BXT-2 kernel: [ 635.369959] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:45 BXT-2 kernel: [ 635.370003] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.370047] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.370090] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.370157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.370256] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.370300] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.370880] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.370918] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.371239] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:45 BXT-2 kernel: [ 635.371294] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.371337] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.371394] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.371690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.372012] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.372056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.372099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.372142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.372236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.372279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.372322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.372364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.372407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.372452] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.372499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.372544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.372619] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.372663] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.374129] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.374174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.374274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:45 BXT-2 kernel: [ 635.375074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.375119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.375867] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:45 BXT-2 kernel: [ 635.375914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:45 BXT-2 kernel: [ 635.376985] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:45 BXT-2 kernel: [ 635.379086] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:45 BXT-2 kernel: [ 635.380053] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.396944] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.397003] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.397175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.513907] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.514063] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.531479] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.531596] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.531679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.532041] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.532101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.532152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.532288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.532331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.532377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.532427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.532470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.532513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.532557] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.532605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.532653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.532699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.532771] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.532814] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.532869] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.532932] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.532976] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.533020] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:45 BXT-2 kernel: [ 635.533058] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:45 BXT-2 kernel: [ 635.533693] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.535724] [drm:drm_mode_addfb2] [FB:79] >May 24 03:32:45 BXT-2 kernel: [ 635.557043] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.557106] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.557276] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:45 BXT-2 kernel: [ 635.557320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:45 BXT-2 kernel: [ 635.557366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:45 BXT-2 kernel: [ 635.557412] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:45 BXT-2 kernel: [ 635.557454] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:45 BXT-2 kernel: [ 635.557499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.557544] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:45 BXT-2 kernel: [ 635.557588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.557632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:45 BXT-2 kernel: [ 635.557676] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.557719] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:45 BXT-2 kernel: [ 635.557726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.557768] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:45 BXT-2 kernel: [ 635.557775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.557819] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.557865] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:45 BXT-2 kernel: [ 635.557908] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:45 BXT-2 kernel: [ 635.557951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:45 BXT-2 kernel: [ 635.557995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.558042] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:45 BXT-2 kernel: [ 635.558085] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:45 BXT-2 kernel: [ 635.558129] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.558173] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.558241] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.558304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.558359] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.558406] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.559003] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.559042] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.559360] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:45 BXT-2 kernel: [ 635.559417] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.559458] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.559514] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.559762] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.560089] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.560134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.560177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.560269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.560315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.560361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.560407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.560453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.560498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.560543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.560593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.560638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.560714] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.560758] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.562191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.562262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.562306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:45 BXT-2 kernel: [ 635.563070] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.563113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.563858] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:45 BXT-2 kernel: [ 635.563902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:45 BXT-2 kernel: [ 635.564960] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:45 BXT-2 kernel: [ 635.567071] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:45 BXT-2 kernel: [ 635.568104] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.584981] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.585040] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.585255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.701867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.702000] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:45 BXT-2 kernel: [ 635.719496] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:45 BXT-2 kernel: [ 635.719609] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.719690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.720012] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.720057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.720100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.720143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.720227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.720275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.720330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.720374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.720417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.720463] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.720512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.720558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.720603] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.720667] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.720710] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.720764] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.720829] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:45 BXT-2 kernel: [ 635.720874] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.720918] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:45 BXT-2 kernel: [ 635.720958] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:45 BXT-2 kernel: [ 635.721576] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.745294] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:45 BXT-2 kernel: [ 635.745338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:45 BXT-2 kernel: [ 635.745382] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:45 BXT-2 kernel: [ 635.745424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:45 BXT-2 kernel: [ 635.745465] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:45 BXT-2 kernel: [ 635.745508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.745551] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:45 BXT-2 kernel: [ 635.745593] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.745635] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:45 BXT-2 kernel: [ 635.745676] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.745717] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:45 BXT-2 kernel: [ 635.745724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.745765] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:45 BXT-2 kernel: [ 635.745769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.745811] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.745853] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:45 BXT-2 kernel: [ 635.745895] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:45 BXT-2 kernel: [ 635.745936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:45 BXT-2 kernel: [ 635.745977] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.746021] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:45 BXT-2 kernel: [ 635.746062] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:45 BXT-2 kernel: [ 635.746104] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.746146] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.746215] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.746257] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.746307] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:45 BXT-2 kernel: [ 635.746348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:45 BXT-2 kernel: [ 635.746391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:45 BXT-2 kernel: [ 635.746434] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:45 BXT-2 kernel: [ 635.746475] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:45 BXT-2 kernel: [ 635.746517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.746560] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:45 BXT-2 kernel: [ 635.746602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.746643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:45 BXT-2 kernel: [ 635.746685] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.746725] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:45 BXT-2 kernel: [ 635.746731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.746772] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:45 BXT-2 kernel: [ 635.746777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.746818] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:45 BXT-2 kernel: [ 635.746860] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:45 BXT-2 kernel: [ 635.746901] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:45 BXT-2 kernel: [ 635.746943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:45 BXT-2 kernel: [ 635.746984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:45 BXT-2 kernel: [ 635.747027] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:45 BXT-2 kernel: [ 635.747067] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:45 BXT-2 kernel: [ 635.747109] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.747151] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.747223] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.747265] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:45 BXT-2 kernel: [ 635.747312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.747366] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.747408] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:45 BXT-2 kernel: [ 635.747451] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.747493] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:45 BXT-2 kernel: [ 635.747637] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:45 BXT-2 kernel: [ 635.747673] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:45 BXT-2 kernel: [ 635.747965] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:45 BXT-2 kernel: [ 635.748020] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.748060] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:45 BXT-2 kernel: [ 635.748115] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:45 BXT-2 kernel: [ 635.748392] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.748721] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:45 BXT-2 kernel: [ 635.748764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.748806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.748848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.748889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.748930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:45 BXT-2 kernel: [ 635.748972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:45 BXT-2 kernel: [ 635.749014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:45 BXT-2 kernel: [ 635.749055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:45 BXT-2 kernel: [ 635.749097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:45 BXT-2 kernel: [ 635.749143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.749252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.749329] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:45 BXT-2 kernel: [ 635.749370] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.750802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.750845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.750888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:45 BXT-2 kernel: [ 635.769902] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:45 BXT-2 kernel: [ 635.769947] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:45 BXT-2 kernel: [ 635.788872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:45 BXT-2 kernel: [ 635.790948] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:45 BXT-2 kernel: [ 635.792133] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:45 BXT-2 kernel: [ 635.792266] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:45 BXT-2 kernel: [ 635.792308] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:45 BXT-2 kernel: [ 635.792364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:45 BXT-2 kernel: [ 635.792548] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:45 BXT-2 kernel: [ 635.792591] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.793994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.794035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.794078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:45 BXT-2 kernel: [ 635.794837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.794877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:45 BXT-2 kernel: [ 635.795608] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:45 BXT-2 kernel: [ 635.795649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:45 BXT-2 kernel: [ 635.796687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:45 BXT-2 kernel: [ 635.798763] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:45 BXT-2 kernel: [ 635.799934] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:45 BXT-2 kernel: [ 635.816878] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:45 BXT-2 kernel: [ 635.816934] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:45 BXT-2 kernel: [ 635.817115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:45 BXT-2 kernel: [ 635.817338] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:45 BXT-2 kernel: [ 635.817392] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:45 BXT-2 kernel: [ 635.817563] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:45 BXT-2 kernel: [ 635.817947] Console: switching to colour frame buffer device 240x67 >May 24 03:32:46 BXT-2 kernel: [ 636.163917] Console: switching to colour dummy device 80x25 >May 24 03:32:46 BXT-2 kernel: [ 636.179075] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.179143] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.180085] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:46 BXT-2 kernel: [ 636.181038] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:46 BXT-2 kernel: [ 636.181084] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.181127] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.181170] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.181969] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:46 BXT-2 kernel: [ 636.182578] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:46 BXT-2 kernel: [ 636.183440] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.184761] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.186040] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.187301] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.188585] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.189875] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.191135] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.192409] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.193719] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.195112] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.196509] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.197890] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.199305] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.200732] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.202137] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.203650] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.205031] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.206307] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.207554] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.208885] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.210131] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.211516] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.212996] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.214383] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.215769] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.217176] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.218560] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.220020] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.221404] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.222301] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:46 BXT-2 kernel: [ 636.223047] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.223053] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:46 BXT-2 kernel: [ 636.223058] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:46 BXT-2 kernel: [ 636.223063] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:46 BXT-2 kernel: [ 636.223566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:46 BXT-2 kernel: [ 636.223574] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223580] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223585] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:46 BXT-2 kernel: [ 636.223590] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:46 BXT-2 kernel: [ 636.223595] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223600] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:46 BXT-2 kernel: [ 636.223605] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:46 BXT-2 kernel: [ 636.223610] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223615] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223620] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:46 BXT-2 kernel: [ 636.223625] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223631] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223636] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223641] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223646] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223651] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223656] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223661] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223666] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223671] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223676] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223681] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223686] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223691] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223696] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223702] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.223707] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223712] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223717] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223722] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223727] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223732] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223737] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.223742] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:46 BXT-2 kernel: [ 636.223822] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.223883] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.225520] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:46 BXT-2 kernel: [ 636.226432] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:46 BXT-2 kernel: [ 636.226479] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.226523] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:46 BXT-2 kernel: [ 636.226566] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:46 BXT-2 kernel: [ 636.227057] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:46 BXT-2 kernel: [ 636.227100] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:46 BXT-2 kernel: [ 636.232144] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:46 BXT-2 kernel: [ 636.232246] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:46 BXT-2 kernel: [ 636.232253] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232258] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232264] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232269] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232274] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232279] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232284] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.232289] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232294] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.232299] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.232304] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.232309] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:46 BXT-2 kernel: [ 636.239655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.239722] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.240428] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:46 BXT-2 kernel: [ 636.241361] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:46 BXT-2 kernel: [ 636.241407] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.241450] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.241493] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.241988] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:46 BXT-2 kernel: [ 636.242642] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:46 BXT-2 kernel: [ 636.243519] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.244871] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.246127] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.247383] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.248712] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.249977] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.251231] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.252479] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.253721] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.255106] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.256507] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.257887] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.259270] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.260717] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.262110] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.263505] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.264882] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.266182] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.267432] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.268701] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.269952] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.271347] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.272769] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.274245] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.276145] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.277728] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.279099] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.280471] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.281846] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:46 BXT-2 kernel: [ 636.282640] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:46 BXT-2 kernel: [ 636.283544] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.283552] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:46 BXT-2 kernel: [ 636.283558] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:46 BXT-2 kernel: [ 636.283562] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:46 BXT-2 kernel: [ 636.283805] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:46 BXT-2 kernel: [ 636.283812] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283818] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283823] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:46 BXT-2 kernel: [ 636.283828] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:46 BXT-2 kernel: [ 636.283833] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283838] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:46 BXT-2 kernel: [ 636.283843] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:46 BXT-2 kernel: [ 636.283848] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283853] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283858] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:46 BXT-2 kernel: [ 636.283863] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283868] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283873] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283878] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283883] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283888] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283893] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283898] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283903] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283908] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283913] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283918] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283923] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283929] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283934] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283939] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.283943] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283948] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283953] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283958] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283963] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283968] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283973] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.283978] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:46 BXT-2 kernel: [ 636.284424] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.284485] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.285028] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:46 BXT-2 kernel: [ 636.285923] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:46 BXT-2 kernel: [ 636.285968] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.286010] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:46 BXT-2 kernel: [ 636.286053] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:46 BXT-2 kernel: [ 636.286766] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:46 BXT-2 kernel: [ 636.286809] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:46 BXT-2 kernel: [ 636.291746] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:46 BXT-2 kernel: [ 636.291814] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:46 BXT-2 kernel: [ 636.291821] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291826] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291831] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291836] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291841] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291846] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291851] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.291856] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291861] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.291866] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.291872] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:46 BXT-2 kernel: [ 636.291877] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:46 BXT-2 kernel: [ 636.293662] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:46 BXT-2 kernel: [ 636.309011] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:32:46 BXT-2 kernel: [ 636.309166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.309561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:32:46 BXT-2 kernel: [ 636.309618] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:46 BXT-2 kernel: [ 636.309710] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:32:46 BXT-2 kernel: [ 636.327676] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:32:46 BXT-2 kernel: [ 636.327790] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.327879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.327927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.327970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.328013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.328057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.328100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.328143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.328622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.328666] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.328718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.328763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.328808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.333822] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:46 BXT-2 kernel: [ 636.334536] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:32:46 BXT-2 kernel: [ 636.334685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.334850] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:32:46 BXT-2 kernel: [ 636.350554] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:32:46 BXT-2 kernel: [ 636.350665] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.350753] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.351074] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.351118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.351161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.351608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.351651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.351694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.351744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.351786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.351829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.351872] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.351919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.351964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.352009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.352071] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.352114] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.352167] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.352724] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:46 BXT-2 kernel: [ 636.352773] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.352817] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:46 BXT-2 kernel: [ 636.352855] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:46 BXT-2 kernel: [ 636.354021] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.355276] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.355328] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.355451] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:46 BXT-2 kernel: [ 636.355494] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:46 BXT-2 kernel: [ 636.355540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:46 BXT-2 kernel: [ 636.355583] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:46 BXT-2 kernel: [ 636.355625] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:46 BXT-2 kernel: [ 636.355668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.355711] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:46 BXT-2 kernel: [ 636.355754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.355797] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:46 BXT-2 kernel: [ 636.355839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.355880] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:46 BXT-2 kernel: [ 636.355887] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.355929] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:46 BXT-2 kernel: [ 636.355934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.355977] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.356020] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:46 BXT-2 kernel: [ 636.356062] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:46 BXT-2 kernel: [ 636.356105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:46 BXT-2 kernel: [ 636.356147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.356786] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:46 BXT-2 kernel: [ 636.356829] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:46 BXT-2 kernel: [ 636.356876] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.356919] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.356962] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.357030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.357085] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.357128] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.357744] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.357783] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.358073] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:46 BXT-2 kernel: [ 636.358126] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.358166] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.358530] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.358780] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.359100] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.359143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.359251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.359295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.359338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.359381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.359423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.359467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.359511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.359554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.359603] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.359648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.359724] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.359767] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.361229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.361273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.361317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:46 BXT-2 kernel: [ 636.380253] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:46 BXT-2 kernel: [ 636.380301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:46 BXT-2 kernel: [ 636.398369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:46 BXT-2 kernel: [ 636.400472] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:46 BXT-2 kernel: [ 636.401517] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.401615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.401658] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:46 BXT-2 kernel: [ 636.401713] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:46 BXT-2 kernel: [ 636.418416] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.418475] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.418647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.535344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.535466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.535521] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:46 BXT-2 kernel: [ 636.535618] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.553484] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.553596] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.553677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.554000] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.554043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.554091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.554134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.554177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.554275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.554321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.554366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.554411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.554455] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.554504] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.554551] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.554597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.554658] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.554702] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.554756] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.554819] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.554863] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.554907] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:46 BXT-2 kernel: [ 636.554945] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:46 BXT-2 kernel: [ 636.556116] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.557415] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:46 BXT-2 kernel: [ 636.580770] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.580838] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.580967] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:46 BXT-2 kernel: [ 636.581011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:46 BXT-2 kernel: [ 636.581056] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:46 BXT-2 kernel: [ 636.581100] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:46 BXT-2 kernel: [ 636.581145] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:46 BXT-2 kernel: [ 636.582428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.582476] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:46 BXT-2 kernel: [ 636.582519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.582562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:46 BXT-2 kernel: [ 636.582605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.582647] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:46 BXT-2 kernel: [ 636.582656] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.582698] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:46 BXT-2 kernel: [ 636.582704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.582747] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.582790] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:46 BXT-2 kernel: [ 636.582833] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:46 BXT-2 kernel: [ 636.582876] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:46 BXT-2 kernel: [ 636.582919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.582964] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:46 BXT-2 kernel: [ 636.583007] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:46 BXT-2 kernel: [ 636.583050] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.583093] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.583136] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.583398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.583454] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.583499] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.584077] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.584116] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.584524] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:46 BXT-2 kernel: [ 636.585042] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.585084] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.585141] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.585839] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.586170] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.586530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.586575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.586619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.586662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.586705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.586747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.586790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.586833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.586876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.586927] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.586972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.587047] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.587090] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.588867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.588914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.588958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:46 BXT-2 kernel: [ 636.607926] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:46 BXT-2 kernel: [ 636.607974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:46 BXT-2 kernel: [ 636.629756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:46 BXT-2 kernel: [ 636.631863] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:46 BXT-2 kernel: [ 636.632899] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.633004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.633047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD >May 24 03:32:46 BXT-2 kernel: [ 636.633103] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:46 BXT-2 kernel: [ 636.649815] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.649874] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.650045] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.766710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.766828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.766883] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:32:46 BXT-2 kernel: [ 636.766970] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.784536] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.784650] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.784732] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.785052] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.785095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.785142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.785244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.785289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.785334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.785379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.785424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.785469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.785512] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:46 BXT-2 kernel: [ 636.785562] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.785608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.785653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.785716] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.785760] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.785813] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.785876] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.785920] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.785965] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:46 BXT-2 kernel: [ 636.786004] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:46 BXT-2 kernel: [ 636.786597] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.787641] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:46 BXT-2 kernel: [ 636.803760] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.803821] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.803949] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:46 BXT-2 kernel: [ 636.803993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:46 BXT-2 kernel: [ 636.804038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:46 BXT-2 kernel: [ 636.804082] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:46 BXT-2 kernel: [ 636.804125] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.804169] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.804289] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:46 BXT-2 kernel: [ 636.804335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.804381] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:46 BXT-2 kernel: [ 636.804426] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.804470] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:46 BXT-2 kernel: [ 636.804478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.804520] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:46 BXT-2 kernel: [ 636.804876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.804934] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.804978] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:46 BXT-2 kernel: [ 636.805021] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:46 BXT-2 kernel: [ 636.805065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:46 BXT-2 kernel: [ 636.805108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.805162] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:46 BXT-2 kernel: [ 636.805237] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:46 BXT-2 kernel: [ 636.805282] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.805325] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.805369] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.805438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.805493] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.805537] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.806698] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.806738] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.807028] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:46 BXT-2 kernel: [ 636.807082] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.807123] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.807479] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.807733] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.808056] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.808101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.808144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.808486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.808532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.808576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.808622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.808665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.808708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.808752] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.808801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.808846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.808920] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.808963] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.810851] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.810897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.810942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:46 BXT-2 kernel: [ 636.811795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.811840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.812640] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:46 BXT-2 kernel: [ 636.812687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:46 BXT-2 kernel: [ 636.813743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:46 BXT-2 kernel: [ 636.815861] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:46 BXT-2 kernel: [ 636.816920] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.833790] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.833848] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.834022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.950840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.950979] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.968699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.968811] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.968892] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.969274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.969323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.969367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.969410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.969454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.969498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.969547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.969590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.969634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.969678] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.969726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.969773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.969818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.969881] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.969924] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.969979] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.970042] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.970086] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.970131] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:46 BXT-2 kernel: [ 636.970170] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:46 BXT-2 kernel: [ 636.970757] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.971800] [drm:drm_mode_addfb2] [FB:78] >May 24 03:32:46 BXT-2 kernel: [ 636.989530] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:32:46 BXT-2 kernel: [ 636.989580] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:32:46 BXT-2 kernel: [ 636.989711] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:46 BXT-2 kernel: [ 636.989754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:46 BXT-2 kernel: [ 636.989799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:46 BXT-2 kernel: [ 636.989843] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:46 BXT-2 kernel: [ 636.989885] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:46 BXT-2 kernel: [ 636.989929] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.989972] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:32:46 BXT-2 kernel: [ 636.990014] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.990057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:46 BXT-2 kernel: [ 636.990100] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.990141] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:46 BXT-2 kernel: [ 636.990502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.990558] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:46 BXT-2 kernel: [ 636.990565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.990609] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:46 BXT-2 kernel: [ 636.990653] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:46 BXT-2 kernel: [ 636.990696] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:46 BXT-2 kernel: [ 636.990739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:46 BXT-2 kernel: [ 636.990782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:46 BXT-2 kernel: [ 636.990828] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:46 BXT-2 kernel: [ 636.990871] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:46 BXT-2 kernel: [ 636.990915] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.990958] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.991001] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:32:46 BXT-2 kernel: [ 636.991068] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.991122] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.991166] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:32:46 BXT-2 kernel: [ 636.992159] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:46 BXT-2 kernel: [ 636.992258] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:46 BXT-2 kernel: [ 636.992555] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:46 BXT-2 kernel: [ 636.992610] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.992652] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:46 BXT-2 kernel: [ 636.992709] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:46 BXT-2 kernel: [ 636.992954] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.993278] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:46 BXT-2 kernel: [ 636.993324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:46 BXT-2 kernel: [ 636.993368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.993413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.993456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.993501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:46 BXT-2 kernel: [ 636.993544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:46 BXT-2 kernel: [ 636.993587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:46 BXT-2 kernel: [ 636.993631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:46 BXT-2 kernel: [ 636.993674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:46 BXT-2 kernel: [ 636.993721] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:46 BXT-2 kernel: [ 636.993766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.993844] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:32:46 BXT-2 kernel: [ 636.993887] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:46 BXT-2 kernel: [ 636.995333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.995377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.995421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:46 BXT-2 kernel: [ 636.996173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.996267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:46 BXT-2 kernel: [ 636.996991] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:46 BXT-2 kernel: [ 636.997035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:46 BXT-2 kernel: [ 636.998156] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:47 BXT-2 kernel: [ 637.000268] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:47 BXT-2 kernel: [ 637.001312] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:32:47 BXT-2 kernel: [ 637.018189] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.018311] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:47 BXT-2 kernel: [ 637.018485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.135056] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.135353] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:32:47 BXT-2 kernel: [ 637.153585] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:32:47 BXT-2 kernel: [ 637.153700] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.153780] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.154103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.154147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:47 BXT-2 kernel: [ 637.154270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:47 BXT-2 kernel: [ 637.154322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:47 BXT-2 kernel: [ 637.154367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:47 BXT-2 kernel: [ 637.154413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:47 BXT-2 kernel: [ 637.154464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:47 BXT-2 kernel: [ 637.154507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:47 BXT-2 kernel: [ 637.154553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:47 BXT-2 kernel: [ 637.154597] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.154646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:47 BXT-2 kernel: [ 637.154693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:47 BXT-2 kernel: [ 637.154739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.154803] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:32:47 BXT-2 kernel: [ 637.154846] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:32:47 BXT-2 kernel: [ 637.154901] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:32:47 BXT-2 kernel: [ 637.154965] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:32:47 BXT-2 kernel: [ 637.155010] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:32:47 BXT-2 kernel: [ 637.155055] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:32:47 BXT-2 kernel: [ 637.155094] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:32:47 BXT-2 kernel: [ 637.155708] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:32:47 BXT-2 kernel: [ 637.180383] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:32:47 BXT-2 kernel: [ 637.180426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:32:47 BXT-2 kernel: [ 637.180471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:32:47 BXT-2 kernel: [ 637.180513] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:32:47 BXT-2 kernel: [ 637.180554] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:32:47 BXT-2 kernel: [ 637.180598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.180641] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:32:47 BXT-2 kernel: [ 637.180683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.180725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:32:47 BXT-2 kernel: [ 637.180766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.180807] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:47 BXT-2 kernel: [ 637.180815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.180855] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:47 BXT-2 kernel: [ 637.180860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.180902] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.180944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:47 BXT-2 kernel: [ 637.180985] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:47 BXT-2 kernel: [ 637.181027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:47 BXT-2 kernel: [ 637.181068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.181111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:47 BXT-2 kernel: [ 637.181153] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:47 BXT-2 kernel: [ 637.181352] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.181395] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.181436] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.181478] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.181529] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:32:47 BXT-2 kernel: [ 637.181570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:32:47 BXT-2 kernel: [ 637.181613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:32:47 BXT-2 kernel: [ 637.181656] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:32:47 BXT-2 kernel: [ 637.181697] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.181740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.181782] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:32:47 BXT-2 kernel: [ 637.181824] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.181865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:32:47 BXT-2 kernel: [ 637.181906] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.181947] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:32:47 BXT-2 kernel: [ 637.181954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.181995] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:32:47 BXT-2 kernel: [ 637.182000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.182041] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.182083] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:32:47 BXT-2 kernel: [ 637.182230] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:32:47 BXT-2 kernel: [ 637.182272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:32:47 BXT-2 kernel: [ 637.182313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:32:47 BXT-2 kernel: [ 637.182358] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:32:47 BXT-2 kernel: [ 637.182398] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:32:47 BXT-2 kernel: [ 637.182440] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.182482] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.182523] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.182565] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:32:47 BXT-2 kernel: [ 637.182611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.182665] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:32:47 BXT-2 kernel: [ 637.182707] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:32:47 BXT-2 kernel: [ 637.182750] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.182791] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:32:47 BXT-2 kernel: [ 637.182916] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:32:47 BXT-2 kernel: [ 637.182952] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:32:47 BXT-2 kernel: [ 637.183317] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:32:47 BXT-2 kernel: [ 637.183881] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:32:47 BXT-2 kernel: [ 637.183922] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:32:47 BXT-2 kernel: [ 637.183978] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:32:47 BXT-2 kernel: [ 637.184262] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.184587] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.184629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:32:47 BXT-2 kernel: [ 637.184671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:32:47 BXT-2 kernel: [ 637.184712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:32:47 BXT-2 kernel: [ 637.184754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:32:47 BXT-2 kernel: [ 637.184795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:32:47 BXT-2 kernel: [ 637.184837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:32:47 BXT-2 kernel: [ 637.184878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:32:47 BXT-2 kernel: [ 637.184919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:32:47 BXT-2 kernel: [ 637.184961] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:32:47 BXT-2 kernel: [ 637.185006] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:47 BXT-2 kernel: [ 637.185050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.185123] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:32:47 BXT-2 kernel: [ 637.185165] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:32:47 BXT-2 kernel: [ 637.186619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:47 BXT-2 kernel: [ 637.186660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:47 BXT-2 kernel: [ 637.186703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:47 BXT-2 kernel: [ 637.205634] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:47 BXT-2 kernel: [ 637.205677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:32:47 BXT-2 kernel: [ 637.223717] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:47 BXT-2 kernel: [ 637.225797] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:32:47 BXT-2 kernel: [ 637.226925] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:32:47 BXT-2 kernel: [ 637.227008] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:32:47 BXT-2 kernel: [ 637.227049] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:32:47 BXT-2 kernel: [ 637.227105] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:32:47 BXT-2 kernel: [ 637.227303] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:32:47 BXT-2 kernel: [ 637.227345] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.228764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:47 BXT-2 kernel: [ 637.228806] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:47 BXT-2 kernel: [ 637.228849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:32:47 BXT-2 kernel: [ 637.229636] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:32:47 BXT-2 kernel: [ 637.229677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:32:47 BXT-2 kernel: [ 637.230416] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:32:47 BXT-2 kernel: [ 637.230458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:32:47 BXT-2 kernel: [ 637.231495] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:32:47 BXT-2 kernel: [ 637.233240] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:32:47 BXT-2 kernel: [ 637.234402] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:32:47 BXT-2 kernel: [ 637.251362] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:47 BXT-2 kernel: [ 637.251416] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:32:47 BXT-2 kernel: [ 637.251591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:32:47 BXT-2 kernel: [ 637.251765] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.251817] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:32:47 BXT-2 kernel: [ 637.251990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:32:47 BXT-2 kernel: [ 637.252449] Console: switching to colour frame buffer device 240x67 >May 24 03:32:47 BXT-2 kernel: [ 637.626505] Console: switching to colour dummy device 80x25 >May 24 03:32:47 BXT-2 kernel: [ 637.642740] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:47 BXT-2 kernel: [ 637.642806] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:47 BXT-2 kernel: [ 637.643593] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:47 BXT-2 kernel: [ 637.644451] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:47 BXT-2 kernel: [ 637.644496] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.644539] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.644581] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.645053] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:47 BXT-2 kernel: [ 637.645516] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:47 BXT-2 kernel: [ 637.646447] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.647716] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.648959] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.650363] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.651759] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.653014] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.654263] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.655519] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.656787] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.658259] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.659654] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.661042] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.662446] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.663812] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.665210] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.666624] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.667924] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.669219] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.670477] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.671738] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.672983] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.674375] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.675757] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.677137] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.678520] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.679923] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.681317] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.682692] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.684065] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.684863] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:47 BXT-2 kernel: [ 637.685627] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.685634] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:47 BXT-2 kernel: [ 637.685639] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:47 BXT-2 kernel: [ 637.685644] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:47 BXT-2 kernel: [ 637.685887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:47 BXT-2 kernel: [ 637.685894] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685899] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685904] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:47 BXT-2 kernel: [ 637.685909] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:47 BXT-2 kernel: [ 637.685915] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685920] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:47 BXT-2 kernel: [ 637.685925] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:47 BXT-2 kernel: [ 637.685930] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685935] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685940] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:47 BXT-2 kernel: [ 637.685945] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685950] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685955] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685960] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685966] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685971] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.685976] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.685981] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.685986] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.685991] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.685996] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686001] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686006] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.686011] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.686016] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.686022] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.686027] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686032] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686037] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686042] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686047] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686052] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686057] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.686062] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:47 BXT-2 kernel: [ 637.686184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.686242] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.686793] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:47 BXT-2 kernel: [ 637.687696] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:47 BXT-2 kernel: [ 637.687745] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.687789] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:47 BXT-2 kernel: [ 637.687832] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:47 BXT-2 kernel: [ 637.688336] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:47 BXT-2 kernel: [ 637.688380] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:47 BXT-2 kernel: [ 637.693118] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:47 BXT-2 kernel: [ 637.693238] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:47 BXT-2 kernel: [ 637.693245] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693251] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693256] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693261] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693266] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693271] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693276] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.693281] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693287] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.693292] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.693298] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.693303] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:47 BXT-2 kernel: [ 637.700217] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:32:47 BXT-2 kernel: [ 637.700285] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:32:47 BXT-2 kernel: [ 637.700831] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:32:47 BXT-2 kernel: [ 637.701759] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:32:47 BXT-2 kernel: [ 637.701805] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.701847] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.701890] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.702384] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:32:47 BXT-2 kernel: [ 637.703072] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:47 BXT-2 kernel: [ 637.703933] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.705221] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.706469] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.707718] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.708975] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.710234] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.711490] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.712740] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.713986] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.720606] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.722092] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.723499] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.725057] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.726474] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.727857] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.729391] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.730923] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.732209] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.733522] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.735372] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.736957] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.738446] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.740273] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.741940] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.743381] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.744842] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.746291] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.747712] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.749124] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:32:47 BXT-2 kernel: [ 637.749946] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:32:47 BXT-2 kernel: [ 637.750747] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:32:47 BXT-2 kernel: [ 637.750755] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:32:47 BXT-2 kernel: [ 637.750760] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:32:47 BXT-2 kernel: [ 637.750765] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:32:47 BXT-2 kernel: [ 637.750998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:32:47 BXT-2 kernel: [ 637.751005] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751011] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751016] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:47 BXT-2 kernel: [ 637.751021] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:47 BXT-2 kernel: [ 637.751026] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751031] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:32:47 BXT-2 kernel: [ 637.751036] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:32:47 BXT-2 kernel: [ 637.751041] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751046] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751051] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:32:47 BXT-2 kernel: [ 637.751056] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751061] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751066] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751071] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751076] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751081] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751086] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751091] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751096] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751101] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751107] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751112] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751117] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751122] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751127] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751132] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.751137] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751142] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751173] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751178] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751187] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751195] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751202] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.751209] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:32:47 BXT-2 kernel: [ 637.751590] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.751649] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:32:47 BXT-2 kernel: [ 637.752244] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:32:47 BXT-2 kernel: [ 637.753149] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:32:47 BXT-2 kernel: [ 637.753325] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:32:47 BXT-2 kernel: [ 637.753368] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:32:47 BXT-2 kernel: [ 637.753410] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:32:47 BXT-2 kernel: [ 637.753928] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:32:47 BXT-2 kernel: [ 637.753972] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:32:47 BXT-2 kernel: [ 637.758919] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:32:47 BXT-2 kernel: [ 637.758985] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:32:47 BXT-2 kernel: [ 637.758993] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.758998] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759003] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759008] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759013] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759018] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759023] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.759028] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759033] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:32:47 BXT-2 kernel: [ 637.759038] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.759043] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:32:47 BXT-2 kernel: [ 637.759048] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:33:04 BXT-2 kernel: [ 637.894237] PM: Syncing filesystems ... done. >May 24 03:33:04 BXT-2 kernel: [ 637.908847] PM: Preparing system for sleep (mem) >May 24 03:33:04 BXT-2 kernel: [ 637.909641] Freezing user space processes ... >May 24 03:33:04 BXT-2 kernel: [ 638.797018] hpet1: lost 7160 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 639.723183] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 640.645243] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 641.564196] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 642.491272] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 643.411020] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 644.340220] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 645.253384] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 646.169283] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 647.104024] hpet1: lost 7160 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 648.039248] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 648.974404] hpet1: lost 7160 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 649.612796] (elapsed 11.703 seconds) done. >May 24 03:33:04 BXT-2 kernel: [ 649.612814] OOM killer disabled. >May 24 03:33:04 BXT-2 kernel: [ 649.612818] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 03:33:04 BXT-2 kernel: [ 649.614378] PM: Suspending system (mem) >May 24 03:33:04 BXT-2 kernel: [ 649.614480] Suspending console(s) (use no_console_suspend to debug) >May 24 03:33:04 BXT-2 kernel: [ 649.741689] system 00:00: System wakeup disabled by ACPI >May 24 03:33:04 BXT-2 kernel: [ 649.742134] sd 0:0:0:0: [sda] Synchronizing SCSI cache >May 24 03:33:04 BXT-2 kernel: [ 649.742414] ACPI : EC: event blocked >May 24 03:33:04 BXT-2 kernel: [ 649.745457] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:33:04 BXT-2 kernel: [ 649.753412] sd 0:0:0:0: [sda] Stopping disk >May 24 03:33:04 BXT-2 kernel: [ 649.762008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:04 BXT-2 kernel: [ 649.762160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:33:04 BXT-2 kernel: [ 649.762343] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:33:04 BXT-2 kernel: [ 649.762548] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:04 BXT-2 kernel: [ 649.778267] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:33:04 BXT-2 kernel: [ 649.778375] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 649.778466] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:33:04 BXT-2 kernel: [ 649.784871] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:33:04 BXT-2 kernel: [ 649.784975] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 649.785055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 649.785378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 649.785422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 649.785470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 649.785513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 649.785557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 649.785599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 649.785645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 649.785687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 649.785729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 649.785773] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 649.785820] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 649.785866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 649.785910] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 649.785954] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 649.786033] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:04 BXT-2 kernel: [ 649.786090] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:33:04 BXT-2 kernel: [ 649.899470] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 650.751222] PM: suspend of devices complete after 1014.988 msecs >May 24 03:33:04 BXT-2 kernel: [ 650.761983] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 650.762026] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:33:04 BXT-2 kernel: [ 650.762065] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 650.762116] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 650.762155] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:04 BXT-2 kernel: [ 650.762216] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:04 BXT-2 kernel: [ 650.762254] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:04 BXT-2 kernel: [ 650.762805] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:04 BXT-2 kernel: [ 650.762844] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:04 BXT-2 kernel: [ 650.763216] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 650.763253] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:04 BXT-2 kernel: [ 650.763297] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:04 BXT-2 kernel: [ 650.763337] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:04 BXT-2 kernel: [ 650.763382] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:04 BXT-2 kernel: [ 650.763422] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:04 BXT-2 kernel: [ 650.775251] PM: late suspend of devices complete after 24.021 msecs >May 24 03:33:04 BXT-2 kernel: [ 650.791423] hpet1: lost 7161 rtc interrupts >May 24 03:33:04 BXT-2 kernel: [ 650.793824] ACPI : EC: interrupt blocked >May 24 03:33:04 BXT-2 kernel: [ 650.793855] r8169 0000:03:00.0: System wakeup enabled by ACPI >May 24 03:33:04 BXT-2 kernel: [ 650.794604] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI >May 24 03:33:04 BXT-2 kernel: [ 650.817336] PM: noirq suspend of devices complete after 42.076 msecs >May 24 03:33:04 BXT-2 kernel: [ 650.817563] ACPI: Preparing to enter system sleep state S3 >May 24 03:33:04 BXT-2 kernel: [ 650.821726] ACPI : EC: EC stopped >May 24 03:33:04 BXT-2 kernel: [ 650.821730] PM: Saving platform NVS memory >May 24 03:33:04 BXT-2 kernel: [ 650.821745] Disabling non-boot CPUs ... >May 24 03:33:04 BXT-2 kernel: [ 650.836672] Broke affinity for irq 369 >May 24 03:33:04 BXT-2 kernel: [ 650.836687] Broke affinity for irq 370 >May 24 03:33:04 BXT-2 kernel: [ 650.836701] Broke affinity for irq 371 >May 24 03:33:04 BXT-2 kernel: [ 650.836716] Broke affinity for irq 373 >May 24 03:33:04 BXT-2 kernel: [ 650.837948] smpboot: CPU 1 is now offline >May 24 03:33:04 BXT-2 kernel: [ 650.859985] Broke affinity for irq 369 >May 24 03:33:04 BXT-2 kernel: [ 650.860002] Broke affinity for irq 370 >May 24 03:33:04 BXT-2 kernel: [ 650.860015] Broke affinity for irq 371 >May 24 03:33:04 BXT-2 kernel: [ 650.860031] Broke affinity for irq 373 >May 24 03:33:04 BXT-2 kernel: [ 650.861298] smpboot: CPU 2 is now offline >May 24 03:33:04 BXT-2 kernel: [ 650.875829] Broke affinity for irq 1 >May 24 03:33:04 BXT-2 kernel: [ 650.875845] Broke affinity for irq 8 >May 24 03:33:04 BXT-2 kernel: [ 650.875856] Broke affinity for irq 9 >May 24 03:33:04 BXT-2 kernel: [ 650.875868] Broke affinity for irq 12 >May 24 03:33:04 BXT-2 kernel: [ 650.875880] Broke affinity for irq 14 >May 24 03:33:04 BXT-2 kernel: [ 650.876062] Broke affinity for irq 367 >May 24 03:33:04 BXT-2 kernel: [ 650.876073] Broke affinity for irq 368 >May 24 03:33:04 BXT-2 kernel: [ 650.876082] Broke affinity for irq 369 >May 24 03:33:04 BXT-2 kernel: [ 650.876092] Broke affinity for irq 370 >May 24 03:33:04 BXT-2 kernel: [ 650.876102] Broke affinity for irq 371 >May 24 03:33:04 BXT-2 kernel: [ 650.876112] Broke affinity for irq 372 >May 24 03:33:04 BXT-2 kernel: [ 650.876122] Broke affinity for irq 373 >May 24 03:33:04 BXT-2 kernel: [ 650.877249] smpboot: CPU 3 is now offline >May 24 03:33:04 BXT-2 kernel: [ 650.883937] ACPI: Low-level resume complete >May 24 03:33:04 BXT-2 kernel: [ 650.884533] ACPI : EC: EC started >May 24 03:33:04 BXT-2 kernel: [ 650.884545] PM: Restoring platform NVS memory >May 24 03:33:04 BXT-2 kernel: [ 650.885900] Suspended for 3.119 seconds >May 24 03:33:04 BXT-2 kernel: [ 650.886287] Enabling non-boot CPUs ... >May 24 03:33:04 BXT-2 kernel: [ 650.886860] x86: Booting SMP configuration: >May 24 03:33:04 BXT-2 kernel: [ 650.886877] smpboot: Booting Node 0 Processor 1 APIC 0x2 >May 24 03:33:04 BXT-2 kernel: [ 650.899083] cache: parent cpu1 should not be sleeping >May 24 03:33:04 BXT-2 kernel: [ 650.903681] CPU1 is up >May 24 03:33:04 BXT-2 kernel: [ 650.903900] smpboot: Booting Node 0 Processor 2 APIC 0x4 >May 24 03:33:04 BXT-2 kernel: [ 650.911524] cache: parent cpu2 should not be sleeping >May 24 03:33:04 BXT-2 kernel: [ 650.914430] CPU2 is up >May 24 03:33:04 BXT-2 kernel: [ 650.915599] smpboot: Booting Node 0 Processor 3 APIC 0x6 >May 24 03:33:04 BXT-2 kernel: [ 650.923265] cache: parent cpu3 should not be sleeping >May 24 03:33:04 BXT-2 kernel: [ 650.926713] CPU3 is up >May 24 03:33:04 BXT-2 kernel: [ 650.930147] ACPI: Waking up from system sleep state S3 >May 24 03:33:04 BXT-2 kernel: [ 650.940061] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI >May 24 03:33:04 BXT-2 kernel: [ 650.940311] ACPI : EC: interrupt unblocked >May 24 03:33:04 BXT-2 kernel: [ 650.963822] PM: noirq resume of devices complete after 24.468 msecs >May 24 03:33:04 BXT-2 kernel: [ 650.964484] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00 >May 24 03:33:04 BXT-2 kernel: [ 650.964593] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:04 BXT-2 kernel: [ 650.964662] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:04 BXT-2 kernel: [ 650.964806] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 03:33:04 BXT-2 kernel: [ 650.964959] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:04 BXT-2 kernel: [ 650.965039] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:04 BXT-2 kernel: [ 650.965134] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 650.965212] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:04 BXT-2 kernel: [ 650.967517] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 650.969645] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:04 BXT-2 kernel: [ 650.969711] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:04 BXT-2 kernel: [ 650.969779] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:04 BXT-2 kernel: [ 650.969861] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 650.969933] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:33:04 BXT-2 kernel: [ 650.970080] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 650.978545] PM: early resume of devices complete after 14.371 msecs >May 24 03:33:04 BXT-2 kernel: [ 650.979340] ACPI : EC: event unblocked >May 24 03:33:04 BXT-2 kernel: [ 650.979401] r8169 0000:03:00.0: System wakeup disabled by ACPI >May 24 03:33:04 BXT-2 kernel: [ 650.979957] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 03:33:04 BXT-2 kernel: [ 650.989012] sd 0:0:0:0: [sda] Starting disk >May 24 03:33:04 BXT-2 kernel: [ 650.991601] r8169 0000:03:00.0 enp3s0: link down >May 24 03:33:04 BXT-2 kernel: [ 651.090025] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:33:04 BXT-2 kernel: [ 651.090157] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:33:04 BXT-2 kernel: [ 651.090200] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:33:04 BXT-2 kernel: [ 651.090282] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:33:04 BXT-2 kernel: [ 651.090405] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38 >May 24 03:33:04 BXT-2 kernel: [ 651.090720] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:33:04 BXT-2 kernel: [ 651.090782] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:33:04 BXT-2 kernel: [ 651.090889] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:33:04 BXT-2 kernel: [ 651.090996] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:33:04 BXT-2 kernel: [ 651.091102] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:33:04 BXT-2 kernel: [ 651.091184] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.091243] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:04 BXT-2 kernel: [ 651.091334] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.091376] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:33:04 BXT-2 kernel: [ 651.091427] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.091469] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:33:04 BXT-2 kernel: [ 651.091568] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.091610] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:33:04 BXT-2 kernel: [ 651.091658] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:33:04 BXT-2 kernel: [ 651.091702] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:33:04 BXT-2 kernel: [ 651.091747] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:33:04 BXT-2 kernel: [ 651.091793] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.091836] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.091878] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:33:04 BXT-2 kernel: [ 651.091922] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:33:04 BXT-2 kernel: [ 651.091967] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.092009] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.092051] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:33:04 BXT-2 kernel: [ 651.092095] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:33:04 BXT-2 kernel: [ 651.092144] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:33:04 BXT-2 kernel: [ 651.092191] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:33:04 BXT-2 kernel: [ 651.092244] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:33:04 BXT-2 kernel: [ 651.092287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.092329] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.092370] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.092378] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.092419] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.092424] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.092466] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.092528] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:33:04 BXT-2 kernel: [ 651.092570] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.092611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.092652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.092698] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.092739] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.092782] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.092824] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.092868] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.092912] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.092956] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:33:04 BXT-2 kernel: [ 651.092998] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093039] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093080] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.093085] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093126] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.093131] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093173] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093215] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093256] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.093339] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093381] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093423] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.093468] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.093527] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.093569] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.093611] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.093655] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:33:04 BXT-2 kernel: [ 651.093696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093738] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093779] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.093784] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093824] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.093829] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093871] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.093913] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093954] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.093996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.094037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.094080] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:33:04 BXT-2 kernel: [ 651.094121] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.094165] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.094208] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.094251] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.094415] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.094458] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:33:04 BXT-2 kernel: [ 651.094513] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.094567] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.094609] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.094653] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:04 BXT-2 kernel: [ 651.094692] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:04 BXT-2 kernel: [ 651.095237] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.095319] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.095361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.095405] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.095448] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:33:04 BXT-2 kernel: [ 651.095505] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:33:04 BXT-2 kernel: [ 651.095549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.095591] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:04 BXT-2 kernel: [ 651.095632] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.095674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:33:04 BXT-2 kernel: [ 651.095715] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.095756] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.095761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.095802] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.095807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.095850] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.095891] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:04 BXT-2 kernel: [ 651.095933] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.095974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.096016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.096059] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.096100] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.096141] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.096182] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.096224] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.096265] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.096310] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.096352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.096394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.096436] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:04 BXT-2 kernel: [ 651.096477] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:04 BXT-2 kernel: [ 651.096533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.096575] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:33:04 BXT-2 kernel: [ 651.096616] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.096658] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:04 BXT-2 kernel: [ 651.096699] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.096740] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.096745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.096786] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.096791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.096833] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.096875] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:04 BXT-2 kernel: [ 651.096917] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.096958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.096999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.097044] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.097085] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.097127] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.097168] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.097210] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.097251] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.097297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.097350] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.097392] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.097437] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.097479] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:33:04 BXT-2 kernel: [ 651.097656] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.097693] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.097979] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:04 BXT-2 kernel: [ 651.098031] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.098070] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.098124] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.098430] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.098743] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.098788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.098830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.098871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.098913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.098955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 651.098998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.099040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.099082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.099127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 651.099172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.099215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.099289] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:33:04 BXT-2 kernel: [ 651.099333] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.100758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.100799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.100842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:04 BXT-2 kernel: [ 651.136288] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -5 >May 24 03:33:04 BXT-2 kernel: [ 651.136354] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training >May 24 03:33:04 BXT-2 kernel: [ 651.136418] [drm:intel_dp_start_link_train [i915]] Link Training failed at link rate = 162000, lane count = 4 >May 24 03:33:04 BXT-2 kernel: [ 651.136733] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.138412] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.138538] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.138600] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:33:04 BXT-2 kernel: [ 651.138700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:33:04 BXT-2 kernel: [ 651.138931] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:33:04 BXT-2 kernel: [ 651.138993] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.140484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.140563] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.140618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:04 BXT-2 kernel: [ 651.141414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.141464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.142249] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:04 BXT-2 kernel: [ 651.142300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:04 BXT-2 kernel: [ 651.143378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:04 BXT-2 kernel: [ 651.145467] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:04 BXT-2 kernel: [ 651.146729] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:33:04 BXT-2 kernel: [ 651.163667] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.163741] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:04 BXT-2 kernel: [ 651.163947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.164158] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 651.164232] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:33:04 BXT-2 kernel: [ 651.164438] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.164610] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:04 BXT-2 kernel: [ 651.165578] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:04 BXT-2 kernel: [ 651.165665] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.165696] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from connected to disconnected >May 24 03:33:04 BXT-2 kernel: [ 651.165760] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 651.165888] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:33:04 BXT-2 kernel: [ 651.168842] PM: resume of devices complete after 190.288 msecs >May 24 03:33:04 BXT-2 kernel: [ 651.169016] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:04 BXT-2 kernel: [ 651.170152] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:04 BXT-2 kernel: [ 651.170233] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:04 BXT-2 kernel: [ 651.170311] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:04 BXT-2 kernel: [ 651.170387] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:04 BXT-2 kernel: [ 651.171001] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:04 BXT-2 kernel: [ 651.171078] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:04 BXT-2 kernel: [ 651.172027] PM: Finishing wakeup. >May 24 03:33:04 BXT-2 kernel: [ 651.172035] OOM killer enabled. >May 24 03:33:04 BXT-2 kernel: [ 651.172040] Restarting tasks ... done. >May 24 03:33:04 BXT-2 kernel: [ 651.178586] video LNXVIDEO:00: Restoring backlight state >May 24 03:33:04 BXT-2 kernel: [ 651.183999] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:04 BXT-2 kernel: [ 651.186018] [drm:drm_mode_addfb2] [FB:103] >May 24 03:33:04 BXT-2 kernel: [ 651.212209] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:04 BXT-2 kernel: [ 651.212368] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.218570] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.218631] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:33:04 BXT-2 kernel: [ 651.218723] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.222796] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:33:04 BXT-2 kernel: [ 651.222914] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.223004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.223051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.223094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.223137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.223180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 651.223223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.223266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.223309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.223354] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.223404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 651.223450] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.223536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.230237] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:04 BXT-2 kernel: [ 651.230694] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:33:04 BXT-2 kernel: [ 651.230841] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.230964] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:33:04 BXT-2 NetworkManager[807]: <info> [1495614784.2900] device (enp3s0): link disconnected >May 24 03:33:04 BXT-2 kernel: [ 651.248794] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:33:04 BXT-2 kernel: [ 651.248906] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.248995] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.249311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.249355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.249399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.249442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.249486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.249568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 651.249616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.249664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.249710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.249756] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 651.249806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 651.249853] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.249898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.249963] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.250006] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.250059] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.250121] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:33:04 BXT-2 kernel: [ 651.250166] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.250211] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:04 BXT-2 kernel: [ 651.250250] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:04 BXT-2 kernel: [ 651.250849] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.252642] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:04 BXT-2 kernel: [ 651.252697] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.252815] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.252860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.252905] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 540000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.252948] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:04 BXT-2 kernel: [ 651.252991] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:04 BXT-2 kernel: [ 651.253035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.253078] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:33:04 BXT-2 kernel: [ 651.253120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.253164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:04 BXT-2 kernel: [ 651.253206] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.253248] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.253255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.253297] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.253303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.253346] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.253389] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:04 BXT-2 kernel: [ 651.253431] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.253474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.253558] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.253608] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.253653] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.253700] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.253746] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.253791] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.253857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.253912] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.253957] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:33:04 BXT-2 kernel: [ 651.254546] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.254586] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.254879] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:04 BXT-2 kernel: [ 651.254934] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.254976] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.255034] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.255299] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.255624] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.255670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.255715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.255758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.255802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.255846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 651.255890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.255933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.255977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.256020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 651.256069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.256115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.256191] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:33:04 BXT-2 kernel: [ 651.256235] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.257693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.257739] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.257784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:04 BXT-2 kernel: [ 651.293216] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -5 >May 24 03:33:04 BXT-2 kernel: [ 651.293277] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training >May 24 03:33:04 BXT-2 kernel: [ 651.293326] [drm:intel_dp_start_link_train [i915]] Link Training failed at link rate = 270000, lane count = 2 >May 24 03:33:04 BXT-2 kernel: [ 651.293423] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.294346] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:33:04 BXT-2 kernel: [ 651.294718] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:33:04 BXT-2 kernel: [ 651.311715] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.311774] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:04 BXT-2 kernel: [ 651.311947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.395189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.395326] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:33:04 BXT-2 kernel: [ 651.413134] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:33:04 BXT-2 kernel: [ 651.413251] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.413333] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.413740] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.413788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.413839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.413882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.413925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.413969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 651.414011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.414055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.414098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.414142] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.414191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 651.414238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.414283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.414362] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.414407] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.414462] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.414581] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:04 BXT-2 kernel: [ 651.414629] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.414673] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:04 BXT-2 kernel: [ 651.414712] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:04 BXT-2 kernel: [ 651.415273] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.417365] [drm:drm_mode_addfb2] [FB:103] >May 24 03:33:04 BXT-2 kernel: [ 651.434202] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:04 BXT-2 kernel: [ 651.434264] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.434395] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.434440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.434485] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 162000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.434932] [drm:intel_atomic_check [i915]] Encoder config failure >May 24 03:33:04 BXT-2 kernel: [ 651.435049] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][failed] >May 24 03:33:04 BXT-2 kernel: [ 651.435093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.435136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 0; gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.435179] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.435221] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.435236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.435280] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.435289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.435335] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.435382] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 1920x1080, pixel rate 0 >May 24 03:33:04 BXT-2 kernel: [ 651.435427] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.435472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.436011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.436057] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.436100] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.436145] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.436188] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.436231] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.456575] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:33:04 BXT-2 kernel: [ 651.497592] ata1.00: configured for UDMA/133 >May 24 03:33:04 BXT-2 kernel: [ 651.505139] [drm] RC6 on >May 24 03:33:04 BXT-2 kernel: [ 651.528549] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.528593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.528636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 162000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.528679] [drm:intel_atomic_check [i915]] Encoder config failure >May 24 03:33:04 BXT-2 kernel: [ 651.528721] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][failed] >May 24 03:33:04 BXT-2 kernel: [ 651.528763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.528805] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 0; gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.528846] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.528887] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.528895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.528936] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.528940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.528983] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.529025] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 1920x1080, pixel rate 0 >May 24 03:33:04 BXT-2 kernel: [ 651.529067] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.529109] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.529151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.529196] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.529237] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.529280] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.529322] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.529364] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.529405] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.529737] Console: switching to colour frame buffer device 240x67 >May 24 03:33:04 BXT-2 kernel: [ 651.554959] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.555007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.555052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 162000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.555095] [drm:intel_atomic_check [i915]] Encoder config failure >May 24 03:33:04 BXT-2 kernel: [ 651.555138] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][failed] >May 24 03:33:04 BXT-2 kernel: [ 651.555181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.555224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 0; gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.555267] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.555309] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.555318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.555360] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.555366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.555409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.555452] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 1920x1080, pixel rate 0 >May 24 03:33:04 BXT-2 kernel: [ 651.556136] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.556180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.556223] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.556269] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.556311] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.556354] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.556397] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.556440] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.556483] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.556988] [drm:drm_fb_helper_hotplug_event] >May 24 03:33:04 BXT-2 kernel: [ 651.556993] [drm:drm_setup_crtcs] >May 24 03:33:04 BXT-2 kernel: [ 651.557001] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.557066] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:04 BXT-2 kernel: [ 651.557109] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.557146] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.560025] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:04 BXT-2 kernel: [ 651.560330] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.560371] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.560426] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.561373] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.561417] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.568644] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.568690] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.568733] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:04 BXT-2 kernel: [ 651.568773] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:04 BXT-2 kernel: [ 651.569319] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.569331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:33:04 BXT-2 kernel: [ 651.569880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 651.569943] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 651.569985] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.570023] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.570148] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:04 BXT-2 kernel: [ 651.570202] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.570242] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.570296] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.571427] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:04 BXT-2 kernel: [ 651.572362] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:04 BXT-2 kernel: [ 651.572408] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:04 BXT-2 kernel: [ 651.572450] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:04 BXT-2 kernel: [ 651.572807] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:04 BXT-2 kernel: [ 651.573317] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:04 BXT-2 kernel: [ 651.573360] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:04 BXT-2 kernel: [ 651.583830] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.583876] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.583932] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.583973] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.584017] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:04 BXT-2 kernel: [ 651.584056] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:04 BXT-2 kernel: [ 651.585258] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.585375] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:33:04 BXT-2 kernel: [ 651.585444] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:33:04 BXT-2 kernel: [ 651.585793] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585800] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585805] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585810] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585815] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585820] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585826] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:33:04 BXT-2 kernel: [ 651.585831] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585836] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.585841] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:33:04 BXT-2 kernel: [ 651.585846] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:33:04 BXT-2 kernel: [ 651.585852] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:33:04 BXT-2 kernel: [ 651.585879] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:33:04 BXT-2 kernel: [ 651.585883] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:33:04 BXT-2 kernel: [ 651.585943] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:33:04 BXT-2 kernel: [ 651.585956] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:33:04 BXT-2 kernel: [ 651.585960] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:33:04 BXT-2 kernel: [ 651.585964] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:33:04 BXT-2 kernel: [ 651.585968] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:33:04 BXT-2 kernel: [ 651.585995] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:33:04 BXT-2 kernel: [ 651.586238] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:04 BXT-2 kernel: [ 651.586281] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:04 BXT-2 kernel: [ 651.586326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:04 BXT-2 kernel: [ 651.586370] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:04 BXT-2 kernel: [ 651.586412] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:04 BXT-2 kernel: [ 651.586457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.587442] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:04 BXT-2 kernel: [ 651.587486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.587684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:04 BXT-2 kernel: [ 651.587726] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.587768] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:04 BXT-2 kernel: [ 651.587776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.587818] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:04 BXT-2 kernel: [ 651.587824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.587868] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:04 BXT-2 kernel: [ 651.587910] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:04 BXT-2 kernel: [ 651.587954] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:04 BXT-2 kernel: [ 651.587996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:04 BXT-2 kernel: [ 651.588039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:04 BXT-2 kernel: [ 651.588084] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:04 BXT-2 kernel: [ 651.588126] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:04 BXT-2 kernel: [ 651.588170] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.588213] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.588256] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.588299] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:04 BXT-2 kernel: [ 651.588347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.588402] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.588446] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.589305] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:04 BXT-2 kernel: [ 651.589344] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:04 BXT-2 kernel: [ 651.589809] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:04 BXT-2 kernel: [ 651.590256] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.590296] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:04 BXT-2 kernel: [ 651.590352] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:04 BXT-2 kernel: [ 651.590850] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.591171] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:04 BXT-2 kernel: [ 651.591215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:04 BXT-2 kernel: [ 651.591258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.591301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.591344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.591387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:04 BXT-2 kernel: [ 651.591430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:04 BXT-2 kernel: [ 651.591473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:04 BXT-2 kernel: [ 651.591949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:04 BXT-2 kernel: [ 651.591993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:04 BXT-2 kernel: [ 651.592042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:04 BXT-2 kernel: [ 651.592088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.592163] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:04 BXT-2 kernel: [ 651.593346] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.594995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.595039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:04 BXT-2 kernel: [ 651.595084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:04 BXT-2 kernel: [ 651.596828] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:04 BXT-2 kernel: [ 651.596876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:04 BXT-2 kernel: [ 651.598000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:04 BXT-2 kernel: [ 651.602565] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:04 BXT-2 kernel: [ 651.603678] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:04 BXT-2 kernel: [ 651.620670] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:04 BXT-2 kernel: [ 651.620727] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:04 BXT-2 kernel: [ 651.620899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:04 BXT-2 kernel: [ 651.868059] Console: switching to colour dummy device 80x25 >May 24 03:33:05 BXT-2 kernel: [ 651.893023] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:33:05 BXT-2 kernel: [ 651.893085] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:05 BXT-2 kernel: [ 651.893101] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:33:05 BXT-2 kernel: [ 651.893124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.893169] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.894056] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:05 BXT-2 kernel: [ 651.895095] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:05 BXT-2 kernel: [ 651.895144] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:05 BXT-2 kernel: [ 651.895188] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:05 BXT-2 kernel: [ 651.895230] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:05 BXT-2 kernel: [ 651.896230] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:05 BXT-2 kernel: [ 651.896276] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:05 BXT-2 kernel: [ 651.902291] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:33:05 BXT-2 kernel: [ 651.902357] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:33:05 BXT-2 kernel: [ 651.902364] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902370] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902375] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902380] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902385] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902390] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902395] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:33:05 BXT-2 kernel: [ 651.902400] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902405] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.902410] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:33:05 BXT-2 kernel: [ 651.902415] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:33:05 BXT-2 kernel: [ 651.902420] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:33:05 BXT-2 kernel: [ 651.910260] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:33:05 BXT-2 kernel: [ 651.910322] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:05 BXT-2 kernel: [ 651.910338] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:33:05 BXT-2 kernel: [ 651.911041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.911108] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.912431] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:05 BXT-2 kernel: [ 651.913610] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:05 BXT-2 kernel: [ 651.913659] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:05 BXT-2 kernel: [ 651.913701] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:05 BXT-2 kernel: [ 651.913744] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:05 BXT-2 kernel: [ 651.914262] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:05 BXT-2 kernel: [ 651.914307] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:05 BXT-2 kernel: [ 651.919919] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:33:05 BXT-2 kernel: [ 651.919985] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:33:05 BXT-2 kernel: [ 651.919992] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.919998] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920003] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920008] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920013] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920018] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920023] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:33:05 BXT-2 kernel: [ 651.920028] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920033] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.920038] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:33:05 BXT-2 kernel: [ 651.920043] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:33:05 BXT-2 kernel: [ 651.920048] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:33:05 BXT-2 kernel: [ 651.921183] [drm:drm_mode_addfb2] [FB:78] >May 24 03:33:05 BXT-2 kernel: [ 651.940003] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:05 BXT-2 kernel: [ 651.940174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:05 BXT-2 kernel: [ 651.940338] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:05 BXT-2 kernel: [ 651.955886] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:05 BXT-2 kernel: [ 651.956000] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 651.956089] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 651.956415] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 651.956460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 651.956547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 651.956597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 651.956646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 651.956692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 651.956742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 651.956786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 651.956831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 651.956877] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.956926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 651.956974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 651.957020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 651.957082] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 651.957125] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 651.957181] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 651.957243] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:05 BXT-2 kernel: [ 651.957295] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:05 BXT-2 kernel: [ 651.957340] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:05 BXT-2 kernel: [ 651.957379] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:05 BXT-2 kernel: [ 651.958566] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:05 BXT-2 kernel: [ 651.959778] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:33:05 BXT-2 kernel: [ 651.962168] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 651.962221] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.962342] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:05 BXT-2 kernel: [ 651.962386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:05 BXT-2 kernel: [ 651.962431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:05 BXT-2 kernel: [ 651.962475] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:05 BXT-2 kernel: [ 651.962550] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:05 BXT-2 kernel: [ 651.962601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 651.962650] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:33:05 BXT-2 kernel: [ 651.962697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 651.962742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:05 BXT-2 kernel: [ 651.962785] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:05 BXT-2 kernel: [ 651.962830] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:05 BXT-2 kernel: [ 651.962840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.962882] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:05 BXT-2 kernel: [ 651.962890] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.962936] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:05 BXT-2 kernel: [ 651.962979] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:05 BXT-2 kernel: [ 651.963023] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:05 BXT-2 kernel: [ 651.963067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:05 BXT-2 kernel: [ 651.963110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:05 BXT-2 kernel: [ 651.963155] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:05 BXT-2 kernel: [ 651.963198] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:05 BXT-2 kernel: [ 651.963242] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 651.963285] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 651.963328] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 651.963395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:05 BXT-2 kernel: [ 651.963449] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 651.963521] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:33:05 BXT-2 kernel: [ 651.964112] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:05 BXT-2 kernel: [ 651.964151] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:05 BXT-2 kernel: [ 651.964440] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:05 BXT-2 kernel: [ 651.964523] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 651.964567] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 651.964626] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 651.965658] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 651.966188] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 651.966233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 651.966277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 651.966320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 651.966363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 651.966406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 651.966449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 651.966530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 651.966580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 651.966628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 651.966678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 651.966724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 651.966801] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 651.966845] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 651.969447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 651.969521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 651.969567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:05 BXT-2 kernel: [ 651.971323] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:05 BXT-2 kernel: [ 651.971464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:05 BXT-2 kernel: [ 651.973964] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:05 BXT-2 kernel: [ 651.975570] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:05 BXT-2 kernel: [ 651.977257] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 651.994197] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 651.994256] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 651.994428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.077687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.077822] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.095782] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.095896] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.095977] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.096304] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.096349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.096392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.096436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.096479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.096571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.096619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.096662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.096705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.096749] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.096797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.096842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.096888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.096952] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.096995] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.097049] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.097111] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.097155] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.097198] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:05 BXT-2 kernel: [ 652.097237] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:05 BXT-2 kernel: [ 652.097805] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.099689] [drm:drm_mode_addfb2] [FB:76] >May 24 03:33:05 BXT-2 kernel: [ 652.122791] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.122856] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.122987] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:05 BXT-2 kernel: [ 652.123031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:05 BXT-2 kernel: [ 652.123076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:05 BXT-2 kernel: [ 652.123120] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:05 BXT-2 kernel: [ 652.123163] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:05 BXT-2 kernel: [ 652.123207] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.123250] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:33:05 BXT-2 kernel: [ 652.123293] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.123336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:05 BXT-2 kernel: [ 652.123378] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.123420] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:05 BXT-2 kernel: [ 652.123427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.123469] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:05 BXT-2 kernel: [ 652.123520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.123566] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.123613] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:05 BXT-2 kernel: [ 652.123661] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:05 BXT-2 kernel: [ 652.123708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:05 BXT-2 kernel: [ 652.123753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.123801] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:05 BXT-2 kernel: [ 652.123846] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:05 BXT-2 kernel: [ 652.123893] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.123937] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.123981] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.124045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.124098] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.124145] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.124878] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.124919] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.125217] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:05 BXT-2 kernel: [ 652.125271] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.125311] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.125368] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.125664] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.125989] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.126033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.126076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.126120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.126163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.126206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.126249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.126292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.126334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.126378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.126424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.126469] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.126591] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.126634] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.128631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.128677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.128722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:05 BXT-2 kernel: [ 652.129484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.129760] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.130491] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:05 BXT-2 kernel: [ 652.130676] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:05 BXT-2 kernel: [ 652.131943] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:05 BXT-2 kernel: [ 652.134046] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:05 BXT-2 kernel: [ 652.135077] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.151950] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.152009] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.152181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.235651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.235788] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.253881] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.253994] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.254076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.254391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.254435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.254479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.254563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.254606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.254649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.254699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.254742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.254785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.254829] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.254878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.254925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.254970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.255034] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.255077] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.255132] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.255195] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.255239] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.255284] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:05 BXT-2 kernel: [ 652.255323] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:05 BXT-2 kernel: [ 652.255960] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.257651] [drm:i915_reset_and_wakeup [i915]] resetting chip >May 24 03:33:05 BXT-2 kernel: [ 652.257755] drm/i915: Resetting chip after gpu hang >May 24 03:33:05 BXT-2 kernel: [ 652.262365] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:33:05 BXT-2 kernel: [ 652.262438] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:33:05 BXT-2 kernel: [ 652.262647] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:33:05 BXT-2 kernel: [ 652.262776] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:33:05 BXT-2 kernel: [ 652.262901] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:33:05 BXT-2 kernel: [ 652.264553] [drm:drm_mode_addfb2] [FB:76] >May 24 03:33:05 BXT-2 kernel: [ 652.280073] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.280136] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.280269] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:05 BXT-2 kernel: [ 652.280313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:05 BXT-2 kernel: [ 652.280357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:05 BXT-2 kernel: [ 652.280401] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:05 BXT-2 kernel: [ 652.280444] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:05 BXT-2 kernel: [ 652.280531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.280580] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:33:05 BXT-2 kernel: [ 652.280625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.280671] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:05 BXT-2 kernel: [ 652.280717] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.280761] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:05 BXT-2 kernel: [ 652.280768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.280810] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:05 BXT-2 kernel: [ 652.280819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.280864] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.280907] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:05 BXT-2 kernel: [ 652.280951] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:05 BXT-2 kernel: [ 652.280994] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:05 BXT-2 kernel: [ 652.281036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.281081] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:05 BXT-2 kernel: [ 652.281123] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:05 BXT-2 kernel: [ 652.281166] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.281209] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.281251] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.281313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.281365] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.281409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.282037] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.282076] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.282370] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:05 BXT-2 kernel: [ 652.282426] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.282466] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.282569] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.282831] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.283151] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.283195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.283239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.283282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.283325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.283368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.283411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.283454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.283526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.283574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.283624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.283671] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.283747] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.283791] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.285286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.285332] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.285376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:05 BXT-2 kernel: [ 652.286237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.286283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.287060] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:05 BXT-2 kernel: [ 652.287106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:05 BXT-2 kernel: [ 652.288170] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:05 BXT-2 kernel: [ 652.289572] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:05 BXT-2 kernel: [ 652.290651] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.307564] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.307623] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.307795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.391054] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.391194] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.408893] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.409041] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.409149] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.409490] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.409604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.409650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.409696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.409739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.409783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.409834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.409878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.409922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.409966] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.410015] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.410063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.410108] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.410182] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.410226] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.410282] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.410346] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.410390] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.410434] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:05 BXT-2 kernel: [ 652.410473] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:05 BXT-2 kernel: [ 652.411062] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.412652] [drm:drm_mode_addfb2] [FB:76] >May 24 03:33:05 BXT-2 kernel: [ 652.430034] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.430095] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.430219] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:05 BXT-2 kernel: [ 652.430264] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:05 BXT-2 kernel: [ 652.430309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:05 BXT-2 kernel: [ 652.430353] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:05 BXT-2 kernel: [ 652.430396] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:05 BXT-2 kernel: [ 652.430440] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.430483] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:33:05 BXT-2 kernel: [ 652.430578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.430621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:05 BXT-2 kernel: [ 652.430664] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.430711] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:05 BXT-2 kernel: [ 652.430718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.430760] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:05 BXT-2 kernel: [ 652.430766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.430811] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.430854] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:05 BXT-2 kernel: [ 652.430898] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:05 BXT-2 kernel: [ 652.430941] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:05 BXT-2 kernel: [ 652.430984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.431029] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:05 BXT-2 kernel: [ 652.431073] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:05 BXT-2 kernel: [ 652.431116] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.431160] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.431203] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.431268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.431322] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.431366] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.431986] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.432025] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.432315] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:05 BXT-2 kernel: [ 652.432371] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.432414] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.432473] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.432774] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.433094] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.433138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.433181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.433224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.433267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.433311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.433354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.433396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.433439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.433482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.433583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.433630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.433706] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.433749] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.435796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.435841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.435886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:05 BXT-2 kernel: [ 652.436992] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:05 BXT-2 kernel: [ 652.437038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:05 BXT-2 kernel: [ 652.438094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:05 BXT-2 kernel: [ 652.440195] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:05 BXT-2 kernel: [ 652.441236] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.458118] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.458176] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.458347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.541728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.541863] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:33:05 BXT-2 kernel: [ 652.559789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 03:33:05 BXT-2 kernel: [ 652.559903] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.559985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.560314] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.560359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.560402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.560445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.560539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.560584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.560638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.560682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.560725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.560770] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.560820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.560868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.560914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.560989] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.561035] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.561091] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.561158] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:33:05 BXT-2 kernel: [ 652.561206] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.561251] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:05 BXT-2 kernel: [ 652.561290] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:05 BXT-2 kernel: [ 652.561883] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.594405] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:05 BXT-2 kernel: [ 652.594448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:05 BXT-2 kernel: [ 652.594542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:05 BXT-2 kernel: [ 652.594584] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:05 BXT-2 kernel: [ 652.594626] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:05 BXT-2 kernel: [ 652.594669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.594712] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:05 BXT-2 kernel: [ 652.594754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.594796] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:05 BXT-2 kernel: [ 652.594837] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.594877] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:05 BXT-2 kernel: [ 652.594885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.594926] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:05 BXT-2 kernel: [ 652.594931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.594973] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:05 BXT-2 kernel: [ 652.595014] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:05 BXT-2 kernel: [ 652.595056] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:05 BXT-2 kernel: [ 652.595098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:05 BXT-2 kernel: [ 652.595139] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:05 BXT-2 kernel: [ 652.595183] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:05 BXT-2 kernel: [ 652.595224] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:05 BXT-2 kernel: [ 652.595266] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.595307] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.595349] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.595390] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:05 BXT-2 kernel: [ 652.595436] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.595516] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.595559] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:05 BXT-2 kernel: [ 652.595690] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:05 BXT-2 kernel: [ 652.595726] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:05 BXT-2 kernel: [ 652.596014] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:05 BXT-2 kernel: [ 652.596069] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.596108] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:05 BXT-2 kernel: [ 652.596162] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:05 BXT-2 kernel: [ 652.596459] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.596974] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:05 BXT-2 kernel: [ 652.597019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:05 BXT-2 kernel: [ 652.597062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.597104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.597145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.597187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:05 BXT-2 kernel: [ 652.597228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:05 BXT-2 kernel: [ 652.597270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:05 BXT-2 kernel: [ 652.597311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:05 BXT-2 kernel: [ 652.597353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:05 BXT-2 kernel: [ 652.597401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:05 BXT-2 kernel: [ 652.597445] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.597561] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:05 BXT-2 kernel: [ 652.597603] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.602264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.602307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.602351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:05 BXT-2 kernel: [ 652.603203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.603245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:05 BXT-2 kernel: [ 652.604178] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:05 BXT-2 kernel: [ 652.604222] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:05 BXT-2 kernel: [ 652.605606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:05 BXT-2 kernel: [ 652.607578] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:05 BXT-2 kernel: [ 652.608833] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:05 BXT-2 kernel: [ 652.625751] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:05 BXT-2 kernel: [ 652.625806] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:05 BXT-2 kernel: [ 652.625983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:05 BXT-2 kernel: [ 652.626345] Console: switching to colour frame buffer device 240x67 >May 24 03:33:05 BXT-2 kernel: [ 652.872413] Console: switching to colour dummy device 80x25 >May 24 03:33:06 BXT-2 kernel: [ 652.942589] Console: switching to colour frame buffer device 240x67 >May 24 03:33:06 BXT-2 kernel: [ 653.233326] Console: switching to colour dummy device 80x25 >May 24 03:33:06 BXT-2 kernel: [ 653.242613] Console: switching to colour frame buffer device 240x67 >May 24 03:33:06 BXT-2 kernel: [ 653.522542] Console: switching to colour dummy device 80x25 >May 24 03:33:06 BXT-2 kernel: [ 653.542659] [drm:drm_mode_addfb2] [FB:78] >May 24 03:33:06 BXT-2 kernel: [ 653.644343] ahci 0000:00:12.0: port does not support device sleep >May 24 03:33:07 BXT-2 kernel: [ 654.260373] r8169 0000:03:00.0 enp3s0: link up >May 24 03:33:07 BXT-2 NetworkManager[807]: <info> [1495614787.3758] device (enp3s0): link connected >May 24 03:33:07 BXT-2 kernel: [ 654.642449] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:07 BXT-2 kernel: [ 654.642663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.642810] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:07 BXT-2 kernel: [ 654.660885] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:07 BXT-2 kernel: [ 654.660998] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:07 BXT-2 kernel: [ 654.661086] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.661411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.661455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:07 BXT-2 kernel: [ 654.661551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:07 BXT-2 kernel: [ 654.661597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:07 BXT-2 kernel: [ 654.661647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:07 BXT-2 kernel: [ 654.661693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:07 BXT-2 kernel: [ 654.661743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:07 BXT-2 kernel: [ 654.661788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:07 BXT-2 kernel: [ 654.661835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:07 BXT-2 kernel: [ 654.661878] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:07 BXT-2 kernel: [ 654.661926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:07 BXT-2 kernel: [ 654.661972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:07 BXT-2 kernel: [ 654.662018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:07 BXT-2 kernel: [ 654.662080] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:07 BXT-2 kernel: [ 654.662125] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:07 BXT-2 kernel: [ 654.662180] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:07 BXT-2 kernel: [ 654.662243] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:07 BXT-2 kernel: [ 654.662297] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:07 BXT-2 kernel: [ 654.662342] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:07 BXT-2 kernel: [ 654.662381] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:07 BXT-2 kernel: [ 654.662985] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:07 BXT-2 kernel: [ 654.663930] [drm:intel_runtime_suspend [i915]] Suspending device >May 24 03:33:07 BXT-2 kernel: [ 654.664321] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.665236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.665367] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.665603] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.665647] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:07 BXT-2 kernel: [ 654.665696] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:07 BXT-2 kernel: [ 654.665739] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:07 BXT-2 kernel: [ 654.665815] [drm:intel_runtime_suspend [i915]] Device suspended >May 24 03:33:07 BXT-2 kernel: [ 654.666411] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:33:07 BXT-2 kernel: [ 654.666849] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:07 BXT-2 kernel: [ 654.767124] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:07 BXT-2 kernel: [ 654.767174] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:07 BXT-2 kernel: [ 654.767306] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:07 BXT-2 kernel: [ 654.767350] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:07 BXT-2 kernel: [ 654.767396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:07 BXT-2 kernel: [ 654.767440] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:07 BXT-2 kernel: [ 654.767482] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:07 BXT-2 kernel: [ 654.767671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:07 BXT-2 kernel: [ 654.767717] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:07 BXT-2 kernel: [ 654.767760] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:07 BXT-2 kernel: [ 654.767804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:07 BXT-2 kernel: [ 654.767847] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:07 BXT-2 kernel: [ 654.767889] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:07 BXT-2 kernel: [ 654.767899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:07 BXT-2 kernel: [ 654.767942] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:07 BXT-2 kernel: [ 654.767948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:07 BXT-2 kernel: [ 654.767992] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:07 BXT-2 kernel: [ 654.768035] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:07 BXT-2 kernel: [ 654.768079] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:07 BXT-2 kernel: [ 654.768122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:07 BXT-2 kernel: [ 654.768165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:07 BXT-2 kernel: [ 654.768210] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:07 BXT-2 kernel: [ 654.768253] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:07 BXT-2 kernel: [ 654.768296] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:07 BXT-2 kernel: [ 654.768340] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:07 BXT-2 kernel: [ 654.768383] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:07 BXT-2 kernel: [ 654.768426] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:07 BXT-2 kernel: [ 654.768545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.768602] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:07 BXT-2 kernel: [ 654.768648] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:07 BXT-2 kernel: [ 654.780779] [drm:intel_runtime_resume [i915]] Resuming device >May 24 03:33:07 BXT-2 kernel: [ 654.780911] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:07 BXT-2 kernel: [ 654.780953] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.781025] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.781193] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.781376] [drm:skl_set_power_well [i915]] Enabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.781431] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.781473] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:07 BXT-2 kernel: [ 654.781929] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.785711] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:07 BXT-2 kernel: [ 654.785755] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:07 BXT-2 kernel: [ 654.788825] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:33:07 BXT-2 kernel: [ 654.790330] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:07 BXT-2 kernel: [ 654.790929] [drm:intel_runtime_resume [i915]] Device resumed >May 24 03:33:07 BXT-2 kernel: [ 654.792455] [drm:intel_runtime_suspend [i915]] Suspending device >May 24 03:33:07 BXT-2 kernel: [ 654.792912] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.793744] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.793784] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.793839] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.793887] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:07 BXT-2 kernel: [ 654.793947] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:07 BXT-2 kernel: [ 654.793991] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:07 BXT-2 kernel: [ 654.794067] [drm:intel_runtime_suspend [i915]] Device suspended >May 24 03:33:07 BXT-2 kernel: [ 654.817675] [drm:intel_runtime_resume [i915]] Resuming device >May 24 03:33:07 BXT-2 kernel: [ 654.817732] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:07 BXT-2 kernel: [ 654.817774] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.817846] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.817923] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.817976] [drm:skl_set_power_well [i915]] Enabling power well 1 >May 24 03:33:07 BXT-2 kernel: [ 654.818032] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.818074] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:07 BXT-2 kernel: [ 654.818435] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.822811] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:07 BXT-2 kernel: [ 654.822856] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:07 BXT-2 kernel: [ 654.826586] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:33:07 BXT-2 kernel: [ 654.827196] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:07 BXT-2 kernel: [ 654.828052] [drm:intel_runtime_resume [i915]] Device resumed >May 24 03:33:07 BXT-2 kernel: [ 654.829288] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:07 BXT-2 kernel: [ 654.829326] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:07 BXT-2 kernel: [ 654.830536] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:07 BXT-2 kernel: [ 654.830866] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:07 BXT-2 kernel: [ 654.830909] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:07 BXT-2 kernel: [ 654.831332] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:07 BXT-2 kernel: [ 654.831893] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.832235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.832280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:07 BXT-2 kernel: [ 654.832324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:07 BXT-2 kernel: [ 654.832366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:07 BXT-2 kernel: [ 654.832409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:07 BXT-2 kernel: [ 654.832452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:07 BXT-2 kernel: [ 654.832542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:07 BXT-2 kernel: [ 654.832586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:07 BXT-2 kernel: [ 654.832631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:07 BXT-2 kernel: [ 654.832674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:07 BXT-2 kernel: [ 654.832724] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:07 BXT-2 kernel: [ 654.832770] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:07 BXT-2 kernel: [ 654.832849] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:07 BXT-2 kernel: [ 654.832893] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:07 BXT-2 kernel: [ 654.837253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:07 BXT-2 kernel: [ 654.837299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:07 BXT-2 kernel: [ 654.837345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:07 BXT-2 kernel: [ 654.838137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:07 BXT-2 kernel: [ 654.838180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:07 BXT-2 kernel: [ 654.838937] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:07 BXT-2 kernel: [ 654.838982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:07 BXT-2 kernel: [ 654.840060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:07 BXT-2 kernel: [ 654.841564] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:07 BXT-2 kernel: [ 654.843431] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:07 BXT-2 kernel: [ 654.860579] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:07 BXT-2 kernel: [ 654.860803] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:07 BXT-2 kernel: [ 654.860997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:07 BXT-2 kernel: [ 654.861287] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:07 BXT-2 kernel: [ 654.861312] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:33:07 BXT-2 kernel: [ 654.861357] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:07 BXT-2 kernel: [ 654.862164] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:07 BXT-2 kernel: [ 654.863275] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:07 BXT-2 kernel: [ 654.863323] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:07 BXT-2 kernel: [ 654.863366] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:07 BXT-2 kernel: [ 654.863409] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:07 BXT-2 kernel: [ 654.864043] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:07 BXT-2 kernel: [ 654.864089] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:07 BXT-2 kernel: [ 654.869205] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:07 BXT-2 kernel: [ 654.869286] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:07 BXT-2 kernel: [ 654.869302] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:33:07 BXT-2 kernel: [ 654.869387] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:07 BXT-2 kernel: [ 654.870149] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:07 BXT-2 kernel: [ 654.871156] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:07 BXT-2 kernel: [ 654.871202] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:07 BXT-2 kernel: [ 654.871245] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:07 BXT-2 kernel: [ 654.871287] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:07 BXT-2 kernel: [ 654.871925] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:07 BXT-2 kernel: [ 654.871970] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:07 BXT-2 kernel: [ 654.876958] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:07 BXT-2 kernel: [ 654.877157] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:07 BXT-2 kernel: [ 654.878820] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:07 BXT-2 kernel: [ 654.883408] ahci 0000:00:12.0: port does not support device sleep >May 24 03:33:08 BXT-2 kernel: [ 654.896830] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:08 BXT-2 kernel: [ 654.897021] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:08 BXT-2 kernel: [ 654.897182] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:08 BXT-2 kernel: [ 654.897547] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:08 BXT-2 kernel: [ 654.897592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:08 BXT-2 kernel: [ 654.897642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:08 BXT-2 kernel: [ 654.897687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:08 BXT-2 kernel: [ 654.897733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:08 BXT-2 kernel: [ 654.897776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:08 BXT-2 kernel: [ 654.897826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:08 BXT-2 kernel: [ 654.897870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:08 BXT-2 kernel: [ 654.897913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:08 BXT-2 kernel: [ 654.897956] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:08 BXT-2 kernel: [ 654.898004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:08 BXT-2 kernel: [ 654.898050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:08 BXT-2 kernel: [ 654.898095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:08 BXT-2 kernel: [ 654.898269] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:08 BXT-2 kernel: [ 654.898448] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:08 BXT-2 kernel: [ 654.898680] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:08 BXT-2 kernel: [ 654.898778] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:08 BXT-2 kernel: [ 654.898847] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:08 BXT-2 kernel: [ 654.898894] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:08 BXT-2 kernel: [ 654.898933] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:08 BXT-2 kernel: [ 654.899508] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:08 BXT-2 kernel: [ 654.921834] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:08 BXT-2 kernel: [ 654.921881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:08 BXT-2 kernel: [ 654.921927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:08 BXT-2 kernel: [ 654.921971] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:08 BXT-2 kernel: [ 654.922013] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:08 BXT-2 kernel: [ 654.922057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:08 BXT-2 kernel: [ 654.922100] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:08 BXT-2 kernel: [ 654.922143] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:08 BXT-2 kernel: [ 654.922186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:08 BXT-2 kernel: [ 654.922228] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:08 BXT-2 kernel: [ 654.922270] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:08 BXT-2 kernel: [ 654.922279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:08 BXT-2 kernel: [ 654.922321] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:08 BXT-2 kernel: [ 654.922327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:08 BXT-2 kernel: [ 654.922370] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:08 BXT-2 kernel: [ 654.922413] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:08 BXT-2 kernel: [ 654.922456] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:08 BXT-2 kernel: [ 654.922553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:08 BXT-2 kernel: [ 654.922596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:08 BXT-2 kernel: [ 654.922641] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:08 BXT-2 kernel: [ 654.922683] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:08 BXT-2 kernel: [ 654.922726] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:08 BXT-2 kernel: [ 654.922769] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:08 BXT-2 kernel: [ 654.922812] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:08 BXT-2 kernel: [ 654.922854] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:08 BXT-2 kernel: [ 654.922902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:08 BXT-2 kernel: [ 654.922956] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:08 BXT-2 kernel: [ 654.922999] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:08 BXT-2 kernel: [ 654.923136] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:08 BXT-2 kernel: [ 654.923175] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:08 BXT-2 kernel: [ 654.923470] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:08 BXT-2 kernel: [ 654.924217] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:08 BXT-2 kernel: [ 654.924261] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:08 BXT-2 kernel: [ 654.924324] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:08 BXT-2 kernel: [ 654.926614] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:08 BXT-2 kernel: [ 654.926954] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:08 BXT-2 kernel: [ 654.926998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:08 BXT-2 kernel: [ 654.927042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:08 BXT-2 kernel: [ 654.927085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:08 BXT-2 kernel: [ 654.927128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:08 BXT-2 kernel: [ 654.927171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:08 BXT-2 kernel: [ 654.927214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:08 BXT-2 kernel: [ 654.927256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:08 BXT-2 kernel: [ 654.927299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:08 BXT-2 kernel: [ 654.927342] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:08 BXT-2 kernel: [ 654.927391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:08 BXT-2 kernel: [ 654.927436] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:08 BXT-2 kernel: [ 654.928370] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:08 BXT-2 kernel: [ 654.928417] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:08 BXT-2 kernel: [ 654.930388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:08 BXT-2 kernel: [ 654.930433] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:08 BXT-2 kernel: [ 654.930479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:08 BXT-2 kernel: [ 654.931482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:08 BXT-2 kernel: [ 654.931655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:08 BXT-2 kernel: [ 654.932408] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:08 BXT-2 kernel: [ 654.932452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:08 BXT-2 kernel: [ 654.933710] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:08 BXT-2 kernel: [ 654.935555] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:08 BXT-2 kernel: [ 654.937447] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:08 BXT-2 kernel: [ 654.954372] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:08 BXT-2 kernel: [ 654.954432] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:08 BXT-2 kernel: [ 654.954716] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:08 BXT-2 kernel: [ 654.972143] Console: switching to colour frame buffer device 240x67 >May 24 03:33:08 BXT-2 kernel: [ 655.250776] Console: switching to colour dummy device 80x25 >May 24 03:33:08 BXT-2 kernel: [ 655.272517] [drm:drm_mode_addfb2] [FB:78] >May 24 03:33:08 BXT-2 kernel: [ 655.371540] ahci 0000:00:12.0: port does not support device sleep >May 24 03:33:09 BXT-2 kernel: [ 656.372358] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:09 BXT-2 kernel: [ 656.372650] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.372802] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:09 BXT-2 kernel: [ 656.388846] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:09 BXT-2 kernel: [ 656.388967] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.389088] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.389578] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.389627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:09 BXT-2 kernel: [ 656.389671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.389717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.389760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.389803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:09 BXT-2 kernel: [ 656.389855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.389898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.389941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.389985] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.390034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:09 BXT-2 kernel: [ 656.390082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:09 BXT-2 kernel: [ 656.390130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.390196] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.390242] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.390312] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.390380] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:09 BXT-2 kernel: [ 656.390435] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.390517] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.390558] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.391126] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.391277] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:33:09 BXT-2 kernel: [ 656.391407] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:33:09 BXT-2 kernel: [ 656.391647] [drm:intel_runtime_suspend [i915]] Suspending device >May 24 03:33:09 BXT-2 kernel: [ 656.392046] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.393051] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.393094] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.393150] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.393198] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:09 BXT-2 kernel: [ 656.393258] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:09 BXT-2 kernel: [ 656.393301] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:09 BXT-2 kernel: [ 656.393381] [drm:intel_runtime_suspend [i915]] Device suspended >May 24 03:33:09 BXT-2 kernel: [ 656.496751] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:09 BXT-2 kernel: [ 656.496811] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.496940] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:09 BXT-2 kernel: [ 656.496985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:09 BXT-2 kernel: [ 656.497031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:09 BXT-2 kernel: [ 656.497075] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:09 BXT-2 kernel: [ 656.497117] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:09 BXT-2 kernel: [ 656.497161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.497205] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:09 BXT-2 kernel: [ 656.497249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.497292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:09 BXT-2 kernel: [ 656.497334] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.497376] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:09 BXT-2 kernel: [ 656.497384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:09 BXT-2 kernel: [ 656.497426] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:09 BXT-2 kernel: [ 656.497432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:09 BXT-2 kernel: [ 656.497475] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:09 BXT-2 kernel: [ 656.498346] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:09 BXT-2 kernel: [ 656.498391] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:09 BXT-2 kernel: [ 656.498433] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:09 BXT-2 kernel: [ 656.498476] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.500601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:09 BXT-2 kernel: [ 656.500645] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:09 BXT-2 kernel: [ 656.500689] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.500732] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.500775] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.500817] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.500887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.500941] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.500984] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:09 BXT-2 kernel: [ 656.512656] [drm:intel_runtime_resume [i915]] Resuming device >May 24 03:33:09 BXT-2 kernel: [ 656.512704] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:09 BXT-2 kernel: [ 656.512747] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.512820] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.512895] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.512949] [drm:skl_set_power_well [i915]] Enabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.513005] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.513047] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:09 BXT-2 kernel: [ 656.513407] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.517058] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.517103] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.520748] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:33:09 BXT-2 kernel: [ 656.521326] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:09 BXT-2 kernel: [ 656.521387] [drm:intel_runtime_resume [i915]] Device resumed >May 24 03:33:09 BXT-2 kernel: [ 656.522192] [drm:intel_runtime_suspend [i915]] Suspending device >May 24 03:33:09 BXT-2 kernel: [ 656.523388] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.523761] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.523801] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.523858] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.523907] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:09 BXT-2 kernel: [ 656.523968] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:09 BXT-2 kernel: [ 656.524012] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:09 BXT-2 kernel: [ 656.524089] [drm:intel_runtime_suspend [i915]] Device suspended >May 24 03:33:09 BXT-2 kernel: [ 656.549642] [drm:intel_runtime_resume [i915]] Resuming device >May 24 03:33:09 BXT-2 kernel: [ 656.549691] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:09 BXT-2 kernel: [ 656.549734] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.549805] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.549882] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.549934] [drm:skl_set_power_well [i915]] Enabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.549989] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.550031] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:09 BXT-2 kernel: [ 656.550382] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.554213] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.554257] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.557941] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:33:09 BXT-2 kernel: [ 656.558456] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:09 BXT-2 kernel: [ 656.558521] [drm:intel_runtime_resume [i915]] Device resumed >May 24 03:33:09 BXT-2 kernel: [ 656.558568] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.558606] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.559051] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.559115] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.559158] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.559220] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.559595] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.559920] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.559964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:09 BXT-2 kernel: [ 656.560008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.560050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.560093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.560137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:09 BXT-2 kernel: [ 656.560180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.560222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.560265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.560308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:09 BXT-2 kernel: [ 656.560356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:09 BXT-2 kernel: [ 656.560401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.560478] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:09 BXT-2 kernel: [ 656.560553] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.562018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.562062] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.562108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:09 BXT-2 kernel: [ 656.562892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.562936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.563682] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:09 BXT-2 kernel: [ 656.563726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:09 BXT-2 kernel: [ 656.564784] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:09 BXT-2 kernel: [ 656.566577] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:09 BXT-2 kernel: [ 656.568416] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:09 BXT-2 kernel: [ 656.587025] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.587084] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:09 BXT-2 kernel: [ 656.587287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.591887] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:09 BXT-2 kernel: [ 656.591911] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:33:09 BXT-2 kernel: [ 656.591956] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.593555] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:09 BXT-2 kernel: [ 656.594573] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:09 BXT-2 kernel: [ 656.594621] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:09 BXT-2 kernel: [ 656.594664] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:09 BXT-2 kernel: [ 656.594706] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:09 BXT-2 kernel: [ 656.595358] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:09 BXT-2 kernel: [ 656.595417] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:09 BXT-2 kernel: [ 656.602161] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:09 BXT-2 kernel: [ 656.602242] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:09 BXT-2 kernel: [ 656.602260] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:33:09 BXT-2 kernel: [ 656.602305] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.603145] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:09 BXT-2 kernel: [ 656.604345] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:09 BXT-2 kernel: [ 656.604394] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:09 BXT-2 kernel: [ 656.604437] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:09 BXT-2 kernel: [ 656.604479] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:09 BXT-2 kernel: [ 656.605167] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:09 BXT-2 kernel: [ 656.605213] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:09 BXT-2 kernel: [ 656.607296] ahci 0000:00:12.0: port does not support device sleep >May 24 03:33:09 BXT-2 kernel: [ 656.610518] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:09 BXT-2 kernel: [ 656.610686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.610822] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:09 BXT-2 kernel: [ 656.618835] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:09 BXT-2 kernel: [ 656.618955] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.619078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.619398] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.619442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:09 BXT-2 kernel: [ 656.619485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.619573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.619621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.619668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:09 BXT-2 kernel: [ 656.619718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.619762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.619806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.619852] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.619901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:09 BXT-2 kernel: [ 656.619948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:09 BXT-2 kernel: [ 656.619996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.620061] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.620107] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.620176] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.620242] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:09 BXT-2 kernel: [ 656.620296] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.620343] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.620382] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.621575] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.621758] [drm:intel_runtime_suspend [i915]] Suspending device >May 24 03:33:09 BXT-2 kernel: [ 656.622246] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.625103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.625146] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.625202] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.625250] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:09 BXT-2 kernel: [ 656.625310] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:09 BXT-2 kernel: [ 656.625353] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:09 BXT-2 kernel: [ 656.626004] [drm:intel_runtime_suspend [i915]] Device suspended >May 24 03:33:09 BXT-2 kernel: [ 656.649834] [drm:intel_runtime_resume [i915]] Resuming device >May 24 03:33:09 BXT-2 kernel: [ 656.649972] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:09 BXT-2 kernel: [ 656.650015] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.650087] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.650267] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.650457] [drm:skl_set_power_well [i915]] Enabling power well 1 >May 24 03:33:09 BXT-2 kernel: [ 656.650566] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.650611] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:09 BXT-2 kernel: [ 656.651024] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.654498] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.654573] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.658552] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:33:09 BXT-2 kernel: [ 656.659167] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:09 BXT-2 kernel: [ 656.661063] [drm:intel_runtime_resume [i915]] Device resumed >May 24 03:33:09 BXT-2 kernel: [ 656.663669] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:09 BXT-2 kernel: [ 656.663802] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.667543] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.668090] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.668167] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.668210] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.668449] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.672291] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.672340] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.672478] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.672762] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.672811] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.672851] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.673415] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.673428] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:33:09 BXT-2 kernel: [ 656.673481] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.673892] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.673929] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.674231] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.674293] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.674336] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.674400] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.683549] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:09 BXT-2 kernel: [ 656.684486] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:09 BXT-2 kernel: [ 656.684867] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:09 BXT-2 kernel: [ 656.684911] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:09 BXT-2 kernel: [ 656.684953] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:09 BXT-2 kernel: [ 656.685486] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:09 BXT-2 kernel: [ 656.685795] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:09 BXT-2 kernel: [ 656.690957] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.691005] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.691074] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.691118] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.691165] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:09 BXT-2 kernel: [ 656.691205] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:09 BXT-2 kernel: [ 656.691819] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.691833] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:09 BXT-2 kernel: [ 656.692064] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:09 BXT-2 kernel: [ 656.692109] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:09 BXT-2 kernel: [ 656.692155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:09 BXT-2 kernel: [ 656.692199] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:09 BXT-2 kernel: [ 656.692241] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:09 BXT-2 kernel: [ 656.692286] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.692330] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:09 BXT-2 kernel: [ 656.692373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.692417] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:09 BXT-2 kernel: [ 656.692460] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.692538] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:09 BXT-2 kernel: [ 656.692546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:09 BXT-2 kernel: [ 656.692588] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:09 BXT-2 kernel: [ 656.692595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:09 BXT-2 kernel: [ 656.692638] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:09 BXT-2 kernel: [ 656.692681] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:09 BXT-2 kernel: [ 656.692725] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:09 BXT-2 kernel: [ 656.692767] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:09 BXT-2 kernel: [ 656.692810] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:09 BXT-2 kernel: [ 656.692856] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:09 BXT-2 kernel: [ 656.692898] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:09 BXT-2 kernel: [ 656.692941] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.692985] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.693027] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.693070] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:09 BXT-2 kernel: [ 656.693116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.693169] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.693213] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:09 BXT-2 kernel: [ 656.693339] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:09 BXT-2 kernel: [ 656.693377] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:09 BXT-2 kernel: [ 656.693687] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:09 BXT-2 kernel: [ 656.693751] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.693794] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:09 BXT-2 kernel: [ 656.693857] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:09 BXT-2 kernel: [ 656.694318] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.694830] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:09 BXT-2 kernel: [ 656.694876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:09 BXT-2 kernel: [ 656.694919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.694962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.695005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.695048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:09 BXT-2 kernel: [ 656.695091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:09 BXT-2 kernel: [ 656.695133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:09 BXT-2 kernel: [ 656.695176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:09 BXT-2 kernel: [ 656.695219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:09 BXT-2 kernel: [ 656.695268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:09 BXT-2 kernel: [ 656.695313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.695392] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:09 BXT-2 kernel: [ 656.695435] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.699852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.699897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.699943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:09 BXT-2 kernel: [ 656.700743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.700786] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:09 BXT-2 kernel: [ 656.702044] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:09 BXT-2 kernel: [ 656.702091] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:09 BXT-2 kernel: [ 656.703180] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:09 BXT-2 kernel: [ 656.704557] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:09 BXT-2 kernel: [ 656.706395] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:09 BXT-2 kernel: [ 656.723323] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:09 BXT-2 kernel: [ 656.723382] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:09 BXT-2 kernel: [ 656.723699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:09 BXT-2 kernel: [ 656.740149] Console: switching to colour frame buffer device 240x67 >May 24 03:33:10 BXT-2 kernel: [ 657.021334] Console: switching to colour dummy device 80x25 >May 24 03:33:10 BXT-2 kernel: [ 657.090130] Console: switching to colour frame buffer device 240x67 >May 24 03:33:10 BXT-2 kernel: [ 657.368408] Console: switching to colour dummy device 80x25 >May 24 03:33:11 BXT-2 kernel: [ 658.540165] Console: switching to colour frame buffer device 240x67 >May 24 03:33:11 BXT-2 kernel: [ 658.806094] Console: switching to colour dummy device 80x25 >May 24 03:33:12 BXT-2 kernel: [ 659.790164] Console: switching to colour frame buffer device 240x67 >May 24 03:33:13 BXT-2 kernel: [ 660.060993] Console: switching to colour dummy device 80x25 >May 24 03:33:14 BXT-2 kernel: [ 661.190202] Console: switching to colour frame buffer device 240x67 >May 24 03:33:14 BXT-2 kernel: [ 661.499021] Console: switching to colour dummy device 80x25 >May 24 03:33:15 BXT-2 kernel: [ 662.640195] Console: switching to colour frame buffer device 240x67 >May 24 03:33:16 BXT-2 kernel: [ 662.952155] Console: switching to colour dummy device 80x25 >May 24 03:33:16 BXT-2 kernel: [ 663.073596] Console: switching to colour frame buffer device 240x67 >May 24 03:33:16 BXT-2 kernel: [ 663.402527] Console: switching to colour dummy device 80x25 >May 24 03:33:16 BXT-2 kernel: [ 663.456822] Console: switching to colour frame buffer device 240x67 >May 24 03:33:16 BXT-2 kernel: [ 663.750049] Console: switching to colour dummy device 80x25 >May 24 03:33:16 BXT-2 kernel: [ 663.840234] Console: switching to colour frame buffer device 240x67 >May 24 03:33:17 BXT-2 kernel: [ 664.139606] Console: switching to colour dummy device 80x25 >May 24 03:33:17 BXT-2 kernel: [ 664.240224] Console: switching to colour frame buffer device 240x67 >May 24 03:33:17 BXT-2 kernel: [ 664.536853] Console: switching to colour dummy device 80x25 >May 24 03:33:17 BXT-2 kernel: [ 664.606872] Console: switching to colour frame buffer device 240x67 >May 24 03:33:18 BXT-2 kernel: [ 664.914049] Console: switching to colour dummy device 80x25 >May 24 03:33:18 BXT-2 kernel: [ 664.973569] Console: switching to colour frame buffer device 240x67 >May 24 03:33:18 BXT-2 kernel: [ 665.254172] Console: switching to colour dummy device 80x25 >May 24 03:33:18 BXT-2 kernel: [ 665.292622] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:18 BXT-2 kernel: [ 665.313636] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:18 BXT-2 kernel: [ 665.356857] Console: switching to colour frame buffer device 240x67 >May 24 03:33:18 BXT-2 kernel: [ 665.662342] Console: switching to colour dummy device 80x25 >May 24 03:33:18 BXT-2 kernel: [ 665.684438] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:18 BXT-2 kernel: [ 665.708440] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:18 BXT-2 kernel: [ 665.756875] Console: switching to colour frame buffer device 240x67 >May 24 03:33:19 BXT-2 kernel: [ 666.022952] Console: switching to colour dummy device 80x25 >May 24 03:33:19 BXT-2 kernel: [ 666.056108] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:19 BXT-2 kernel: [ 666.074620] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:19 BXT-2 kernel: [ 666.123595] Console: switching to colour frame buffer device 240x67 >May 24 03:33:19 BXT-2 kernel: [ 666.410081] Console: switching to colour dummy device 80x25 >May 24 03:33:19 BXT-2 kernel: [ 666.459614] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:19 BXT-2 kernel: [ 666.462677] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:19 BXT-2 kernel: [ 666.506909] Console: switching to colour frame buffer device 240x67 >May 24 03:33:19 BXT-2 kernel: [ 666.760975] Console: switching to colour dummy device 80x25 >May 24 03:33:19 BXT-2 kernel: [ 666.801647] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:19 BXT-2 kernel: [ 666.804635] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:19 BXT-2 kernel: [ 666.856895] Console: switching to colour frame buffer device 240x67 >May 24 03:33:20 BXT-2 kernel: [ 667.115167] Console: switching to colour dummy device 80x25 >May 24 03:33:20 BXT-2 kernel: [ 667.161777] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:20 BXT-2 kernel: [ 667.163734] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:20 BXT-2 kernel: [ 667.206948] Console: switching to colour frame buffer device 240x67 >May 24 03:33:20 BXT-2 kernel: [ 667.455650] Console: switching to colour dummy device 80x25 >May 24 03:33:20 BXT-2 kernel: [ 667.500352] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:20 BXT-2 kernel: [ 667.530453] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:20 BXT-2 kernel: [ 667.573559] Console: switching to colour frame buffer device 240x67 >May 24 03:33:20 BXT-2 kernel: [ 667.811005] Console: switching to colour dummy device 80x25 >May 24 03:33:20 BXT-2 kernel: [ 667.851205] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:20 BXT-2 kernel: [ 667.870549] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:21 BXT-2 kernel: [ 667.906923] Console: switching to colour frame buffer device 240x67 >May 24 03:33:21 BXT-2 kernel: [ 668.141973] Console: switching to colour dummy device 80x25 >May 24 03:33:21 BXT-2 kernel: [ 668.196625] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:22 BXT-2 kernel: [ 669.200961] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:22 BXT-2 kernel: [ 669.256925] Console: switching to colour frame buffer device 240x67 >May 24 03:33:22 BXT-2 kernel: [ 669.490365] Console: switching to colour dummy device 80x25 >May 24 03:33:22 BXT-2 kernel: [ 669.521538] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728 >May 24 03:33:22 BXT-2 kernel: [ 669.526376] [drm:drm_mode_addfb2] [FB:76] >May 24 03:33:22 BXT-2 kernel: [ 669.526439] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728 >May 24 03:33:22 BXT-2 kernel: [ 669.531364] [drm:drm_mode_addfb2] [FB:80] >May 24 03:33:22 BXT-2 kernel: [ 669.531534] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:33:22 BXT-2 kernel: [ 669.531596] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:22 BXT-2 kernel: [ 669.531617] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:33:22 BXT-2 kernel: [ 669.531628] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:33:22 BXT-2 kernel: [ 669.531673] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:22 BXT-2 kernel: [ 669.532231] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:22 BXT-2 kernel: [ 669.533139] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:22 BXT-2 kernel: [ 669.533185] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:22 BXT-2 kernel: [ 669.533228] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:22 BXT-2 kernel: [ 669.533270] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:22 BXT-2 kernel: [ 669.533826] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:22 BXT-2 kernel: [ 669.533870] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:22 BXT-2 kernel: [ 669.538784] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:33:22 BXT-2 kernel: [ 669.538851] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:33:22 BXT-2 kernel: [ 669.538858] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538863] [drm:drm_mode_debug_printmodeline] Modeline 67:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538869] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538874] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538879] [drm:drm_mode_debug_printmodeline] Modeline 65:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538884] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538889] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:33:22 BXT-2 kernel: [ 669.538894] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538899] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.538904] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:33:22 BXT-2 kernel: [ 669.538909] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:33:22 BXT-2 kernel: [ 669.538914] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:33:22 BXT-2 kernel: [ 669.538950] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:33:22 BXT-2 kernel: [ 669.538985] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:33:22 BXT-2 kernel: [ 669.539107] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:22 BXT-2 kernel: [ 669.539151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:22 BXT-2 kernel: [ 669.539195] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 78750KHz >May 24 03:33:22 BXT-2 kernel: [ 669.539239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24 >May 24 03:33:22 BXT-2 kernel: [ 669.539281] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000 >May 24 03:33:22 BXT-2 kernel: [ 669.539326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:22 BXT-2 kernel: [ 669.539368] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:22 BXT-2 kernel: [ 669.539411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:22 BXT-2 kernel: [ 669.539454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 191146, gmch_n: 262144, link_m: 63715, link_n: 131072, tu: 64 >May 24 03:33:22 BXT-2 kernel: [ 669.540063] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:22 BXT-2 kernel: [ 669.540106] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:22 BXT-2 kernel: [ 669.540116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.540158] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:22 BXT-2 kernel: [ 669.540165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.540209] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5 >May 24 03:33:22 BXT-2 kernel: [ 669.540252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750 >May 24 03:33:22 BXT-2 kernel: [ 669.540296] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:22 BXT-2 kernel: [ 669.540340] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:22 BXT-2 kernel: [ 669.540383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:22 BXT-2 kernel: [ 669.540428] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:22 BXT-2 kernel: [ 669.540471] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:22 BXT-2 kernel: [ 669.540891] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:77, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:33:22 BXT-2 kernel: [ 669.540935] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:33:22 BXT-2 kernel: [ 669.540980] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:22 BXT-2 kernel: [ 669.541023] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:22 BXT-2 kernel: [ 669.541067] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:22 BXT-2 kernel: [ 669.541138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:22 BXT-2 kernel: [ 669.541193] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:22 BXT-2 kernel: [ 669.541236] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:22 BXT-2 kernel: [ 669.542654] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:22 BXT-2 kernel: [ 669.556847] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:22 BXT-2 kernel: [ 669.556968] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:22 BXT-2 kernel: [ 669.557025] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:22 BXT-2 kernel: [ 669.557359] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:22 BXT-2 kernel: [ 669.557404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:22 BXT-2 kernel: [ 669.557447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:22 BXT-2 kernel: [ 669.557644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:22 BXT-2 kernel: [ 669.557687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:22 BXT-2 kernel: [ 669.557730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:22 BXT-2 kernel: [ 669.557773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:22 BXT-2 kernel: [ 669.557816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:22 BXT-2 kernel: [ 669.557859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:22 BXT-2 kernel: [ 669.557902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:22 BXT-2 kernel: [ 669.557952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:22 BXT-2 kernel: [ 669.557999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:22 BXT-2 kernel: [ 669.558080] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:22 BXT-2 kernel: [ 669.558124] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:22 BXT-2 kernel: [ 669.559718] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:22 BXT-2 kernel: [ 669.559764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:22 BXT-2 kernel: [ 669.559810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:22 BXT-2 kernel: [ 669.560708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:22 BXT-2 kernel: [ 669.560752] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:22 BXT-2 kernel: [ 669.561671] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:22 BXT-2 kernel: [ 669.561719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:22 BXT-2 kernel: [ 669.562936] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:22 BXT-2 kernel: [ 669.565087] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2 >May 24 03:33:22 BXT-2 kernel: [ 669.567171] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:22 BXT-2 kernel: [ 669.580755] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:22 BXT-2 kernel: [ 669.580829] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:22 BXT-2 kernel: [ 669.581032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 669.900921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.901079] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:33:23 BXT-2 kernel: [ 669.916254] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:33:23 BXT-2 kernel: [ 669.916375] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 669.916559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:23 BXT-2 kernel: [ 669.916609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:23 BXT-2 kernel: [ 669.916653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:23 BXT-2 kernel: [ 669.916696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:23 BXT-2 kernel: [ 669.916740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:23 BXT-2 kernel: [ 669.916789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:23 BXT-2 kernel: [ 669.916833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:23 BXT-2 kernel: [ 669.916877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:23 BXT-2 kernel: [ 669.916922] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:23 BXT-2 kernel: [ 669.916970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:23 BXT-2 kernel: [ 669.917018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:23 BXT-2 kernel: [ 669.917064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 669.917125] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:23 BXT-2 kernel: [ 669.917172] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.917241] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.917306] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:23 BXT-2 kernel: [ 669.917359] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:23 BXT-2 kernel: [ 669.917406] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:23 BXT-2 kernel: [ 669.917446] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:23 BXT-2 kernel: [ 669.918040] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:23 BXT-2 kernel: [ 669.918530] [drm:intel_runtime_suspend [i915]] Suspending device >May 24 03:33:23 BXT-2 kernel: [ 669.918778] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4 >May 24 03:33:23 BXT-2 kernel: [ 669.918931] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:23 BXT-2 kernel: [ 669.919772] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.919813] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:33:23 BXT-2 kernel: [ 669.919869] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:33:23 BXT-2 kernel: [ 669.919917] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:33:23 BXT-2 kernel: [ 669.919977] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:33:23 BXT-2 kernel: [ 669.920019] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:33:23 BXT-2 kernel: [ 669.920095] [drm:intel_runtime_suspend [i915]] Device suspended >May 24 03:33:23 BXT-2 kernel: [ 669.943648] [drm:intel_runtime_resume [i915]] Resuming device >May 24 03:33:23 BXT-2 kernel: [ 669.943699] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:33:23 BXT-2 kernel: [ 669.943740] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00 >May 24 03:33:23 BXT-2 kernel: [ 669.943811] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:33:23 BXT-2 kernel: [ 669.943982] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:33:23 BXT-2 kernel: [ 669.944175] [drm:skl_set_power_well [i915]] Enabling power well 1 >May 24 03:33:23 BXT-2 kernel: [ 669.944230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.944272] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:33:23 BXT-2 kernel: [ 669.944632] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.947665] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:23 BXT-2 kernel: [ 669.947708] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:23 BXT-2 kernel: [ 669.950761] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:33:23 BXT-2 kernel: [ 669.951312] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:33:23 BXT-2 kernel: [ 669.951382] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:33:23 BXT-2 kernel: [ 669.951941] [drm:intel_runtime_resume [i915]] Device resumed >May 24 03:33:23 BXT-2 kernel: [ 669.952731] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:23 BXT-2 kernel: [ 669.952774] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:23 BXT-2 kernel: [ 669.953069] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:23 BXT-2 kernel: [ 669.953129] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.953171] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.953233] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:23 BXT-2 kernel: [ 669.953680] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:23 BXT-2 kernel: [ 669.953741] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.953811] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.953856] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:23 BXT-2 kernel: [ 669.953904] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:23 BXT-2 kernel: [ 669.953945] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:23 BXT-2 kernel: [ 669.954530] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:23 BXT-2 kernel: [ 669.954543] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:33:23 BXT-2 kernel: [ 669.954594] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:23 BXT-2 kernel: [ 669.954634] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:23 BXT-2 kernel: [ 669.954673] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:23 BXT-2 kernel: [ 669.955176] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:23 BXT-2 kernel: [ 669.955753] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.955797] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.955858] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:23 BXT-2 kernel: [ 669.957083] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:33:23 BXT-2 kernel: [ 669.958107] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:33:23 BXT-2 kernel: [ 669.958154] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:33:23 BXT-2 kernel: [ 669.958197] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:33:23 BXT-2 kernel: [ 669.958239] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:33:23 BXT-2 kernel: [ 669.959363] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:33:23 BXT-2 kernel: [ 669.959421] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:33:23 BXT-2 kernel: [ 669.964385] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:33:23 BXT-2 kernel: [ 669.964433] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.964561] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.964610] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:33:23 BXT-2 kernel: [ 669.964852] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:33:23 BXT-2 kernel: [ 669.964891] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:33:23 BXT-2 kernel: [ 669.965444] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:33:23 BXT-2 kernel: [ 669.965488] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:33:23 BXT-2 kernel: [ 669.977849] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:33:23 BXT-2 kernel: [ 669.977896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:33:23 BXT-2 kernel: [ 669.977941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:33:23 BXT-2 kernel: [ 669.977986] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:33:23 BXT-2 kernel: [ 669.978028] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:33:23 BXT-2 kernel: [ 669.978072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:33:23 BXT-2 kernel: [ 669.978116] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:33:23 BXT-2 kernel: [ 669.978159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:33:23 BXT-2 kernel: [ 669.978202] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:33:23 BXT-2 kernel: [ 669.978245] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:33:23 BXT-2 kernel: [ 669.978286] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:33:23 BXT-2 kernel: [ 669.978295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:23 BXT-2 kernel: [ 669.978337] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:33:23 BXT-2 kernel: [ 669.978343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:33:23 BXT-2 kernel: [ 669.978386] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:33:23 BXT-2 kernel: [ 669.978429] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:33:23 BXT-2 kernel: [ 669.978472] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:33:23 BXT-2 kernel: [ 669.978585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:33:23 BXT-2 kernel: [ 669.978632] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:33:23 BXT-2 kernel: [ 669.978680] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:33:23 BXT-2 kernel: [ 669.978723] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:33:23 BXT-2 kernel: [ 669.978769] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:33:23 BXT-2 kernel: [ 669.978815] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:33:23 BXT-2 kernel: [ 669.978860] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:33:23 BXT-2 kernel: [ 669.978905] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:33:23 BXT-2 kernel: [ 669.978956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.979011] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 669.979056] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:33:23 BXT-2 kernel: [ 669.979184] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:33:23 BXT-2 kernel: [ 669.979222] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:33:23 BXT-2 kernel: [ 669.979546] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:33:23 BXT-2 kernel: [ 669.979613] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.979657] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:33:23 BXT-2 kernel: [ 669.979721] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:33:23 BXT-2 kernel: [ 669.979981] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.980311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:33:23 BXT-2 kernel: [ 669.980357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:33:23 BXT-2 kernel: [ 669.980402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:33:23 BXT-2 kernel: [ 669.980446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:33:23 BXT-2 kernel: [ 669.980527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:33:23 BXT-2 kernel: [ 669.980571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:33:23 BXT-2 kernel: [ 669.980616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:33:23 BXT-2 kernel: [ 669.980659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:33:23 BXT-2 kernel: [ 669.980702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:33:23 BXT-2 kernel: [ 669.980746] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:33:23 BXT-2 kernel: [ 669.980795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:33:23 BXT-2 kernel: [ 669.980843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 669.980922] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:33:23 BXT-2 kernel: [ 669.980966] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 669.982627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:23 BXT-2 kernel: [ 669.982672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:23 BXT-2 kernel: [ 669.982718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:33:23 BXT-2 kernel: [ 669.983626] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:33:23 BXT-2 kernel: [ 669.983669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:33:23 BXT-2 kernel: [ 669.984406] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:33:23 BXT-2 kernel: [ 669.984450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:33:23 BXT-2 kernel: [ 669.985633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:33:23 BXT-2 kernel: [ 669.987742] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:33:23 BXT-2 kernel: [ 669.989670] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:33:23 BXT-2 kernel: [ 670.006625] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:33:23 BXT-2 kernel: [ 670.006687] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:33:23 BXT-2 kernel: [ 670.006884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:33:23 BXT-2 kernel: [ 670.023419] Console: switching to colour frame buffer device 240x67 >May 24 03:33:23 BXT-2 kernel: [ 670.272505] Console: switching to colour dummy device 80x25 >May 24 03:33:23 BXT-2 kernel: [ 670.311420] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1 >May 24 03:33:23 BXT-2 kernel: [ 670.323666] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:23 BXT-2 kernel: [ 670.339947] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1 >May 24 03:33:23 BXT-2 kernel: [ 670.356891] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:23 BXT-2 kernel: [ 670.374837] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1 >May 24 03:33:23 BXT-2 kernel: [ 670.390112] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:23 BXT-2 kernel: [ 670.404804] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1 >May 24 03:33:23 BXT-2 kernel: [ 670.440077] Console: switching to colour frame buffer device 240x67 >May 24 03:33:23 BXT-2 kernel: [ 670.677207] Console: switching to colour dummy device 80x25 >May 24 03:33:23 BXT-2 kernel: [ 670.740079] Console: switching to colour frame buffer device 240x67 >May 24 03:33:24 BXT-2 kernel: [ 670.989734] Console: switching to colour dummy device 80x25 >May 24 03:33:24 BXT-2 kernel: [ 671.006958] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1 >May 24 03:33:24 BXT-2 kernel: [ 671.007050] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1048576 >May 24 03:33:24 BXT-2 kernel: [ 671.007126] [drm:vgem_gem_dumb_create [vgem]] Created object of size 2147483648 >May 24 03:33:24 BXT-2 kernel: [ 671.023430] Console: switching to colour frame buffer device 240x67 >May 24 03:33:24 BXT-2 kernel: [ 671.296143] Console: switching to colour dummy device 80x25 >May 24 03:33:24 BXT-2 kernel: [ 671.306917] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:24 BXT-2 kernel: [ 671.323437] Console: switching to colour frame buffer device 240x67 >May 24 03:33:24 BXT-2 kernel: [ 671.589172] Console: switching to colour dummy device 80x25 >May 24 03:33:24 BXT-2 kernel: [ 671.628862] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:24 BXT-2 kernel: [ 671.673504] Console: switching to colour frame buffer device 240x67 >May 24 03:33:25 BXT-2 kernel: [ 671.929239] Console: switching to colour dummy device 80x25 >May 24 03:33:25 BXT-2 kernel: [ 671.940220] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304 >May 24 03:33:25 BXT-2 kernel: [ 671.956765] Console: switching to colour frame buffer device 240x67 >May 24 03:33:25 BXT-2 kernel: [ 672.204664] Console: switching to colour dummy device 80x25 >May 24 03:33:25 BXT-2 kernel: [ 672.223641] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:25 BXT-2 kernel: [ 672.240094] Console: switching to colour frame buffer device 240x67 >May 24 03:33:25 BXT-2 kernel: [ 672.488099] Console: switching to colour dummy device 80x25 >May 24 03:33:25 BXT-2 kernel: [ 672.506912] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:25 BXT-2 kernel: [ 672.507105] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096 >May 24 03:33:25 BXT-2 kernel: [ 672.523381] Console: switching to colour frame buffer device 240x67 >May 24 03:33:25 BXT-2 kernel: [ 672.770763] Console: switching to colour dummy device 80x25 >May 24 03:33:25 BXT-2 kernel: [ 672.806741] Console: switching to colour frame buffer device 240x67 >May 24 03:33:26 BXT-2 kernel: [ 673.050541] Console: switching to colour dummy device 80x25 >May 24 03:33:26 BXT-2 kernel: [ 673.073402] Console: switching to colour frame buffer device 240x67 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Linux version 4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ (gfx@bifrost) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4) ) #1 SMP PREEMPT Wed May 24 08:04:21 CDT 2017 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0xe auto panic=1 nmi_watchdog=panic resume=/dev/sda3 fastboot >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: xstate_offset[3]: 576, xstate_sizes[3]: 64 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: xstate_offset[4]: 640, xstate_sizes[4]: 64 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 704 bytes, using 'compacted' format. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] e820: BIOS-provided physical RAM map: >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000003efff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000000003f000-0x000000000003ffff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000040000-0x000000000009dfff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000012151000-0x0000000077716fff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000077717000-0x0000000079838fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079839000-0x0000000079853fff] ACPI data >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079854000-0x00000000798b3fff] ACPI NVS >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000798b4000-0x0000000079bdefff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079bdf000-0x0000000079c43fff] type 20 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079c44000-0x0000000079fc5fff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079fc6000-0x0000000079fc6fff] ACPI NVS >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079fc7000-0x0000000079ff0fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079ff1000-0x000000007a9defff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007a9df000-0x000000007a9e0fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007a9e1000-0x000000007affffff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000d0000000-0x00000000d0ffffff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fe042000-0x00000000fe044fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fe900000-0x00000000fe902fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000047fffffff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] tsc: Using PIT calibration value >May 24 03:34:09 BXT-2 kernel: [ 0.000000] NX (Execute Disable) protection: active >May 24 03:34:09 BXT-2 kernel: [ 0.000000] efi: EFI v2.50 by American Megatrends >May 24 03:34:09 BXT-2 kernel: [ 0.000000] efi: ACPI=0x79846000 ACPI 2.0=0x79846000 SMBIOS=0x79aa8000 SMBIOS 3.0=0x79aa7000 ESRT=0x79aa2a58 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] SMBIOS 3.0.0 present. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMI: Intel corporation NUC6CAYS/NUC6CAYB, BIOS AYAPLCEL.86A.0038.2017.0310.1633 03/10/2017 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] e820: last_pfn = 0x480000 max_arch_pfn = 0x400000000 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] MTRR default type: uncachable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] MTRR fixed ranges enabled: >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 00000-6FFFF write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 70000-7FFFF uncachable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 80000-9FFFF write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] A0000-BFFFF uncachable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] C0000-FFFFF write-protect >May 24 03:34:09 BXT-2 kernel: [ 0.000000] MTRR variable ranges enabled: >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 0 base 0000000000 mask 7F80000000 write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 1 base 007C000000 mask 7FFC000000 uncachable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 2 base 007B000000 mask 7FFF000000 uncachable >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 3 base 0100000000 mask 7F00000000 write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 4 base 0200000000 mask 7F00000000 write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 5 base 0300000000 mask 7F00000000 write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 6 base 0400000000 mask 7F80000000 write-back >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 7 base 00FF000000 mask 7FFF000000 write-combining >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 8 disabled >May 24 03:34:09 BXT-2 kernel: [ 0.000000] 9 disabled >May 24 03:34:09 BXT-2 kernel: [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT >May 24 03:34:09 BXT-2 kernel: [ 0.000000] e820: last_pfn = 0x7b000 max_arch_pfn = 0x400000000 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] esrt: Reserving ESRT space from 0x0000000079aa2a58 to 0x0000000079aa2a90. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Using GB pages for direct mapping >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BRK [0x056c2000, 0x056c2fff] PGTABLE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BRK [0x056c3000, 0x056c3fff] PGTABLE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BRK [0x056c4000, 0x056c4fff] PGTABLE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BRK [0x056c5000, 0x056c5fff] PGTABLE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BRK [0x056c6000, 0x056c6fff] PGTABLE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] BRK [0x056c7000, 0x056c7fff] PGTABLE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Secure boot could not be determined >May 24 03:34:09 BXT-2 kernel: [ 0.000000] RAMDISK: [mem 0x369f4000-0x374f1fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: Early table checksum verification disabled >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: RSDP 0x0000000079846000 000024 (v02 INTEL ) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: XSDT 0x00000000798460D0 0000FC (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: FACP 0x000000007984EF60 000114 (v06 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: DSDT 0x0000000079846260 008CF8 (v02 INTEL NUC6CAYB 01072009 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: FACS 0x0000000079883080 000040 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: FPDT 0x000000007984F080 000044 (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: FIDT 0x000000007984F0D0 00009C (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: MCFG 0x000000007984F170 00003C (v01 INTEL NUC6CAYB 01072009 MSFT 00000097) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: DBG2 0x000000007984F1B0 000072 (v00 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: DBGP 0x000000007984F230 000034 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: HPET 0x000000007984F270 000038 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: LPIT 0x000000007984F2B0 00005C (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: APIC 0x000000007984F310 000084 (v03 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: NPKT 0x000000007984F3A0 000065 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: PRAM 0x000000007984F410 000030 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: WSMT 0x000000007984F440 000028 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x000000007984F470 00002B (v02 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x000000007984F4A0 000A19 (v01 INTEL NUC6CAYB 00001000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x000000007984FEC0 000442 (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850310 00072B (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850A40 00032D (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850D70 00017C (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850EF0 002740 (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: UEFI 0x0000000079853630 000042 (v01 INTEL NUC6CAYB 00000000 00000000) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: BGRT 0x0000000079853680 000038 (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: TPM2 0x00000000798536C0 000034 (v03 INTEL NUC6CAYB 00000001 AMI 00000000) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079853700 0001F8 (v01 INTEL NUC6CAYB 00001000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: MSDM 0x0000000079853900 000055 (v03 INTEL NUC6CAYB 01072009 AMI AFAFAFAF) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: DMAR 0x0000000079853960 0000A8 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: WDAT 0x0000000079853A10 000104 (v01 INTEL NUC6CAYB 00000000 00000000) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: NHLT 0x0000000079853B20 00002D (v00 INTEL NUC6CAYB 00000002 01000013) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Zone ranges: >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Normal [mem 0x0000000100000000-0x000000047fffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Movable zone start for each node >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Early memory node ranges >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000000001000-0x000000000003efff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000000040000-0x000000000009dfff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000000100000-0x000000000fffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000012151000-0x0000000077716fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000079c44000-0x0000000079fc5fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000079ff1000-0x000000007a9defff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x000000007a9e1000-0x000000007affffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000100000000-0x000000047fffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000047fffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] On node 0 totalpages: 4155633 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA zone: 64 pages used for memmap >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA zone: 22 pages reserved >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA zone: 3996 pages, LIFO batch:0 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA32 zone: 7526 pages used for memmap >May 24 03:34:09 BXT-2 kernel: [ 0.000000] DMA32 zone: 481621 pages, LIFO batch:31 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Normal zone: 57344 pages used for memmap >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Normal zone: 3670016 pages, LIFO batch:31 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Reserving Intel graphics memory at 0x000000007c000000-0x000000007fffffff >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: PM-Timer IO Port: 0x408 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1]) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1]) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1]) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1]) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: IRQ0 used by override. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: IRQ9 used by override. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Using ACPI (MADT) for SMP configuration information >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x0003f000-0x0003ffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x10000000-0x12150fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x77717000-0x79838fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79839000-0x79853fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79854000-0x798b3fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x798b4000-0x79bdefff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79bdf000-0x79c43fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79fc6000-0x79fc6fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79fc7000-0x79ff0fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x7a9df000-0x7a9e0fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x80000000-0xcfffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xd0000000-0xd0ffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xd1000000-0xdfffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfe041fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe042000-0xfe044fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe045000-0xfe8fffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe900000-0xfe902fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe903000-0xfebfffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfed00fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xfedfffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff] >May 24 03:34:09 BXT-2 kernel: [ 0.000000] e820: [mem 0x80000000-0xcfffffff] available for PCI devices >May 24 03:34:09 BXT-2 kernel: [ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns >May 24 03:34:09 BXT-2 kernel: [ 0.000000] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] percpu: Embedded 37 pages/cpu @ffff88047fc00000 s114376 r8192 d28984 u524288 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] pcpu-alloc: s114376 r8192 d28984 u524288 alloc=1*2097152 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] pcpu-alloc: [0] 0 1 2 3 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 4090677 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0xe auto panic=1 nmi_watchdog=panic resume=/dev/sda3 fastboot >May 24 03:34:09 BXT-2 kernel: [ 0.000000] log_buf_len individual max cpu contribution: 262144 bytes >May 24 03:34:09 BXT-2 kernel: [ 0.000000] log_buf_len total cpu_extra contributions: 786432 bytes >May 24 03:34:09 BXT-2 kernel: [ 0.000000] log_buf_len min size: 262144 bytes >May 24 03:34:09 BXT-2 kernel: [ 0.000000] log_buf_len: 1048576 bytes >May 24 03:34:09 BXT-2 kernel: [ 0.000000] early log buf free: 247796(94%) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Memory: 16128012K/16622532K available (8664K kernel code, 1377K rwdata, 3444K rodata, 1200K init, 22640K bss, 494520K reserved, 0K cma-reserved) >May 24 03:34:09 BXT-2 kernel: [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Running RCU self tests >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Preemptible hierarchical RCU implementation. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] RCU lockdep checking is enabled. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4. >May 24 03:34:09 BXT-2 kernel: [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] kmemleak: Kernel memory leak detector disabled >May 24 03:34:09 BXT-2 kernel: [ 0.000000] NR_IRQS:4352 nr_irqs:1024 16 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Console: colour dummy device 80x25 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] console [tty0] enabled >May 24 03:34:09 BXT-2 kernel: [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... MAX_LOCK_DEPTH: 48 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... CLASSHASH_SIZE: 4096 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 32768 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_CHAINS: 65536 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] ... CHAINHASH_SIZE: 32768 >May 24 03:34:09 BXT-2 kernel: [ 0.000000] memory used by lock dependency info: 8159 kB >May 24 03:34:09 BXT-2 kernel: [ 0.000000] per task-struct memory footprint: 1920 bytes >May 24 03:34:09 BXT-2 kernel: [ 0.000000] kmemleak: Early log buffer exceeded (2891), please increase DEBUG_KMEMLEAK_EARLY_LOG_SIZE >May 24 03:34:09 BXT-2 kernel: [ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns >May 24 03:34:09 BXT-2 kernel: [ 0.000000] hpet clockevent registered >May 24 03:34:09 BXT-2 kernel: [ 0.002000] tsc: PIT calibration matches HPET. 1 loops >May 24 03:34:09 BXT-2 kernel: [ 0.002000] tsc: Detected 1497.600 MHz processor >May 24 03:34:09 BXT-2 kernel: [ 0.002000] Calibrating delay loop (skipped), value calculated using timer frequency.. 2995.20 BogoMIPS (lpj=1497600) >May 24 03:34:09 BXT-2 kernel: [ 0.002000] pid_max: default: 32768 minimum: 301 >May 24 03:34:09 BXT-2 kernel: [ 0.002000] ACPI: Core revision 20170303 >May 24 03:34:09 BXT-2 kernel: [ 0.201648] ACPI: 9 ACPI AML tables successfully acquired and loaded >May 24 03:34:09 BXT-2 kernel: [ 0.203104] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.203113] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.204796] CPU: Physical Processor ID: 0 >May 24 03:34:09 BXT-2 kernel: [ 0.204802] CPU: Processor Core ID: 0 >May 24 03:34:09 BXT-2 kernel: [ 0.204830] mce: CPU supports 7 MCE banks >May 24 03:34:09 BXT-2 kernel: [ 0.204893] CPU0: Thermal monitoring enabled (TM1) >May 24 03:34:09 BXT-2 kernel: [ 0.205034] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0 >May 24 03:34:09 BXT-2 kernel: [ 0.205038] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 >May 24 03:34:09 BXT-2 kernel: [ 0.205625] Freeing SMP alternatives memory: 32K >May 24 03:34:09 BXT-2 kernel: [ 0.233439] smpboot: Max logical packages: 1 >May 24 03:34:09 BXT-2 kernel: [ 0.233458] DMAR: Host address width 39 >May 24 03:34:09 BXT-2 kernel: [ 0.233464] DMAR: DRHD base: 0x000000fed64000 flags: 0x0 >May 24 03:34:09 BXT-2 kernel: [ 0.233539] DMAR: dmar0: reg_base_addr fed64000 ver 1:0 cap 1c0000c40660462 ecap 7e3ff0505e >May 24 03:34:09 BXT-2 kernel: [ 0.233544] DMAR: DRHD base: 0x000000fed65000 flags: 0x1 >May 24 03:34:09 BXT-2 kernel: [ 0.233592] DMAR: dmar1: reg_base_addr fed65000 ver 1:0 cap d2008c40660462 ecap f050da >May 24 03:34:09 BXT-2 kernel: [ 0.233598] DMAR: RMRR base: 0x000000797d4000 end: 0x000000797f3fff >May 24 03:34:09 BXT-2 kernel: [ 0.233619] DMAR: RMRR base: 0x0000007b800000 end: 0x0000007fffffff >May 24 03:34:09 BXT-2 kernel: [ 0.233639] DMAR-IR: IOAPIC id 1 under DRHD base 0xfed65000 IOMMU 1 >May 24 03:34:09 BXT-2 kernel: [ 0.233644] DMAR-IR: HPET id 0 under DRHD base 0xfed65000 >May 24 03:34:09 BXT-2 kernel: [ 0.233648] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping. >May 24 03:34:09 BXT-2 kernel: [ 0.235968] DMAR-IR: Enabled IRQ remapping in x2apic mode >May 24 03:34:09 BXT-2 kernel: [ 0.235975] x2apic enabled >May 24 03:34:09 BXT-2 kernel: [ 0.236024] Switched APIC routing to cluster x2apic. >May 24 03:34:09 BXT-2 kernel: [ 0.241000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 >May 24 03:34:09 BXT-2 kernel: [ 0.250975] TSC deadline timer enabled >May 24 03:34:09 BXT-2 kernel: [ 0.250993] smpboot: CPU0: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz (family: 0x6, model: 0x5c, stepping: 0x9) >May 24 03:34:09 BXT-2 kernel: [ 0.254097] Performance Events: PEBS fmt3+, Goldmont events, 32-deep LBR, full-width counters, Intel PMU driver. >May 24 03:34:09 BXT-2 kernel: [ 0.254152] ... version: 4 >May 24 03:34:09 BXT-2 kernel: [ 0.254156] ... bit width: 48 >May 24 03:34:09 BXT-2 kernel: [ 0.254160] ... generic registers: 4 >May 24 03:34:09 BXT-2 kernel: [ 0.254164] ... value mask: 0000ffffffffffff >May 24 03:34:09 BXT-2 kernel: [ 0.254168] ... max period: 00007fffffffffff >May 24 03:34:09 BXT-2 kernel: [ 0.254171] ... fixed-purpose events: 3 >May 24 03:34:09 BXT-2 kernel: [ 0.254175] ... event mask: 000000070000000f >May 24 03:34:09 BXT-2 kernel: [ 0.262741] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. >May 24 03:34:09 BXT-2 kernel: [ 0.264023] smp: Bringing up secondary CPUs ... >May 24 03:34:09 BXT-2 kernel: [ 0.272201] x86: Booting SMP configuration: >May 24 03:34:09 BXT-2 kernel: [ 0.272214] .... node #0, CPUs: #1 #2 #3 >May 24 03:34:09 BXT-2 kernel: [ 0.468283] smp: Brought up 1 node, 4 CPUs >May 24 03:34:09 BXT-2 kernel: [ 0.468283] smpboot: Total of 4 processors activated (12087.38 BogoMIPS) >May 24 03:34:09 BXT-2 kernel: [ 0.469843] sched_clock: Marking stable (469000000, 0)->(472596792, -3596792) >May 24 03:34:09 BXT-2 kernel: [ 0.471858] devtmpfs: initialized >May 24 03:34:09 BXT-2 kernel: [ 0.474221] PM: Registering ACPI NVS region [mem 0x79854000-0x798b3fff] (393216 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.474679] PM: Registering ACPI NVS region [mem 0x79fc6000-0x79fc6fff] (4096 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.476826] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns >May 24 03:34:09 BXT-2 kernel: [ 0.476841] futex hash table entries: 1024 (order: 5, 131072 bytes) >May 24 03:34:09 BXT-2 kernel: [ 0.477309] xor: measuring software checksum speed >May 24 03:34:09 BXT-2 kernel: [ 0.487294] prefetch64-sse: 7540.000 MB/sec >May 24 03:34:09 BXT-2 kernel: [ 0.497361] generic_sse: 6484.000 MB/sec >May 24 03:34:09 BXT-2 kernel: [ 0.497366] xor: using function: prefetch64-sse (7540.000 MB/sec) >May 24 03:34:09 BXT-2 kernel: [ 0.497401] pinctrl core: initialized pinctrl subsystem >May 24 03:34:09 BXT-2 kernel: [ 0.502947] NET: Registered protocol family 16 >May 24 03:34:09 BXT-2 kernel: [ 0.505896] cpuidle: using governor menu >May 24 03:34:09 BXT-2 kernel: [ 0.505908] PCCT header not found. >May 24 03:34:09 BXT-2 kernel: [ 0.506216] ACPI: bus type PCI registered >May 24 03:34:09 BXT-2 kernel: [ 0.506798] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) >May 24 03:34:09 BXT-2 kernel: [ 0.506807] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 >May 24 03:34:09 BXT-2 kernel: [ 0.506866] PCI: Using configuration type 1 for base access >May 24 03:34:09 BXT-2 kernel: [ 0.533588] HugeTLB registered 2 MB page size, pre-allocated 0 pages >May 24 03:34:09 BXT-2 kernel: [ 0.551973] raid6: sse2x1 gen() 3230 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.569163] raid6: sse2x1 xor() 1958 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.586358] raid6: sse2x2 gen() 3742 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.603549] raid6: sse2x2 xor() 2292 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.620725] raid6: sse2x4 gen() 4273 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.637912] raid6: sse2x4 xor() 2265 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.637917] raid6: using algorithm sse2x4 gen() 4273 MB/s >May 24 03:34:09 BXT-2 kernel: [ 0.637920] raid6: .... xor() 2265 MB/s, rmw enabled >May 24 03:34:09 BXT-2 kernel: [ 0.637925] raid6: using ssse3x2 recovery algorithm >May 24 03:34:09 BXT-2 kernel: [ 0.638322] ACPI: Added _OSI(Module Device) >May 24 03:34:09 BXT-2 kernel: [ 0.638327] ACPI: Added _OSI(Processor Device) >May 24 03:34:09 BXT-2 kernel: [ 0.638332] ACPI: Added _OSI(3.0 _SCP Extensions) >May 24 03:34:09 BXT-2 kernel: [ 0.638337] ACPI: Added _OSI(Processor Aggregator Device) >May 24 03:34:09 BXT-2 kernel: [ 0.642536] ACPI: Executed 3 blocks of module-level executable AML code >May 24 03:34:09 BXT-2 kernel: [ 0.777431] ACPI: Dynamic OEM Table Load: >May 24 03:34:09 BXT-2 kernel: [ 0.777491] ACPI: SSDT 0xFFFF88046CE8A7C8 000102 (v02 PmRef Cpu0Cst 00003001 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.785730] ACPI: Dynamic OEM Table Load: >May 24 03:34:09 BXT-2 kernel: [ 0.785785] ACPI: SSDT 0xFFFF88046CE89A88 00015F (v02 PmRef ApIst 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.789744] ACPI: Dynamic OEM Table Load: >May 24 03:34:09 BXT-2 kernel: [ 0.789799] ACPI: SSDT 0xFFFF88046CEAEB58 00008D (v02 PmRef ApCst 00003000 INTL 20120913) >May 24 03:34:09 BXT-2 kernel: [ 0.812108] ACPI : EC: EC started >May 24 03:34:09 BXT-2 kernel: [ 0.812120] ACPI : EC: interrupt blocked >May 24 03:34:09 BXT-2 kernel: [ 0.812596] ACPI: \_SB_.PCI0.SBRG.H_EC: Used as first EC >May 24 03:34:09 BXT-2 kernel: [ 0.812614] ACPI: \_SB_.PCI0.SBRG.H_EC: GPE=0x40, EC_CMD/EC_SC=0x66, EC_DATA=0x62 >May 24 03:34:09 BXT-2 kernel: [ 0.812629] ACPI: \_SB_.PCI0.SBRG.H_EC: Used as boot DSDT EC to handle transactions >May 24 03:34:09 BXT-2 kernel: [ 0.812637] ACPI: Interpreter enabled >May 24 03:34:09 BXT-2 kernel: [ 0.812875] ACPI: (supports S0 S3 S4 S5) >May 24 03:34:09 BXT-2 kernel: [ 0.812880] ACPI: Using IOAPIC for interrupt routing >May 24 03:34:09 BXT-2 kernel: [ 0.813333] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug >May 24 03:34:09 BXT-2 kernel: [ 1.000538] ACPI: Power Resource [FN00] (on) >May 24 03:34:09 BXT-2 kernel: [ 1.018718] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) >May 24 03:34:09 BXT-2 kernel: [ 1.018753] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] >May 24 03:34:09 BXT-2 kernel: [ 1.035884] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] >May 24 03:34:09 BXT-2 kernel: [ 1.040047] PCI host bridge to bus 0000:00 >May 24 03:34:09 BXT-2 kernel: [ 1.040060] pci_bus 0000:00: root bus resource [io 0x0070-0x0077] >May 24 03:34:09 BXT-2 kernel: [ 1.040070] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window] >May 24 03:34:09 BXT-2 kernel: [ 1.040080] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window] >May 24 03:34:09 BXT-2 kernel: [ 1.040089] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.040099] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.040108] pci_bus 0000:00: root bus resource [mem 0x7b800001-0x7bffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.040127] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.040137] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.040149] pci_bus 0000:00: root bus resource [bus 00-ff] >May 24 03:34:09 BXT-2 kernel: [ 1.040224] pci 0000:00:00.0: [8086:5af0] type 00 class 0x060000 >May 24 03:34:09 BXT-2 kernel: [ 1.044692] pci 0000:00:02.0: [8086:5a85] type 00 class 0x030000 >May 24 03:34:09 BXT-2 kernel: [ 1.044733] pci 0000:00:02.0: reg 0x10: [mem 0x90000000-0x90ffffff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.044758] pci 0000:00:02.0: reg 0x18: [mem 0x80000000-0x8fffffff 64bit pref] >May 24 03:34:09 BXT-2 kernel: [ 1.044776] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f] >May 24 03:34:09 BXT-2 kernel: [ 1.049578] pci 0000:00:0e.0: [8086:5a98] type 00 class 0x040380 >May 24 03:34:09 BXT-2 kernel: [ 1.049634] pci 0000:00:0e.0: reg 0x10: [mem 0x91410000-0x91413fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.049714] pci 0000:00:0e.0: reg 0x20: [mem 0x91000000-0x910fffff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.049931] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.055033] pci 0000:00:0e.0: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.055447] pci 0000:00:0f.0: [8086:5a9a] type 00 class 0x078000 >May 24 03:34:09 BXT-2 kernel: [ 1.055514] pci 0000:00:0f.0: reg 0x10: [mem 0x91429000-0x91429fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.055799] pci 0000:00:0f.0: PME# supported from D3hot >May 24 03:34:09 BXT-2 kernel: [ 1.059967] pci 0000:00:12.0: [8086:5ae3] type 00 class 0x010601 >May 24 03:34:09 BXT-2 kernel: [ 1.060013] pci 0000:00:12.0: reg 0x10: [mem 0x91414000-0x91415fff] >May 24 03:34:09 BXT-2 kernel: [ 1.060055] pci 0000:00:12.0: reg 0x14: [mem 0x91426000-0x914260ff] >May 24 03:34:09 BXT-2 kernel: [ 1.060079] pci 0000:00:12.0: reg 0x18: [io 0xf090-0xf097] >May 24 03:34:09 BXT-2 kernel: [ 1.060103] pci 0000:00:12.0: reg 0x1c: [io 0xf080-0xf083] >May 24 03:34:09 BXT-2 kernel: [ 1.060133] pci 0000:00:12.0: reg 0x20: [io 0xf060-0xf07f] >May 24 03:34:09 BXT-2 kernel: [ 1.060157] pci 0000:00:12.0: reg 0x24: [mem 0x91425000-0x914257ff] >May 24 03:34:09 BXT-2 kernel: [ 1.060323] pci 0000:00:12.0: PME# supported from D3hot >May 24 03:34:09 BXT-2 kernel: [ 1.064439] pci 0000:00:13.0: [8086:5ad8] type 01 class 0x060400 >May 24 03:34:09 BXT-2 kernel: [ 1.064709] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.068547] pci 0000:00:13.0: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.068941] pci 0000:00:13.1: [8086:5ad9] type 01 class 0x060400 >May 24 03:34:09 BXT-2 kernel: [ 1.069222] pci 0000:00:13.1: PME# supported from D0 D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.073042] pci 0000:00:13.1: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.073473] pci 0000:00:13.2: [8086:5ada] type 01 class 0x060400 >May 24 03:34:09 BXT-2 kernel: [ 1.073740] pci 0000:00:13.2: PME# supported from D0 D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.077586] pci 0000:00:13.2: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.078027] pci 0000:00:15.0: [8086:5aa8] type 00 class 0x0c0330 >May 24 03:34:09 BXT-2 kernel: [ 1.078097] pci 0000:00:15.0: reg 0x10: [mem 0x91400000-0x9140ffff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.078386] pci 0000:00:15.0: PME# supported from D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.082388] pci 0000:00:15.0: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.082837] pci 0000:00:16.0: [8086:5aac] type 00 class 0x118000 >May 24 03:34:09 BXT-2 kernel: [ 1.082894] pci 0000:00:16.0: reg 0x10: [mem 0x91424000-0x91424fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.082930] pci 0000:00:16.0: reg 0x18: [mem 0x91423000-0x91423fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.087237] pci 0000:00:18.0: [8086:5abc] type 00 class 0x118000 >May 24 03:34:09 BXT-2 kernel: [ 1.087293] pci 0000:00:18.0: reg 0x10: [mem 0x91422000-0x91422fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.087329] pci 0000:00:18.0: reg 0x18: [mem 0x91421000-0x91421fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.091629] pci 0000:00:19.0: [8086:5ac2] type 00 class 0x118000 >May 24 03:34:09 BXT-2 kernel: [ 1.091687] pci 0000:00:19.0: reg 0x10: [mem 0x91420000-0x91420fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.091729] pci 0000:00:19.0: reg 0x18: [mem 0x9141f000-0x9141ffff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.095959] pci 0000:00:19.1: [8086:5ac4] type 00 class 0x118000 >May 24 03:34:09 BXT-2 kernel: [ 1.096022] pci 0000:00:19.1: reg 0x10: [mem 0x9141e000-0x9141efff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.096058] pci 0000:00:19.1: reg 0x18: [mem 0x9141d000-0x9141dfff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.100295] pci 0000:00:19.2: [8086:5ac6] type 00 class 0x118000 >May 24 03:34:09 BXT-2 kernel: [ 1.100352] pci 0000:00:19.2: reg 0x10: [mem 0x9141c000-0x9141cfff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.100388] pci 0000:00:19.2: reg 0x18: [mem 0x9141b000-0x9141bfff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.104672] pci 0000:00:1a.0: [8086:5ac8] type 00 class 0x0c8000 >May 24 03:34:09 BXT-2 kernel: [ 1.104748] pci 0000:00:1a.0: reg 0x10: [mem 0x9141a000-0x9141afff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.104785] pci 0000:00:1a.0: reg 0x18: [mem 0x91419000-0x91419fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.104989] pci 0000:00:1a.0: PME# supported from D0 D3hot >May 24 03:34:09 BXT-2 kernel: [ 1.109113] pci 0000:00:1c.0: [8086:5acc] type 00 class 0x080501 >May 24 03:34:09 BXT-2 kernel: [ 1.109177] pci 0000:00:1c.0: reg 0x10: [mem 0x91418000-0x91418fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.109214] pci 0000:00:1c.0: reg 0x18: [mem 0x91417000-0x91417fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.113946] pci 0000:00:1f.0: [8086:5ae8] type 00 class 0x060100 >May 24 03:34:09 BXT-2 kernel: [ 1.118269] pci 0000:00:1f.1: [8086:5ad4] type 00 class 0x0c0500 >May 24 03:34:09 BXT-2 kernel: [ 1.118349] pci 0000:00:1f.1: reg 0x10: [mem 0x91416000-0x914160ff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.118467] pci 0000:00:1f.1: reg 0x20: [io 0xf040-0xf05f] >May 24 03:34:09 BXT-2 kernel: [ 1.122846] pci 0000:01:00.0: [10ec:5229] type 00 class 0xff0000 >May 24 03:34:09 BXT-2 kernel: [ 1.122894] pci 0000:01:00.0: reg 0x10: [mem 0x91300000-0x91300fff] >May 24 03:34:09 BXT-2 kernel: [ 1.123058] pci 0000:01:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug >May 24 03:34:09 BXT-2 kernel: [ 1.123268] pci 0000:01:00.0: supports D1 D2 >May 24 03:34:09 BXT-2 kernel: [ 1.123274] pci 0000:01:00.0: PME# supported from D1 D2 D3hot >May 24 03:34:09 BXT-2 kernel: [ 1.123659] pci 0000:01:00.0: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.124136] pci 0000:00:13.0: PCI bridge to [bus 01] >May 24 03:34:09 BXT-2 kernel: [ 1.124152] pci 0000:00:13.0: bridge window [mem 0x91300000-0x913fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.124496] pci 0000:02:00.0: [8086:24fb] type 00 class 0x028000 >May 24 03:34:09 BXT-2 kernel: [ 1.124573] pci 0000:02:00.0: reg 0x10: [mem 0x91200000-0x91201fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.124683] pci 0000:02:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug >May 24 03:34:09 BXT-2 kernel: [ 1.124939] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.125359] pci 0000:02:00.0: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.125784] pci 0000:00:13.1: PCI bridge to [bus 02] >May 24 03:34:09 BXT-2 kernel: [ 1.125799] pci 0000:00:13.1: bridge window [mem 0x91200000-0x912fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.126148] pci 0000:03:00.0: [10ec:8168] type 00 class 0x020000 >May 24 03:34:09 BXT-2 kernel: [ 1.126200] pci 0000:03:00.0: reg 0x10: [io 0xe000-0xe0ff] >May 24 03:34:09 BXT-2 kernel: [ 1.126256] pci 0000:03:00.0: reg 0x18: [mem 0x91104000-0x91104fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.126298] pci 0000:03:00.0: reg 0x20: [mem 0x91100000-0x91103fff 64bit] >May 24 03:34:09 BXT-2 kernel: [ 1.126333] pci 0000:03:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug >May 24 03:34:09 BXT-2 kernel: [ 1.126590] pci 0000:03:00.0: supports D1 D2 >May 24 03:34:09 BXT-2 kernel: [ 1.126595] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold >May 24 03:34:09 BXT-2 kernel: [ 1.127052] pci 0000:03:00.0: System wakeup disabled by ACPI >May 24 03:34:09 BXT-2 kernel: [ 1.127482] pci 0000:00:13.2: PCI bridge to [bus 03] >May 24 03:34:09 BXT-2 kernel: [ 1.127493] pci 0000:00:13.2: bridge window [io 0xe000-0xefff] >May 24 03:34:09 BXT-2 kernel: [ 1.127502] pci 0000:00:13.2: bridge window [mem 0x91100000-0x911fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.127562] pci_bus 0000:00: on NUMA node 0 >May 24 03:34:09 BXT-2 kernel: [ 1.140362] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.141946] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.143559] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.145133] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.146726] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.148291] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.149876] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.151457] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 03:34:09 BXT-2 kernel: [ 1.197330] ACPI: Enabled 1 GPEs in block 00 to 7F >May 24 03:34:09 BXT-2 kernel: [ 1.198452] ACPI : EC: interrupt unblocked >May 24 03:34:09 BXT-2 kernel: [ 1.198501] ACPI : EC: event unblocked >May 24 03:34:09 BXT-2 kernel: [ 1.198546] ACPI: \_SB_.PCI0.SBRG.H_EC: GPE=0x40, EC_CMD/EC_SC=0x66, EC_DATA=0x62 >May 24 03:34:09 BXT-2 kernel: [ 1.198565] ACPI: \_SB_.PCI0.SBRG.H_EC: Used as boot DSDT EC to handle transactions and events >May 24 03:34:09 BXT-2 kernel: [ 1.199540] pci 0000:00:02.0: vgaarb: setting as boot VGA device >May 24 03:34:09 BXT-2 kernel: [ 1.199550] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none >May 24 03:34:09 BXT-2 kernel: [ 1.199582] pci 0000:00:02.0: vgaarb: bridge control possible >May 24 03:34:09 BXT-2 kernel: [ 1.199587] vgaarb: loaded >May 24 03:34:09 BXT-2 kernel: [ 1.201132] SCSI subsystem initialized >May 24 03:34:09 BXT-2 kernel: [ 1.201629] libata version 3.00 loaded. >May 24 03:34:09 BXT-2 kernel: [ 1.201950] ACPI: bus type USB registered >May 24 03:34:09 BXT-2 kernel: [ 1.202264] usbcore: registered new interface driver usbfs >May 24 03:34:09 BXT-2 kernel: [ 1.202392] usbcore: registered new interface driver hub >May 24 03:34:09 BXT-2 kernel: [ 1.202578] usbcore: registered new device driver usb >May 24 03:34:09 BXT-2 kernel: [ 1.203556] Registered efivars operations >May 24 03:34:09 BXT-2 kernel: [ 1.231571] Advanced Linux Sound Architecture Driver Initialized. >May 24 03:34:09 BXT-2 kernel: [ 1.231691] PCI: Using ACPI for IRQ routing >May 24 03:34:09 BXT-2 kernel: [ 1.264507] PCI: pci_cache_line_size set to 64 bytes >May 24 03:34:09 BXT-2 kernel: [ 1.264696] e820: reserve RAM buffer [mem 0x0003f000-0x0003ffff] >May 24 03:34:09 BXT-2 kernel: [ 1.264724] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff] >May 24 03:34:09 BXT-2 kernel: [ 1.264739] e820: reserve RAM buffer [mem 0x77717000-0x77ffffff] >May 24 03:34:09 BXT-2 kernel: [ 1.264753] e820: reserve RAM buffer [mem 0x79fc6000-0x7bffffff] >May 24 03:34:09 BXT-2 kernel: [ 1.264768] e820: reserve RAM buffer [mem 0x7a9df000-0x7bffffff] >May 24 03:34:09 BXT-2 kernel: [ 1.264782] e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff] >May 24 03:34:09 BXT-2 kernel: [ 1.266717] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 >May 24 03:34:09 BXT-2 kernel: [ 1.266756] hpet0: 8 comparators, 64-bit 19.200000 MHz counter >May 24 03:34:09 BXT-2 kernel: [ 1.269989] clocksource: Switched to clocksource hpet >May 24 03:34:09 BXT-2 kernel: [ 1.469870] pnp: PnP ACPI init >May 24 03:34:09 BXT-2 kernel: [ 1.477066] system 00:00: [io 0x0a00-0x0a1f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.477094] system 00:00: [io 0x0a20-0x0a2f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.477110] system 00:00: [io 0x0a30-0x0a3f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.477125] system 00:00: [io 0x0a40-0x0a4f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.477139] system 00:00: [io 0x0a50-0x0a5f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.477155] system 00:00: [io 0x0a60-0x0a6f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.477202] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) >May 24 03:34:09 BXT-2 kernel: [ 1.481432] pnp 00:01: [dma 0 disabled] >May 24 03:34:09 BXT-2 kernel: [ 1.481766] pnp 00:01: Plug and Play ACPI device, IDs ITE8708 (active) >May 24 03:34:09 BXT-2 kernel: [ 1.482433] system 00:02: [io 0x0680-0x069f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.482450] system 00:02: [io 0x0400-0x047f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.482465] system 00:02: [io 0x0500-0x05fe] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.482480] system 00:02: [io 0x0600-0x061f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.482496] system 00:02: [io 0x164e-0x164f] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.482512] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active) >May 24 03:34:09 BXT-2 kernel: [ 1.489437] system 00:03: [mem 0xe0000000-0xefffffff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489455] system 00:03: [mem 0xfea00000-0xfeafffff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489470] system 00:03: [mem 0xfed01000-0xfed01fff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489485] system 00:03: [mem 0xfed03000-0xfed03fff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489499] system 00:03: [mem 0xfed06000-0xfed06fff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489514] system 00:03: [mem 0xfed08000-0xfed09fff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489529] system 00:03: [mem 0xfed80000-0xfedbffff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489551] system 00:03: [mem 0xfed1c000-0xfed1cfff] has been reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489582] system 00:03: [mem 0xfee00000-0xfeefffff] could not be reserved >May 24 03:34:09 BXT-2 kernel: [ 1.489601] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) >May 24 03:34:09 BXT-2 kernel: [ 1.492651] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) >May 24 03:34:09 BXT-2 kernel: [ 1.496180] pnp: PnP ACPI: found 5 devices >May 24 03:34:09 BXT-2 kernel: [ 1.529852] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns >May 24 03:34:09 BXT-2 kernel: [ 1.529926] pci 0000:00:13.0: PCI bridge to [bus 01] >May 24 03:34:09 BXT-2 kernel: [ 1.529940] pci 0000:00:13.0: bridge window [mem 0x91300000-0x913fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.529959] pci 0000:00:13.1: PCI bridge to [bus 02] >May 24 03:34:09 BXT-2 kernel: [ 1.529970] pci 0000:00:13.1: bridge window [mem 0x91200000-0x912fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.530041] pci 0000:00:13.2: PCI bridge to [bus 03] >May 24 03:34:09 BXT-2 kernel: [ 1.530049] pci 0000:00:13.2: bridge window [io 0xe000-0xefff] >May 24 03:34:09 BXT-2 kernel: [ 1.530060] pci 0000:00:13.2: bridge window [mem 0x91100000-0x911fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.530080] pci_bus 0000:00: resource 4 [io 0x0070-0x0077] >May 24 03:34:09 BXT-2 kernel: [ 1.530085] pci_bus 0000:00: resource 5 [io 0x0000-0x006f window] >May 24 03:34:09 BXT-2 kernel: [ 1.530090] pci_bus 0000:00: resource 6 [io 0x0078-0x0cf7 window] >May 24 03:34:09 BXT-2 kernel: [ 1.530095] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.530100] pci_bus 0000:00: resource 8 [mem 0x7c000001-0x7fffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.530105] pci_bus 0000:00: resource 9 [mem 0x7b800001-0x7bffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.530111] pci_bus 0000:00: resource 10 [mem 0x80000000-0xcfffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.530116] pci_bus 0000:00: resource 11 [mem 0xe0000000-0xefffffff window] >May 24 03:34:09 BXT-2 kernel: [ 1.530122] pci_bus 0000:01: resource 1 [mem 0x91300000-0x913fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.530127] pci_bus 0000:02: resource 1 [mem 0x91200000-0x912fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.530132] pci_bus 0000:03: resource 0 [io 0xe000-0xefff] >May 24 03:34:09 BXT-2 kernel: [ 1.530137] pci_bus 0000:03: resource 1 [mem 0x91100000-0x911fffff] >May 24 03:34:09 BXT-2 kernel: [ 1.532156] NET: Registered protocol family 2 >May 24 03:34:09 BXT-2 kernel: [ 1.533632] TCP established hash table entries: 131072 (order: 8, 1048576 bytes) >May 24 03:34:09 BXT-2 kernel: [ 1.534345] TCP bind hash table entries: 65536 (order: 10, 4194304 bytes) >May 24 03:34:09 BXT-2 kernel: [ 1.544953] TCP: Hash tables configured (established 131072 bind 65536) >May 24 03:34:09 BXT-2 kernel: [ 1.545642] UDP hash table entries: 8192 (order: 8, 1310720 bytes) >May 24 03:34:09 BXT-2 kernel: [ 1.548779] UDP-Lite hash table entries: 8192 (order: 8, 1310720 bytes) >May 24 03:34:09 BXT-2 kernel: [ 1.552196] NET: Registered protocol family 1 >May 24 03:34:09 BXT-2 kernel: [ 1.552273] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] >May 24 03:34:09 BXT-2 kernel: [ 1.557283] PCI: CLS 0 bytes, default 64 >May 24 03:34:09 BXT-2 kernel: [ 1.558106] Unpacking initramfs... >May 24 03:34:09 BXT-2 kernel: [ 2.038519] Freeing initrd memory: 11256K >May 24 03:34:09 BXT-2 kernel: [ 2.038757] DMAR: No ATSR found >May 24 03:34:09 BXT-2 kernel: [ 2.040509] DMAR: dmar0: Using Queued invalidation >May 24 03:34:09 BXT-2 kernel: [ 2.040608] DMAR: dmar1: Using Queued invalidation >May 24 03:34:09 BXT-2 kernel: [ 2.040779] DMAR: Setting RMRR: >May 24 03:34:09 BXT-2 kernel: [ 2.041541] DMAR: Setting identity map for device 0000:00:02.0 [0x7b800000 - 0x7fffffff] >May 24 03:34:09 BXT-2 kernel: [ 2.042106] DMAR: Setting identity map for device 0000:00:15.0 [0x797d4000 - 0x797f3fff] >May 24 03:34:09 BXT-2 kernel: [ 2.042136] DMAR: Prepare 0-16MiB unity mapping for LPC >May 24 03:34:09 BXT-2 kernel: [ 2.042660] DMAR: Setting identity map for device 0000:00:1f.0 [0x0 - 0xffffff] >May 24 03:34:09 BXT-2 kernel: [ 2.042757] DMAR: Intel(R) Virtualization Technology for Directed I/O >May 24 03:34:09 BXT-2 kernel: [ 2.043560] iommu: Adding device 0000:00:00.0 to group 0 >May 24 03:34:09 BXT-2 kernel: [ 2.043698] iommu: Adding device 0000:00:02.0 to group 1 >May 24 03:34:09 BXT-2 kernel: [ 2.043822] iommu: Adding device 0000:00:0e.0 to group 2 >May 24 03:34:09 BXT-2 kernel: [ 2.044027] iommu: Adding device 0000:00:0f.0 to group 3 >May 24 03:34:09 BXT-2 kernel: [ 2.044153] iommu: Adding device 0000:00:12.0 to group 4 >May 24 03:34:09 BXT-2 kernel: [ 2.044383] iommu: Adding device 0000:00:13.0 to group 5 >May 24 03:34:09 BXT-2 kernel: [ 2.044486] iommu: Adding device 0000:00:13.1 to group 5 >May 24 03:34:09 BXT-2 kernel: [ 2.044598] iommu: Adding device 0000:00:13.2 to group 5 >May 24 03:34:09 BXT-2 kernel: [ 2.044749] iommu: Adding device 0000:00:15.0 to group 6 >May 24 03:34:09 BXT-2 kernel: [ 2.044900] iommu: Adding device 0000:00:16.0 to group 7 >May 24 03:34:09 BXT-2 kernel: [ 2.045106] iommu: Adding device 0000:00:18.0 to group 8 >May 24 03:34:09 BXT-2 kernel: [ 2.045309] iommu: Adding device 0000:00:19.0 to group 9 >May 24 03:34:09 BXT-2 kernel: [ 2.045401] iommu: Adding device 0000:00:19.1 to group 9 >May 24 03:34:09 BXT-2 kernel: [ 2.045492] iommu: Adding device 0000:00:19.2 to group 9 >May 24 03:34:09 BXT-2 kernel: [ 2.045644] iommu: Adding device 0000:00:1a.0 to group 10 >May 24 03:34:09 BXT-2 kernel: [ 2.045774] iommu: Adding device 0000:00:1c.0 to group 11 >May 24 03:34:09 BXT-2 kernel: [ 2.045950] iommu: Adding device 0000:00:1f.0 to group 12 >May 24 03:34:09 BXT-2 kernel: [ 2.046098] iommu: Adding device 0000:00:1f.1 to group 12 >May 24 03:34:09 BXT-2 kernel: [ 2.046166] iommu: Adding device 0000:01:00.0 to group 5 >May 24 03:34:09 BXT-2 kernel: [ 2.046232] iommu: Adding device 0000:02:00.0 to group 5 >May 24 03:34:09 BXT-2 kernel: [ 2.046312] iommu: Adding device 0000:03:00.0 to group 5 >May 24 03:34:09 BXT-2 kernel: [ 2.072794] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer >May 24 03:34:09 BXT-2 kernel: [ 2.072802] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules >May 24 03:34:09 BXT-2 kernel: [ 2.072806] RAPL PMU: hw unit of domain package 2^-14 Joules >May 24 03:34:09 BXT-2 kernel: [ 2.072810] RAPL PMU: hw unit of domain dram 2^-14 Joules >May 24 03:34:09 BXT-2 kernel: [ 2.072813] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules >May 24 03:34:09 BXT-2 kernel: [ 2.072826] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x159647815e3, max_idle_ns: 440795269835 ns >May 24 03:34:09 BXT-2 kernel: [ 2.072900] clocksource: Switched to clocksource tsc >May 24 03:34:09 BXT-2 kernel: [ 2.084151] workingset: timestamp_bits=46 max_order=22 bucket_order=0 >May 24 03:34:09 BXT-2 kernel: [ 2.125466] ntfs: driver 2.1.32 [Flags: R/O]. >May 24 03:34:09 BXT-2 kernel: [ 2.156066] NET: Registered protocol family 38 >May 24 03:34:09 BXT-2 kernel: [ 2.156542] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250) >May 24 03:34:09 BXT-2 kernel: [ 2.156562] io scheduler noop registered >May 24 03:34:09 BXT-2 kernel: [ 2.157191] io scheduler cfq registered (default) >May 24 03:34:09 BXT-2 kernel: [ 2.157197] io scheduler mq-deadline registered >May 24 03:34:09 BXT-2 kernel: [ 2.157201] io scheduler kyber registered >May 24 03:34:09 BXT-2 kernel: [ 2.157205] start plist test >May 24 03:34:09 BXT-2 kernel: [ 2.160559] end plist test >May 24 03:34:09 BXT-2 kernel: [ 2.172346] pcieport 0000:00:13.0: Signaling PME with IRQ 367 >May 24 03:34:09 BXT-2 kernel: [ 2.172509] pcieport 0000:00:13.1: Signaling PME with IRQ 368 >May 24 03:34:09 BXT-2 kernel: [ 2.172688] pcieport 0000:00:13.2: Signaling PME with IRQ 369 >May 24 03:34:09 BXT-2 kernel: [ 2.173909] uvesafb: failed to execute /sbin/v86d >May 24 03:34:09 BXT-2 kernel: [ 2.173960] uvesafb: make sure that the v86d helper is installed and executable >May 24 03:34:09 BXT-2 kernel: [ 2.174039] uvesafb: Getting VBE info block failed (eax=0x4f00, err=-2) >May 24 03:34:09 BXT-2 kernel: [ 2.174087] uvesafb: vbe_init() failed with -22 >May 24 03:34:09 BXT-2 kernel: [ 2.174177] uvesafb: probe of uvesafb.0 failed with error -22 >May 24 03:34:09 BXT-2 kernel: [ 2.174360] intel_idle: does not run on family 6 model 92 >May 24 03:34:09 BXT-2 kernel: [ 2.175304] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 >May 24 03:34:09 BXT-2 kernel: [ 2.175542] ACPI: Power Button [PWRB] >May 24 03:34:09 BXT-2 kernel: [ 2.176041] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input1 >May 24 03:34:09 BXT-2 kernel: [ 2.176149] ACPI: Sleep Button [SLPB] >May 24 03:34:09 BXT-2 kernel: [ 2.176612] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 >May 24 03:34:09 BXT-2 kernel: [ 2.176701] ACPI: Power Button [PWRF] >May 24 03:34:09 BXT-2 kernel: [ 2.222413] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). >May 24 03:34:09 BXT-2 kernel: [ 2.239190] thermal LNXTHERM:00: registered as thermal_zone0 >May 24 03:34:09 BXT-2 kernel: [ 2.239196] ACPI: Thermal Zone [TZ01] (64 C) >May 24 03:34:09 BXT-2 kernel: [ 2.239642] GHES: HEST is not enabled! >May 24 03:34:09 BXT-2 kernel: [ 2.240269] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled >May 24 03:34:09 BXT-2 kernel: [ 2.246154] Non-volatile memory driver v1.3 >May 24 03:34:09 BXT-2 kernel: [ 2.246854] Linux agpgart interface v0.103 >May 24 03:34:09 BXT-2 kernel: [ 2.251466] loop: module loaded >May 24 03:34:09 BXT-2 kernel: [ 2.253308] ahci 0000:00:12.0: version 3.0 >May 24 03:34:09 BXT-2 kernel: [ 2.266529] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode >May 24 03:34:09 BXT-2 kernel: [ 2.266540] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst >May 24 03:34:09 BXT-2 kernel: [ 2.271844] scsi host0: ahci >May 24 03:34:09 BXT-2 kernel: [ 2.274265] scsi host1: ahci >May 24 03:34:09 BXT-2 kernel: [ 2.274895] ata1: SATA max UDMA/133 abar m2048@0x91425000 port 0x91425100 irq 370 >May 24 03:34:09 BXT-2 kernel: [ 2.274902] ata2: SATA max UDMA/133 abar m2048@0x91425000 port 0x91425180 irq 370 >May 24 03:34:09 BXT-2 kernel: [ 2.275509] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver >May 24 03:34:09 BXT-2 kernel: [ 2.275553] ehci-pci: EHCI PCI platform driver >May 24 03:34:09 BXT-2 kernel: [ 2.275662] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver >May 24 03:34:10 BXT-2 kernel: [ 2.275687] ohci-pci: OHCI PCI platform driver >May 24 03:34:10 BXT-2 kernel: [ 2.275809] uhci_hcd: USB Universal Host Controller Interface driver >May 24 03:34:10 BXT-2 kernel: [ 2.278860] xhci_hcd 0000:00:15.0: xHCI Host Controller >May 24 03:34:10 BXT-2 kernel: [ 2.279058] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1 >May 24 03:34:10 BXT-2 kernel: [ 2.280759] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x01109810 >May 24 03:34:10 BXT-2 kernel: [ 2.280777] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported >May 24 03:34:10 BXT-2 kernel: [ 2.281952] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 >May 24 03:34:10 BXT-2 kernel: [ 2.281964] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 >May 24 03:34:10 BXT-2 kernel: [ 2.281970] usb usb1: Product: xHCI Host Controller >May 24 03:34:10 BXT-2 kernel: [ 2.281999] usb usb1: Manufacturer: Linux 4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ xhci-hcd >May 24 03:34:10 BXT-2 kernel: [ 2.282004] usb usb1: SerialNumber: 0000:00:15.0 >May 24 03:34:10 BXT-2 kernel: [ 2.284254] hub 1-0:1.0: USB hub found >May 24 03:34:10 BXT-2 kernel: [ 2.284488] hub 1-0:1.0: 8 ports detected >May 24 03:34:10 BXT-2 kernel: [ 2.299726] xhci_hcd 0000:00:15.0: xHCI Host Controller >May 24 03:34:10 BXT-2 kernel: [ 2.299770] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2 >May 24 03:34:10 BXT-2 kernel: [ 2.300493] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003 >May 24 03:34:10 BXT-2 kernel: [ 2.300503] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 >May 24 03:34:10 BXT-2 kernel: [ 2.300508] usb usb2: Product: xHCI Host Controller >May 24 03:34:10 BXT-2 kernel: [ 2.300513] usb usb2: Manufacturer: Linux 4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ xhci-hcd >May 24 03:34:10 BXT-2 kernel: [ 2.300518] usb usb2: SerialNumber: 0000:00:15.0 >May 24 03:34:10 BXT-2 kernel: [ 2.302665] hub 2-0:1.0: USB hub found >May 24 03:34:10 BXT-2 kernel: [ 2.302877] hub 2-0:1.0: 7 ports detected >May 24 03:34:10 BXT-2 kernel: [ 2.316447] usbcore: registered new interface driver usb-storage >May 24 03:34:10 BXT-2 kernel: [ 2.317101] i8042: PNP: No PS/2 controller found. >May 24 03:34:10 BXT-2 kernel: [ 2.317105] i8042: Probing ports directly. >May 24 03:34:10 BXT-2 kernel: [ 2.333218] serio: i8042 KBD port at 0x60,0x64 irq 1 >May 24 03:34:10 BXT-2 kernel: [ 2.333967] serio: i8042 AUX port at 0x60,0x64 irq 12 >May 24 03:34:10 BXT-2 kernel: [ 2.335358] mousedev: PS/2 mouse device common for all mice >May 24 03:34:10 BXT-2 kernel: [ 2.338842] rtc_cmos 00:04: RTC can wake from S4 >May 24 03:34:10 BXT-2 kernel: [ 2.340321] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0 >May 24 03:34:10 BXT-2 kernel: [ 2.340482] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs >May 24 03:34:10 BXT-2 kernel: [ 2.342164] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0) >May 24 03:34:10 BXT-2 kernel: [ 2.343493] device-mapper: uevent: version 1.0.3 >May 24 03:34:10 BXT-2 kernel: [ 2.344851] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com >May 24 03:34:10 BXT-2 kernel: [ 2.344866] intel_pstate: Intel P-state driver initializing >May 24 03:34:10 BXT-2 kernel: [ 2.346689] random: fast init done >May 24 03:34:10 BXT-2 kernel: [ 2.353773] input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 >May 24 03:34:10 BXT-2 kernel: [ 2.354756] EFI Variables Facility v0.08 2004-May-17 >May 24 03:34:10 BXT-2 kernel: [ 2.392766] hidraw: raw HID events driver (C) Jiri Kosina >May 24 03:34:10 BXT-2 kernel: [ 2.393555] usbcore: registered new interface driver usbhid >May 24 03:34:10 BXT-2 kernel: [ 2.393558] usbhid: USB HID core driver >May 24 03:34:10 BXT-2 kernel: [ 2.394222] intel_rapl: Found RAPL domain package >May 24 03:34:10 BXT-2 kernel: [ 2.394229] intel_rapl: Found RAPL domain core >May 24 03:34:10 BXT-2 kernel: [ 2.394234] intel_rapl: Found RAPL domain uncore >May 24 03:34:10 BXT-2 kernel: [ 2.394238] intel_rapl: Found RAPL domain dram >May 24 03:34:10 BXT-2 kernel: [ 2.397658] Initializing XFRM netlink socket >May 24 03:34:10 BXT-2 kernel: [ 2.399268] NET: Registered protocol family 10 >May 24 03:34:10 BXT-2 kernel: [ 2.401943] Segment Routing with IPv6 >May 24 03:34:10 BXT-2 kernel: [ 2.402035] mip6: Mobile IPv6 >May 24 03:34:10 BXT-2 kernel: [ 2.402060] NET: Registered protocol family 17 >May 24 03:34:10 BXT-2 kernel: [ 2.402086] NET: Registered protocol family 15 >May 24 03:34:10 BXT-2 kernel: [ 2.404230] SSE version of gcm_enc/dec engaged. >May 24 03:34:10 BXT-2 kernel: [ 2.483291] alg: No test for pcbc(aes) (pcbc-aes-aesni) >May 24 03:34:10 BXT-2 kernel: [ 2.485813] registered taskstats version 1 >May 24 03:34:10 BXT-2 kernel: [ 2.492850] Btrfs loaded, crc32c=crc32c-generic >May 24 03:34:10 BXT-2 kernel: [ 2.498153] rtc_cmos 00:04: setting system clock to 2017-05-24 08:34:05 UTC (1495614845) >May 24 03:34:10 BXT-2 kernel: [ 2.499212] PM: Checking hibernation image partition /dev/sda3 >May 24 03:34:10 BXT-2 kernel: [ 2.584192] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:34:10 BXT-2 kernel: [ 2.665212] usb 1-8: new full-speed USB device number 2 using xhci_hcd >May 24 03:34:10 BXT-2 kernel: [ 2.747584] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:34:10 BXT-2 kernel: [ 2.763034] ata1.00: ATA-9: INTEL SSDSC2BW080A4, DC22, max UDMA/133 >May 24 03:34:10 BXT-2 kernel: [ 2.763046] ata1.00: 156301488 sectors, multi 16: LBA48 NCQ (depth 31/32), AA >May 24 03:34:10 BXT-2 kernel: [ 2.788902] ata1.00: configured for UDMA/133 >May 24 03:34:10 BXT-2 kernel: [ 2.793233] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSC2BW08 DC22 PQ: 0 ANSI: 5 >May 24 03:34:10 BXT-2 kernel: [ 2.798744] sd 0:0:0:0: Attached scsi generic sg0 type 0 >May 24 03:34:10 BXT-2 kernel: [ 2.799365] sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB) >May 24 03:34:10 BXT-2 kernel: [ 2.799647] sd 0:0:0:0: [sda] Write Protect is off >May 24 03:34:10 BXT-2 kernel: [ 2.799659] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 >May 24 03:34:10 BXT-2 kernel: [ 2.800094] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA >May 24 03:34:10 BXT-2 kernel: [ 2.805039] sda: sda1 sda2 sda3 >May 24 03:34:10 BXT-2 kernel: [ 2.808513] sd 0:0:0:0: [sda] Attached SCSI disk >May 24 03:34:10 BXT-2 kernel: [ 2.808651] PM: Hibernation image partition 8:3 present >May 24 03:34:10 BXT-2 kernel: [ 2.808657] PM: Looking for hibernation image. >May 24 03:34:10 BXT-2 kernel: [ 2.810069] PM: Image not found (code -22) >May 24 03:34:10 BXT-2 kernel: [ 2.810076] PM: Hibernation image not present or could not be loaded. >May 24 03:34:10 BXT-2 kernel: [ 2.810206] ALSA device list: >May 24 03:34:10 BXT-2 kernel: [ 2.810209] No soundcards found. >May 24 03:34:10 BXT-2 kernel: [ 2.814446] Freeing unused kernel memory: 1200K >May 24 03:34:10 BXT-2 kernel: [ 2.814453] Write protecting the kernel read-only data: 14336k >May 24 03:34:10 BXT-2 kernel: [ 2.817166] Freeing unused kernel memory: 1556K >May 24 03:34:10 BXT-2 kernel: [ 2.820506] Freeing unused kernel memory: 652K >May 24 03:34:10 BXT-2 kernel: [ 2.836337] usb 1-8: New USB device found, idVendor=8087, idProduct=0aa7 >May 24 03:34:10 BXT-2 kernel: [ 2.836351] usb 1-8: New USB device strings: Mfr=0, Product=0, SerialNumber=0 >May 24 03:34:10 BXT-2 kernel: [ 3.198486] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded >May 24 03:34:10 BXT-2 kernel: [ 3.205792] r8169 0000:03:00.0 eth0: RTL8168h/8111h at 0xffffc900000a1000, f4:4d:30:68:3e:74, XID 14100800 IRQ 372 >May 24 03:34:10 BXT-2 kernel: [ 3.205799] r8169 0000:03:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko] >May 24 03:34:10 BXT-2 kernel: [ 3.221309] sdhci: Secure Digital Host Controller Interface driver >May 24 03:34:10 BXT-2 kernel: [ 3.221314] sdhci: Copyright(c) Pierre Ossman >May 24 03:34:10 BXT-2 kernel: [ 3.229138] [drm:i915_driver_load [i915]] No PCH found. >May 24 03:34:10 BXT-2 kernel: [ 3.229200] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09 >May 24 03:34:10 BXT-2 kernel: [ 3.232936] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a85 rev=0x0b >May 24 03:34:10 BXT-2 kernel: [ 3.232989] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no >May 24 03:34:10 BXT-2 kernel: [ 3.233098] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233147] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no >May 24 03:34:10 BXT-2 kernel: [ 3.233196] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233348] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233397] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233445] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233494] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233543] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233591] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233640] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233689] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233738] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233786] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233835] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no >May 24 03:34:10 BXT-2 kernel: [ 3.233884] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233933] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes >May 24 03:34:10 BXT-2 kernel: [ 3.233981] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no >May 24 03:34:10 BXT-2 kernel: [ 3.234061] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no >May 24 03:34:10 BXT-2 kernel: [ 3.234110] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes >May 24 03:34:10 BXT-2 kernel: [ 3.234159] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no >May 24 03:34:10 BXT-2 kernel: [ 3.234207] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no >May 24 03:34:10 BXT-2 kernel: [ 3.234256] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no >May 24 03:34:10 BXT-2 kernel: [ 3.234305] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no >May 24 03:34:10 BXT-2 kernel: [ 3.234353] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes >May 24 03:34:10 BXT-2 kernel: [ 3.234402] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no >May 24 03:34:10 BXT-2 kernel: [ 3.234451] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes >May 24 03:34:10 BXT-2 kernel: [ 3.234499] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes >May 24 03:34:10 BXT-2 kernel: [ 3.234548] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no >May 24 03:34:10 BXT-2 kernel: [ 3.234596] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no >May 24 03:34:10 BXT-2 kernel: [ 3.234645] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no >May 24 03:34:10 BXT-2 kernel: [ 3.234695] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no >May 24 03:34:10 BXT-2 kernel: [ 3.234743] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no >May 24 03:34:10 BXT-2 kernel: [ 3.234792] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no >May 24 03:34:10 BXT-2 kernel: [ 3.242211] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001 >May 24 03:34:10 BXT-2 kernel: [ 3.243577] [drm:intel_device_info_runtime_init [i915]] slice total: 1 >May 24 03:34:10 BXT-2 kernel: [ 3.243861] [drm:intel_device_info_runtime_init [i915]] subslice total: 2 >May 24 03:34:10 BXT-2 kernel: [ 3.244151] [drm:intel_device_info_runtime_init [i915]] subslice mask 0006 >May 24 03:34:10 BXT-2 kernel: [ 3.244376] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 2 >May 24 03:34:10 BXT-2 kernel: [ 3.244574] [drm:intel_device_info_runtime_init [i915]] EU total: 12 >May 24 03:34:10 BXT-2 kernel: [ 3.244772] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6 >May 24 03:34:10 BXT-2 kernel: [ 3.244969] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n >May 24 03:34:10 BXT-2 kernel: [ 3.245390] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y >May 24 03:34:10 BXT-2 kernel: [ 3.245701] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y >May 24 03:34:10 BXT-2 kernel: [ 3.245909] [drm:i915_driver_load [i915]] ppgtt mode: 3 >May 24 03:34:10 BXT-2 kernel: [ 3.246167] [drm:i915_driver_load [i915]] use GPU semaphores? no >May 24 03:34:10 BXT-2 kernel: [ 3.246737] [drm] Memory usable by graphics device = 4096M >May 24 03:34:10 BXT-2 kernel: [ 3.246813] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M >May 24 03:34:10 BXT-2 kernel: [ 3.247030] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M >May 24 03:34:10 BXT-2 kernel: [ 3.247301] [drm] VT-d active for gfx access >May 24 03:34:10 BXT-2 kernel: [ 3.247922] [drm] Replacing VGA console driver >May 24 03:34:10 BXT-2 kernel: [ 3.248179] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K >May 24 03:34:10 BXT-2 kernel: [ 3.248304] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 03:34:10 BXT-2 kernel: [ 3.249813] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:34:10 BXT-2 kernel: [ 3.249924] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:34:10 BXT-2 kernel: [ 3.249979] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:34:10 BXT-2 kernel: [ 3.250091] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:34:10 BXT-2 kernel: [ 3.252893] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params >May 24 03:34:10 BXT-2 kernel: [ 3.252913] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). >May 24 03:34:10 BXT-2 kernel: [ 3.252916] [drm] Driver supports precise vblank timestamp query. >May 24 03:34:10 BXT-2 kernel: [ 3.252975] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.253176] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON ", BDB version 207 >May 24 03:34:10 BXT-2 kernel: [ 3.253968] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 >May 24 03:34:10 BXT-2 kernel: [ 3.254025] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 >May 24 03:34:10 BXT-2 kernel: [ 3.254136] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19) >May 24 03:34:10 BXT-2 kernel: [ 3.257127] [drm:intel_bios_init [i915]] Panel type: 0 (VBT) >May 24 03:34:10 BXT-2 kernel: [ 3.257184] [drm:intel_bios_init [i915]] DRRS supported mode is static >May 24 03:34:10 BXT-2 kernel: [ 3.257252] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables: >May 24 03:34:10 BXT-2 kernel: [ 3.257262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 148350 1920 1960 2000 2040 1200 1204 1208 1212 0x8 0xa >May 24 03:34:10 BXT-2 kernel: [ 3.257319] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 1 >May 24 03:34:10 BXT-2 kernel: [ 3.257376] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping. >May 24 03:34:10 BXT-2 kernel: [ 3.257432] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38 >May 24 03:34:10 BXT-2 kernel: [ 3.257496] [drm:intel_bios_init [i915]] DRRS State Enabled:1 >May 24 03:34:10 BXT-2 kernel: [ 3.257555] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 >May 24 03:34:10 BXT-2 kernel: [ 3.257611] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.257667] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:0 DVI:0 EDP:0 CRT:0 >May 24 03:34:10 BXT-2 kernel: [ 3.257723] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.258341] [drm:intel_dsm_detect [i915]] no _DSM method for intel device >May 24 03:34:10 BXT-2 kernel: [ 3.258417] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:34:10 BXT-2 kernel: [ 3.258570] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:34:10 BXT-2 kernel: [ 3.258653] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.258723] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:34:10 BXT-2 kernel: [ 3.258773] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:34:10 BXT-2 kernel: [ 3.258825] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:34:10 BXT-2 kernel: [ 3.258888] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:34:10 BXT-2 kernel: [ 3.258941] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:34:10 BXT-2 kernel: [ 3.261600] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:34:10 BXT-2 kernel: [ 3.261726] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it >May 24 03:34:10 BXT-2 kernel: [ 3.261809] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin >May 24 03:34:10 BXT-2 kernel: [ 3.264021] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7) >May 24 03:34:10 BXT-2 kernel: [ 3.264314] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 03:34:10 BXT-2 kernel: [ 3.266458] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled >May 24 03:34:10 BXT-2 kernel: [ 3.266536] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.266607] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266656] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266705] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266754] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266803] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266852] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266901] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.266951] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec) >May 24 03:34:10 BXT-2 kernel: [ 3.267008] [drm:intel_modeset_init [i915]] 3 display pipes available. >May 24 03:34:10 BXT-2 kernel: [ 3.267808] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.268146] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.268203] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.268228] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem >May 24 03:34:10 BXT-2 kernel: [ 3.268687] [drm:intel_ddi_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it >May 24 03:34:10 BXT-2 kernel: [ 3.268745] [drm:intel_ddi_init [i915]] VBT says port B has lspcon >May 24 03:34:10 BXT-2 kernel: [ 3.268854] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B >May 24 03:34:10 BXT-2 kernel: [ 3.268993] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT) >May 24 03:34:10 BXT-2 kernel: [ 3.271963] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 0.0 >May 24 03:34:10 BXT-2 kernel: [ 3.272559] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.275091] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.276972] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.279107] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.281906] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.283032] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.284144] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.284785] [drm:drm_dp_i2c_do_msg] too many retries, giving up >May 24 03:34:10 BXT-2 kernel: [ 3.285758] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.287092] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.288211] r8169 0000:03:00.0 enp3s0: renamed from eth0 >May 24 03:34:10 BXT-2 kernel: [ 3.288318] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.289464] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.290593] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.291712] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.292826] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:34:10 BXT-2 kernel: [ 3.293479] [drm:drm_dp_i2c_do_msg] too many retries, giving up >May 24 03:34:10 BXT-2 kernel: [ 3.293488] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: (err -121) >May 24 03:34:10 BXT-2 kernel: [ 3.293564] [drm:lspcon_init [i915]] No LSPCON detected, found unknown >May 24 03:34:10 BXT-2 kernel: [ 3.293619] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon >May 24 03:34:10 BXT-2 kernel: [ 3.293699] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port B >May 24 03:34:10 BXT-2 kernel: [ 3.293825] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C >May 24 03:34:10 BXT-2 kernel: [ 3.293895] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT) >May 24 03:34:10 BXT-2 kernel: [ 3.294015] [drm:intel_dsi_init [i915]] >May 24 03:34:10 BXT-2 kernel: [ 3.294628] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x1 >May 24 03:34:10 BXT-2 kernel: [ 3.294694] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: enabled >May 24 03:34:10 BXT-2 kernel: [ 3.294762] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.294818] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:34:10 BXT-2 kernel: [ 3.294883] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.294939] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:34:10 BXT-2 kernel: [ 3.294999] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:34:10 BXT-2 kernel: [ 3.295099] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:34:10 BXT-2 kernel: [ 3.295220] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000001, on 1 >May 24 03:34:10 BXT-2 kernel: [ 3.295280] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.295337] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.295393] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:34:10 BXT-2 kernel: [ 3.295449] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:34:10 BXT-2 kernel: [ 3.295541] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: enabled, pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.295597] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.295654] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:34:10 BXT-2 kernel: [ 3.295710] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:34:10 BXT-2 kernel: [ 3.296171] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:34:10 BXT-2 kernel: [ 3.296391] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: enabled >May 24 03:34:10 BXT-2 kernel: [ 3.296989] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:34:10 BXT-2 kernel: [ 3.297072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.297128] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.297184] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:34:10 BXT-2 kernel: [ 3.297193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 109 270000 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.297249] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:34:10 BXT-2 kernel: [ 3.297255] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 109 270000 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.297312] [drm:intel_dump_pipe_config [i915]] crtc timings: 270000 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.297368] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 270000 >May 24 03:34:10 BXT-2 kernel: [ 3.297424] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.297481] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x07800438, enabled >May 24 03:34:10 BXT-2 kernel: [ 3.297537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.297595] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:34:10 BXT-2 kernel: [ 3.297651] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:34:10 BXT-2 kernel: [ 3.297708] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.297764] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.297820] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.297876] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.297938] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:34:10 BXT-2 kernel: [ 3.297994] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.298131] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.298187] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:34:10 BXT-2 kernel: [ 3.298194] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.298250] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:34:10 BXT-2 kernel: [ 3.298255] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.298312] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.298368] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:34:10 BXT-2 kernel: [ 3.298424] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.298480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:34:10 BXT-2 kernel: [ 3.298535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.298593] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.298649] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:34:10 BXT-2 kernel: [ 3.298705] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.298761] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.298817] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.298873] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.298934] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:34:10 BXT-2 kernel: [ 3.298990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.299067] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.299123] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:34:10 BXT-2 kernel: [ 3.299129] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.299185] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:34:10 BXT-2 kernel: [ 3.299190] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.299247] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.299302] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:34:10 BXT-2 kernel: [ 3.299358] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.299415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:34:10 BXT-2 kernel: [ 3.299471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.299529] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.299585] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:34:10 BXT-2 kernel: [ 3.299641] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.299698] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.299755] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.299943] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:34:10 BXT-2 kernel: [ 3.300133] [drm:skylake_get_initial_plane_config [i915]] pipe A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000 >May 24 03:34:10 BXT-2 kernel: [ 3.300197] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=7e9000 >May 24 03:34:10 BXT-2 kernel: [ 3.300373] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space >May 24 03:34:10 BXT-2 kernel: [ 3.300456] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.300884] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000] >May 24 03:34:10 BXT-2 kernel: [ 3.430637] [drm:i915_gem_context_init [i915]] logical context support initialized >May 24 03:34:10 BXT-2 kernel: [ 3.430903] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfffff000 >May 24 03:34:10 BXT-2 kernel: [ 3.434727] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:34:10 BXT-2 kernel: [ 3.434803] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:34:10 BXT-2 kernel: [ 3.434922] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:34:10 BXT-2 kernel: [ 3.435094] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:34:10 BXT-2 kernel: [ 3.435215] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:34:10 BXT-2 kernel: [ 3.435564] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping >May 24 03:34:10 BXT-2 kernel: [ 3.435617] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping >May 24 03:34:10 BXT-2 kernel: [ 3.435670] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping >May 24 03:34:10 BXT-2 kernel: [ 3.435723] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config >May 24 03:34:10 BXT-2 kernel: [ 3.435847] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:34:10 BXT-2 kernel: [ 3.438485] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1 >May 24 03:34:10 BXT-2 kernel: [ 3.439960] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2 >May 24 03:34:10 BXT-2 kernel: [ 3.440641] [drm] Initialized i915 1.6.0 20170515 for 0000:00:02.0 on minor 0 >May 24 03:34:10 BXT-2 kernel: [ 3.442127] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:34:10 BXT-2 kernel: [ 3.455059] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) >May 24 03:34:10 BXT-2 kernel: [ 3.461991] [drm:asle_work [i915]] bclp = 0x80000005 >May 24 03:34:10 BXT-2 kernel: [ 3.462104] [drm:asle_work [i915]] updating opregion backlight 5/255 >May 24 03:34:10 BXT-2 kernel: [ 3.463636] [drm:asle_work [i915]] bclp = 0x800000ff >May 24 03:34:10 BXT-2 kernel: [ 3.463698] [drm:asle_work [i915]] updating opregion backlight 255/255 >May 24 03:34:10 BXT-2 kernel: [ 3.464976] acpi device:10: registered as cooling_device5 >May 24 03:34:10 BXT-2 kernel: [ 3.465852] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input6 >May 24 03:34:10 BXT-2 kernel: [ 3.467415] [drm] DRM_I915_DEBUG enabled >May 24 03:34:10 BXT-2 kernel: [ 3.467420] [drm] DRM_I915_DEBUG_GEM enabled >May 24 03:34:10 BXT-2 kernel: [ 3.467509] [drm:drm_setup_crtcs] >May 24 03:34:10 BXT-2 kernel: [ 3.467532] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:34:10 BXT-2 kernel: [ 3.467639] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:34:10 BXT-2 kernel: [ 3.467642] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev b) >May 24 03:34:10 BXT-2 kernel: [ 3.467664] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] status updated from unknown to disconnected >May 24 03:34:10 BXT-2 kernel: [ 3.467868] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:34:10 BXT-2 kernel: [ 3.467878] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:34:10 BXT-2 kernel: [ 3.467952] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:34:10 BXT-2 kernel: [ 3.469137] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:34:10 BXT-2 kernel: [ 3.470074] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:34:10 BXT-2 kernel: [ 3.470133] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:34:10 BXT-2 kernel: [ 3.470190] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:34:10 BXT-2 kernel: [ 3.470245] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:34:10 BXT-2 kernel: [ 3.470768] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:34:10 BXT-2 kernel: [ 3.470825] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:34:10 BXT-2 kernel: [ 3.472328] mmc0: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit >May 24 03:34:10 BXT-2 kernel: [ 3.476394] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] status updated from unknown to connected >May 24 03:34:10 BXT-2 kernel: [ 3.476509] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:34:10 BXT-2 kernel: [ 3.476521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:34:10 BXT-2 kernel: [ 3.476528] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476533] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476538] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476543] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476549] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476554] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476559] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:34:10 BXT-2 kernel: [ 3.476564] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476569] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.476574] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:34:10 BXT-2 kernel: [ 3.476579] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:34:10 BXT-2 kernel: [ 3.476584] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:34:10 BXT-2 kernel: [ 3.476611] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:34:10 BXT-2 kernel: [ 3.476615] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:34:10 BXT-2 kernel: [ 3.476705] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:34:10 BXT-2 kernel: [ 3.476718] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:34:10 BXT-2 kernel: [ 3.476722] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:34:10 BXT-2 kernel: [ 3.476726] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:34:10 BXT-2 kernel: [ 3.476730] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config >May 24 03:34:10 BXT-2 kernel: [ 3.476749] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:34:10 BXT-2 kernel: [ 3.476825] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one >May 24 03:34:10 BXT-2 kernel: [ 3.479849] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00040000 >May 24 03:34:10 BXT-2 kernel: [ 3.480929] fbcon: inteldrmfb (fb0) is primary device >May 24 03:34:10 BXT-2 kernel: [ 3.482288] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:34:10 BXT-2 kernel: [ 3.482348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:34:10 BXT-2 kernel: [ 3.482406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:34:10 BXT-2 kernel: [ 3.482463] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:34:10 BXT-2 kernel: [ 3.482517] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:34:10 BXT-2 kernel: [ 3.482574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.482630] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:34:10 BXT-2 kernel: [ 3.482687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.482743] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:34:10 BXT-2 kernel: [ 3.482797] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.482851] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:34:10 BXT-2 kernel: [ 3.482861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.482915] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:34:10 BXT-2 kernel: [ 3.482920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.482975] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:34:10 BXT-2 kernel: [ 3.483061] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:34:10 BXT-2 kernel: [ 3.483135] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.483187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:34:10 BXT-2 kernel: [ 3.483239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:34:10 BXT-2 kernel: [ 3.483298] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:34:10 BXT-2 kernel: [ 3.483350] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:34:10 BXT-2 kernel: [ 3.483405] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.483459] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.483513] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.483567] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:34:10 BXT-2 kernel: [ 3.483624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.483686] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:34:10 BXT-2 kernel: [ 3.483739] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.483795] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:34:10 BXT-2 kernel: [ 3.484591] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.487677] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:34:10 BXT-2 kernel: [ 3.487830] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:34:10 BXT-2 kernel: [ 3.487907] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.490634] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:34:10 BXT-2 kernel: [ 3.490693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:34:10 BXT-2 kernel: [ 3.490748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:34:10 BXT-2 kernel: [ 3.490803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:34:10 BXT-2 kernel: [ 3.490859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:34:10 BXT-2 kernel: [ 3.490916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:34:10 BXT-2 kernel: [ 3.490973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:34:10 BXT-2 kernel: [ 3.491048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:34:10 BXT-2 kernel: [ 3.491103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:34:10 BXT-2 kernel: [ 3.491161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:34:10 BXT-2 kernel: [ 3.491223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:34:10 BXT-2 kernel: [ 3.491281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:34:10 BXT-2 kernel: [ 3.491372] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:34:10 BXT-2 kernel: [ 3.491428] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:34:10 BXT-2 kernel: [ 3.493339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:34:10 BXT-2 kernel: [ 3.493393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:34:10 BXT-2 kernel: [ 3.493453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:34:10 BXT-2 kernel: [ 3.494259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:34:10 BXT-2 kernel: [ 3.494312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:34:10 BXT-2 kernel: [ 3.495074] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:34:10 BXT-2 kernel: [ 3.495128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:34:10 BXT-2 kernel: [ 3.496201] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:34:10 BXT-2 kernel: [ 3.498336] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:34:10 BXT-2 kernel: [ 3.499628] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:34:10 BXT-2 kernel: [ 3.533535] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:34:10 BXT-2 kernel: [ 3.533623] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:34:10 BXT-2 kernel: [ 3.533816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:34:10 BXT-2 kernel: [ 3.534107] Console: switching to colour frame buffer device 240x67 >May 24 03:34:10 BXT-2 kernel: [ 3.563432] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device >May 24 03:34:10 BXT-2 kernel: [ 3.606106] mmc0: new HS400 MMC card at address 0001 >May 24 03:34:10 BXT-2 kernel: [ 3.614247] mmcblk0: mmc0:0001 DF4032 29.1 GiB >May 24 03:34:10 BXT-2 kernel: [ 3.615081] mmcblk0boot0: mmc0:0001 DF4032 partition 1 4.00 MiB >May 24 03:34:10 BXT-2 kernel: [ 3.615910] mmcblk0boot1: mmc0:0001 DF4032 partition 2 4.00 MiB >May 24 03:34:10 BXT-2 kernel: [ 3.616694] mmcblk0rpmb: mmc0:0001 DF4032 partition 3 4.00 MiB >May 24 03:34:10 BXT-2 kernel: [ 3.622573] mmcblk0: p1 p2 p3 p4 >May 24 03:34:10 BXT-2 kernel: [ 3.669068] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null) >May 24 03:34:10 BXT-2 kernel: [ 4.601798] EXT4-fs (sda2): re-mounted. Opts: (null) >May 24 03:34:10 BXT-2 kernel: [ 4.716450] [drm] RC6 on >May 24 03:34:10 BXT-2 kernel: [ 5.546933] [drm:asle_work [i915]] bclp = 0x800000ff >May 24 03:34:10 BXT-2 kernel: [ 5.546986] [drm:asle_work [i915]] updating opregion backlight 255/255 >May 24 03:34:10 BXT-2 kernel: [ 5.599151] random: crng init done >May 24 03:34:10 BXT-2 kernel: [ 5.638093] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) >May 24 03:34:10 BXT-2 kernel: [ 5.645578] lpc_ich 0000:00:1f.0: I/O space for ACPI uninitialized >May 24 03:34:10 BXT-2 kernel: [ 5.680608] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC283: line_outs=2 (0x1b/0x21/0x0/0x0/0x0) type:hp >May 24 03:34:10 BXT-2 kernel: [ 5.680615] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) >May 24 03:34:10 BXT-2 kernel: [ 5.680619] snd_hda_codec_realtek hdaudioC0D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0) >May 24 03:34:10 BXT-2 kernel: [ 5.680622] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 >May 24 03:34:10 BXT-2 kernel: [ 5.680625] snd_hda_codec_realtek hdaudioC0D0: dig-out=0x1e/0x0 >May 24 03:34:10 BXT-2 kernel: [ 5.680628] snd_hda_codec_realtek hdaudioC0D0: inputs: >May 24 03:34:10 BXT-2 kernel: [ 5.680633] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 >May 24 03:34:10 BXT-2 kernel: [ 5.680636] snd_hda_codec_realtek hdaudioC0D0: Internal Mic=0x12 >May 24 03:34:10 BXT-2 kernel: [ 5.753752] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:34:10 BXT-2 kernel: [ 5.753811] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:34:10 BXT-2 kernel: [ 5.753854] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:34:10 BXT-2 kernel: [ 5.753897] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:34:10 BXT-2 kernel: [ 5.753941] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:34:10 BXT-2 kernel: [ 5.753984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C >May 24 03:34:10 BXT-2 kernel: [ 5.754061] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:34:10 BXT-2 kernel: [ 5.754106] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:34:10 BXT-2 kernel: [ 5.754152] [drm:i915_audio_component_get_eld [i915]] Not valid for port D >May 24 03:34:10 BXT-2 kernel: [ 5.762444] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input7 >May 24 03:34:10 BXT-2 kernel: [ 5.764683] input: HDA Intel PCH Headphone Front as /devices/pci0000:00/0000:00:0e.0/sound/card0/input8 >May 24 03:34:10 BXT-2 kernel: [ 5.765920] input: HDA Intel PCH Front Headphone Surround as /devices/pci0000:00/0000:00:0e.0/sound/card0/input9 >May 24 03:34:10 BXT-2 kernel: [ 5.766662] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input10 >May 24 03:34:10 BXT-2 kernel: [ 5.767266] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input11 >May 24 03:34:10 BXT-2 kernel: [ 5.767854] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input12 >May 24 03:34:10 BXT-2 kernel: [ 5.768511] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input13 >May 24 03:34:10 BXT-2 kernel: [ 5.771448] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input14 >May 24 03:34:10 BXT-2 kernel: [ 5.934027] Adding 16642044k swap on /dev/sda3. Priority:-1 extents:1 across:16642044k SSFS >May 24 03:34:10 BXT-2 kernel: [ 6.300010] r8169 0000:03:00.0 enp3s0: link down >May 24 03:34:10 BXT-2 kernel: [ 6.300080] r8169 0000:03:00.0 enp3s0: link down >May 24 03:34:10 BXT-2 kernel: [ 6.300370] IPv6: ADDRCONF(NETDEV_UP): enp3s0: link is not ready >May 24 03:34:10 BXT-2 kernel: [ 7.158418] new mount options do not match the existing superblock, will be ignored >May 24 03:34:10 BXT-2 NetworkManager[793]: <info> [1495614850.4524] NetworkManager (version 1.2.4) is starting... >May 24 03:34:10 BXT-2 NetworkManager[793]: <info> [1495614850.4534] Read config: /etc/NetworkManager/NetworkManager.conf (etc: default-wifi-powersave-on.conf) >May 24 03:34:10 BXT-2 NetworkManager[793]: <info> [1495614850.4642] manager[0x55d183d1c1a0]: monitoring kernel firmware directory '/lib/firmware'. >May 24 03:34:10 BXT-2 NetworkManager[793]: <info> [1495614850.4644] monitoring ifupdown state file '/run/network/ifstate'. >May 24 03:34:10 BXT-2 NetworkManager[793]: <info> [1495614850.4715] dns-mgr[0x55d183d14940]: init: dns=dnsmasq, rc-manager=resolvconf, plugin=dnsmasq >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1109] init! >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1123] guessed connection type (enp3s0) = 802-3-ethernet >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1127] update_connection_setting_from_if_block: name:enp3s0, type:802-3-ethernet, id:Ifupdown (enp3s0), uuid: 23ba95ab-026a-2447-b6b9-e319d485a821 >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1184] addresses count: 1 >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1185] adding enp3s0 to connections >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1186] adding iface enp3s0 to eni_ifaces >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1187] autoconnect >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1188] management mode: unmanaged >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1213] devices added (path: /sys/devices/pci0000:00/0000:00:13.2/0000:03:00.0/net/enp3s0, iface: enp3s0) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1216] locking wired connection setting >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1218] devices added (path: /sys/devices/virtual/net/lo, iface: lo) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1219] device added (path: /sys/devices/virtual/net/lo, iface: lo): no ifupdown configuration found. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1238] end _init. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1240] settings: loaded plugin ifupdown: (C) 2008 Canonical Ltd. To report bugs please use the NetworkManager mailing list. (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-settings-plugin-ifupdown.so) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1241] settings: loaded plugin keyfile: (c) 2007 - 2015 Red Hat, Inc. To report bugs please use the NetworkManager mailing list. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1248] SettingsPlugin-Ofono: init! >May 24 03:34:11 BXT-2 NetworkManager[793]: <warn> [1495614851.1251] SettingsPlugin-Ofono: file doesn't exist: /var/lib/ofono >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1251] SettingsPlugin-Ofono: end _init. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1252] settings: loaded plugin ofono: (C) 2013-2016 Canonical Ltd. To report bugs please use the NetworkManager mailing list. (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-settings-plugin-ofono.so) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1253] (-2083321488) ... get_connections. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1254] (-2083321488) ... get_connections (managed=false): return empty list. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1272] SettingsPlugin-Ofono: (-2083321648) ... get_connections. >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1273] SettingsPlugin-Ofono: (-2083321648) connections count: 0 >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.1274] get unmanaged devices count: 1 >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4856] settings: hostname: using hostnamed >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4858] settings: hostname changed from (none) to "BXT-2" >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4863] Using DHCP client 'dhclient' >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4864] manager: WiFi enabled by radio killswitch; enabled by state file >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4865] manager: WWAN enabled by radio killswitch; enabled by state file >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4866] manager: Networking is enabled by state file >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4867] Loaded device plugin: NMVxlanFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4868] Loaded device plugin: NMVlanFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4869] Loaded device plugin: NMVethFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4870] Loaded device plugin: NMTunFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4871] Loaded device plugin: NMMacvlanFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4871] Loaded device plugin: NMIPTunnelFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4872] Loaded device plugin: NMInfinibandFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4873] Loaded device plugin: NMEthernetFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4874] Loaded device plugin: NMBridgeFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4875] Loaded device plugin: NMBondFactory (internal) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4903] Loaded device plugin: NMWwanFactory (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-wwan.so) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4917] Loaded device plugin: NMAtmManager (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-adsl.so) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.4928] Loaded device plugin: NMWifiFactory (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-wifi.so) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5107] Loaded device plugin: NMBluezManager (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-bluetooth.so) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5158] manager: (enp3s0): new Ethernet device (/org/freedesktop/NetworkManager/Devices/0) >May 24 03:34:11 BXT-2 NetworkManager[793]: nm_device_get_device_type: assertion 'NM_IS_DEVICE (self)' failed >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5180] device (lo): link connected >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5194] manager: (lo): new Generic device (/org/freedesktop/NetworkManager/Devices/1) >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5214] manager: startup complete >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5219] manager: NetworkManager state is now CONNECTED_GLOBAL >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5384] urfkill disappeared from the bus >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5430] ofono is now available >May 24 03:34:11 BXT-2 NetworkManager[793]: <info> [1495614851.5475] ModemManager available in the bus >May 24 03:34:11 BXT-2 NetworkManager[793]: <warn> [1495614851.5477] failed to enumerate oFono devices: GDBus.Error:org.freedesktop.DBus.Error.ServiceUnknown: The name org.ofono was not provided by any .service files >May 24 03:34:12 BXT-2 kernel: [ 9.730440] r8169 0000:03:00.0 enp3s0: link up >May 24 03:34:12 BXT-2 kernel: [ 9.730480] IPv6: ADDRCONF(NETDEV_CHANGE): enp3s0: link becomes ready >May 24 03:34:12 BXT-2 NetworkManager[793]: <info> [1495614852.7338] device (enp3s0): link connected >May 24 03:34:16 BXT-2 kernel: [ 13.803795] [drm:drm_fb_helper_hotplug_event] >May 24 03:34:16 BXT-2 kernel: [ 13.803818] [drm:drm_setup_crtcs] >May 24 03:34:16 BXT-2 kernel: [ 13.803846] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:34:16 BXT-2 kernel: [ 13.803939] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:34:16 BXT-2 kernel: [ 13.804078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:34:16 BXT-2 kernel: [ 13.804086] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:34:16 BXT-2 kernel: [ 13.804139] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:34:16 BXT-2 kernel: [ 13.805445] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:34:16 BXT-2 kernel: [ 13.806387] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:34:16 BXT-2 kernel: [ 13.806434] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:34:16 BXT-2 kernel: [ 13.806477] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:34:16 BXT-2 kernel: [ 13.806520] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:34:16 BXT-2 kernel: [ 13.807093] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:34:16 BXT-2 kernel: [ 13.807139] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:34:16 BXT-2 kernel: [ 13.812203] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:34:16 BXT-2 kernel: [ 13.812279] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:34:16 BXT-2 kernel: [ 13.812286] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812292] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812297] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812302] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812307] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812312] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812318] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:34:16 BXT-2 kernel: [ 13.812323] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812328] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:34:16 BXT-2 kernel: [ 13.812333] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:34:16 BXT-2 kernel: [ 13.812338] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:34:16 BXT-2 kernel: [ 13.812343] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:34:16 BXT-2 kernel: [ 13.812376] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:34:16 BXT-2 kernel: [ 13.812380] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:34:16 BXT-2 kernel: [ 13.812443] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:34:16 BXT-2 kernel: [ 13.812460] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:34:16 BXT-2 kernel: [ 13.812464] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:34:16 BXT-2 kernel: [ 13.812468] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:34:16 BXT-2 kernel: [ 13.812472] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:34:16 BXT-2 kernel: [ 13.812501] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:34:17 BXT-2 content-hub-pee[1148]: Error parsing manifest for package 'com.ubuntu.gallery': com.ubuntu.gallery does not exist in any database for user gfx >May 24 03:34:17 BXT-2 content-hub-pee[1148]: Unable to get snap information for 'com.ubuntu.gallery': Status code is: 404 >May 24 03:34:17 BXT-2 content-hub-pee[1148]: Error parsing manifest for package 'com.ubuntu.gallery': com.ubuntu.gallery does not exist in any database for user gfx >May 24 03:34:17 BXT-2 content-hub-pee[1148]: Unable to get snap information for 'com.ubuntu.gallery': Status code is: 404 >May 24 03:34:17 BXT-2 click[1125]: hooks.vala:1216: User-level hook push-helper failed: Hook command '/usr/lib/ubuntu-push-client/click-hook-wrapper' failed: Child process exited with code 1 >May 24 03:35:29 BXT-2 kernel: [ 86.035757] Console: switching to colour dummy device 80x25 >May 24 03:35:29 BXT-2 kernel: [ 86.167644] Console: switching to colour frame buffer device 240x67 >May 24 03:35:29 BXT-2 kernel: [ 86.328195] Console: switching to colour dummy device 80x25 >May 24 03:35:29 BXT-2 kernel: [ 86.356289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:35:29 BXT-2 kernel: [ 86.356430] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:29 BXT-2 kernel: [ 86.356510] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:35:29 BXT-2 kernel: [ 86.356602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:35:29 BXT-2 kernel: [ 86.356668] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:29 BXT-2 kernel: [ 86.358121] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:35:29 BXT-2 kernel: [ 86.359161] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:35:29 BXT-2 kernel: [ 86.359230] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:29 BXT-2 kernel: [ 86.359292] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:35:29 BXT-2 kernel: [ 86.359354] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:35:29 BXT-2 kernel: [ 86.359896] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:35:29 BXT-2 kernel: [ 86.359958] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:29 BXT-2 kernel: [ 86.365296] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:35:29 BXT-2 kernel: [ 86.365366] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:35:29 BXT-2 kernel: [ 86.365392] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365397] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365402] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365407] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365413] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365418] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365423] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:29 BXT-2 kernel: [ 86.365428] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365433] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.365438] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:29 BXT-2 kernel: [ 86.365443] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:29 BXT-2 kernel: [ 86.365448] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:35:29 BXT-2 kernel: [ 86.373162] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:35:29 BXT-2 kernel: [ 86.373222] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:29 BXT-2 kernel: [ 86.373238] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:35:29 BXT-2 kernel: [ 86.373600] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:35:29 BXT-2 kernel: [ 86.373646] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:29 BXT-2 kernel: [ 86.374397] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:35:29 BXT-2 kernel: [ 86.375282] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:35:29 BXT-2 kernel: [ 86.375328] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:29 BXT-2 kernel: [ 86.375370] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:35:29 BXT-2 kernel: [ 86.375412] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:35:29 BXT-2 kernel: [ 86.375907] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:35:29 BXT-2 kernel: [ 86.375949] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:29 BXT-2 kernel: [ 86.381132] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:35:29 BXT-2 kernel: [ 86.381194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:35:29 BXT-2 kernel: [ 86.381201] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381207] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381212] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381217] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381222] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381227] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381232] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:29 BXT-2 kernel: [ 86.381237] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381242] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.381247] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:29 BXT-2 kernel: [ 86.381252] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:29 BXT-2 kernel: [ 86.381257] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:35:29 BXT-2 kernel: [ 86.381743] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:35:29 BXT-2 kernel: [ 86.381787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:35:29 BXT-2 kernel: [ 86.381831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:35:29 BXT-2 kernel: [ 86.381874] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:35:29 BXT-2 kernel: [ 86.381916] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:35:29 BXT-2 kernel: [ 86.381961] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:29 BXT-2 kernel: [ 86.382003] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:35:29 BXT-2 kernel: [ 86.382849] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:35:29 BXT-2 kernel: [ 86.382893] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:35:29 BXT-2 kernel: [ 86.382936] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:29 BXT-2 kernel: [ 86.382978] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:29 BXT-2 kernel: [ 86.383176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.383230] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:29 BXT-2 kernel: [ 86.383236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.383280] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:29 BXT-2 kernel: [ 86.383323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:29 BXT-2 kernel: [ 86.383365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:29 BXT-2 kernel: [ 86.383408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:29 BXT-2 kernel: [ 86.383450] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:29 BXT-2 kernel: [ 86.383495] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:35:29 BXT-2 kernel: [ 86.383536] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:29 BXT-2 kernel: [ 86.383581] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:35:29 BXT-2 kernel: [ 86.383624] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:35:29 BXT-2 kernel: [ 86.383667] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:35:29 BXT-2 kernel: [ 86.383710] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:35:29 BXT-2 kernel: [ 86.383752] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:35:29 BXT-2 kernel: [ 86.383801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:35:29 BXT-2 kernel: [ 86.383854] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:35:29 BXT-2 kernel: [ 86.383897] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:35:29 BXT-2 kernel: [ 86.385877] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:35:29 BXT-2 kernel: [ 86.400966] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:35:29 BXT-2 kernel: [ 86.401186] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:35:29 BXT-2 kernel: [ 86.401253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:29 BXT-2 kernel: [ 86.401299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:29 BXT-2 kernel: [ 86.401343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:29 BXT-2 kernel: [ 86.401388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:29 BXT-2 kernel: [ 86.401433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:29 BXT-2 kernel: [ 86.401478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:29 BXT-2 kernel: [ 86.401522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:29 BXT-2 kernel: [ 86.401567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:29 BXT-2 kernel: [ 86.401612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:29 BXT-2 kernel: [ 86.401659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:29 BXT-2 kernel: [ 86.401705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:29 BXT-2 kernel: [ 86.401780] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:35:29 BXT-2 kernel: [ 86.401824] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:35:29 BXT-2 kernel: [ 86.404944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:29 BXT-2 kernel: [ 86.404992] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:29 BXT-2 kernel: [ 86.405265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:29 BXT-2 kernel: [ 86.406240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:29 BXT-2 kernel: [ 86.406286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:29 BXT-2 kernel: [ 86.407232] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:29 BXT-2 kernel: [ 86.407284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:29 BXT-2 kernel: [ 86.408471] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:29 BXT-2 kernel: [ 86.410684] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:29 BXT-2 kernel: [ 86.411796] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:35:29 BXT-2 kernel: [ 86.412313] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:29 BXT-2 kernel: [ 86.412376] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:35:29 BXT-2 kernel: [ 86.412557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:29 BXT-2 kernel: [ 86.520527] PM: Syncing filesystems ... done. >May 24 03:35:29 BXT-2 kernel: [ 86.551131] PM: Preparing system for sleep (mem) >May 24 03:35:45 BXT-2 kernel: [ 86.592734] Freezing user space processes ... (elapsed 0.022 seconds) done. >May 24 03:35:45 BXT-2 kernel: [ 86.615475] OOM killer disabled. >May 24 03:35:45 BXT-2 kernel: [ 86.615479] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 03:35:45 BXT-2 kernel: [ 86.617488] PM: Suspending system (mem) >May 24 03:35:45 BXT-2 kernel: [ 86.617754] Suspending console(s) (use no_console_suspend to debug) >May 24 03:35:45 BXT-2 kernel: [ 86.747425] sd 0:0:0:0: [sda] Synchronizing SCSI cache >May 24 03:35:45 BXT-2 kernel: [ 86.753672] system 00:00: System wakeup disabled by ACPI >May 24 03:35:45 BXT-2 kernel: [ 86.754937] ACPI : EC: event blocked >May 24 03:35:45 BXT-2 kernel: [ 86.757677] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:35:45 BXT-2 kernel: [ 86.758838] sd 0:0:0:0: [sda] Stopping disk >May 24 03:35:45 BXT-2 kernel: [ 86.784821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:35:45 BXT-2 kernel: [ 86.785902] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:35:45 BXT-2 kernel: [ 86.797480] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:35:45 BXT-2 kernel: [ 86.797626] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 86.797745] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 86.798089] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 86.798136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 86.798180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 86.798223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 86.798265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 86.798308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 86.798357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 86.798399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 86.798441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 86.798484] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 86.798530] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 86.798574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 86.798618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 86.798710] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:35:45 BXT-2 kernel: [ 86.908445] PM: suspend of devices complete after 164.132 msecs >May 24 03:35:45 BXT-2 kernel: [ 86.919129] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 86.919191] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:35:45 BXT-2 kernel: [ 86.919230] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 86.919327] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 86.919367] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:35:45 BXT-2 kernel: [ 86.919408] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:35:45 BXT-2 kernel: [ 86.919446] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:35:45 BXT-2 kernel: [ 86.919992] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:35:45 BXT-2 kernel: [ 86.920065] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:35:45 BXT-2 kernel: [ 86.920908] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 86.920944] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:35:45 BXT-2 kernel: [ 86.920987] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:35:45 BXT-2 kernel: [ 86.921045] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:35:45 BXT-2 kernel: [ 86.921091] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:35:45 BXT-2 kernel: [ 86.921132] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:35:45 BXT-2 kernel: [ 86.933372] PM: late suspend of devices complete after 24.915 msecs >May 24 03:35:45 BXT-2 kernel: [ 86.936965] ACPI : EC: interrupt blocked >May 24 03:35:45 BXT-2 kernel: [ 86.937177] r8169 0000:03:00.0: System wakeup enabled by ACPI >May 24 03:35:45 BXT-2 kernel: [ 86.937646] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI >May 24 03:35:45 BXT-2 kernel: [ 86.961170] PM: noirq suspend of devices complete after 27.788 msecs >May 24 03:35:45 BXT-2 kernel: [ 86.961398] ACPI: Preparing to enter system sleep state S3 >May 24 03:35:45 BXT-2 kernel: [ 86.965862] ACPI : EC: EC stopped >May 24 03:35:45 BXT-2 kernel: [ 86.965871] PM: Saving platform NVS memory >May 24 03:35:45 BXT-2 kernel: [ 86.965922] Disabling non-boot CPUs ... >May 24 03:35:45 BXT-2 kernel: [ 86.987631] Broke affinity for irq 369 >May 24 03:35:45 BXT-2 kernel: [ 86.987642] Broke affinity for irq 370 >May 24 03:35:45 BXT-2 kernel: [ 86.987651] Broke affinity for irq 371 >May 24 03:35:45 BXT-2 kernel: [ 86.987662] Broke affinity for irq 373 >May 24 03:35:45 BXT-2 kernel: [ 86.989159] smpboot: CPU 1 is now offline >May 24 03:35:45 BXT-2 kernel: [ 87.010860] Broke affinity for irq 369 >May 24 03:35:45 BXT-2 kernel: [ 87.010871] Broke affinity for irq 370 >May 24 03:35:45 BXT-2 kernel: [ 87.010879] Broke affinity for irq 371 >May 24 03:35:45 BXT-2 kernel: [ 87.010890] Broke affinity for irq 373 >May 24 03:35:45 BXT-2 kernel: [ 87.012054] smpboot: CPU 2 is now offline >May 24 03:35:45 BXT-2 kernel: [ 87.027453] Broke affinity for irq 1 >May 24 03:35:45 BXT-2 kernel: [ 87.027470] Broke affinity for irq 8 >May 24 03:35:45 BXT-2 kernel: [ 87.027482] Broke affinity for irq 9 >May 24 03:35:45 BXT-2 kernel: [ 87.027496] Broke affinity for irq 12 >May 24 03:35:45 BXT-2 kernel: [ 87.027509] Broke affinity for irq 14 >May 24 03:35:45 BXT-2 kernel: [ 87.027717] Broke affinity for irq 367 >May 24 03:35:45 BXT-2 kernel: [ 87.027729] Broke affinity for irq 368 >May 24 03:35:45 BXT-2 kernel: [ 87.027740] Broke affinity for irq 369 >May 24 03:35:45 BXT-2 kernel: [ 87.027751] Broke affinity for irq 370 >May 24 03:35:45 BXT-2 kernel: [ 87.027762] Broke affinity for irq 371 >May 24 03:35:45 BXT-2 kernel: [ 87.027773] Broke affinity for irq 372 >May 24 03:35:45 BXT-2 kernel: [ 87.027784] Broke affinity for irq 373 >May 24 03:35:45 BXT-2 kernel: [ 87.029036] smpboot: CPU 3 is now offline >May 24 03:35:45 BXT-2 kernel: [ 87.036421] ACPI: Low-level resume complete >May 24 03:35:45 BXT-2 kernel: [ 87.037015] ACPI : EC: EC started >May 24 03:35:45 BXT-2 kernel: [ 87.037026] PM: Restoring platform NVS memory >May 24 03:35:45 BXT-2 kernel: [ 87.038753] Suspended for 14.965 seconds >May 24 03:35:45 BXT-2 kernel: [ 87.042979] Enabling non-boot CPUs ... >May 24 03:35:45 BXT-2 kernel: [ 87.045810] x86: Booting SMP configuration: >May 24 03:35:45 BXT-2 kernel: [ 87.045935] smpboot: Booting Node 0 Processor 1 APIC 0x2 >May 24 03:35:45 BXT-2 kernel: [ 87.058404] cache: parent cpu1 should not be sleeping >May 24 03:35:45 BXT-2 kernel: [ 87.060791] CPU1 is up >May 24 03:35:45 BXT-2 kernel: [ 87.061028] smpboot: Booting Node 0 Processor 2 APIC 0x4 >May 24 03:35:45 BXT-2 kernel: [ 87.069046] cache: parent cpu2 should not be sleeping >May 24 03:35:45 BXT-2 kernel: [ 87.072347] CPU2 is up >May 24 03:35:45 BXT-2 kernel: [ 87.072559] smpboot: Booting Node 0 Processor 3 APIC 0x6 >May 24 03:35:45 BXT-2 kernel: [ 87.080974] cache: parent cpu3 should not be sleeping >May 24 03:35:45 BXT-2 kernel: [ 87.084670] CPU3 is up >May 24 03:35:45 BXT-2 kernel: [ 87.089104] ACPI: Waking up from system sleep state S3 >May 24 03:35:45 BXT-2 kernel: [ 87.100045] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI >May 24 03:35:45 BXT-2 kernel: [ 87.100104] ACPI : EC: interrupt unblocked >May 24 03:35:45 BXT-2 kernel: [ 87.123158] PM: noirq resume of devices complete after 24.858 msecs >May 24 03:35:45 BXT-2 kernel: [ 87.123847] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.123995] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:35:45 BXT-2 kernel: [ 87.124069] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.124210] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 03:35:45 BXT-2 kernel: [ 87.124537] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.124624] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:35:45 BXT-2 kernel: [ 87.124729] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.124813] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:35:45 BXT-2 kernel: [ 87.127287] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.129584] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.129656] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.129731] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.129822] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.129931] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:35:45 BXT-2 kernel: [ 87.131360] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.138307] PM: early resume of devices complete after 14.722 msecs >May 24 03:35:45 BXT-2 kernel: [ 87.138956] ACPI : EC: event unblocked >May 24 03:35:45 BXT-2 kernel: [ 87.141307] r8169 0000:03:00.0: System wakeup disabled by ACPI >May 24 03:35:45 BXT-2 kernel: [ 87.141483] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 03:35:45 BXT-2 kernel: [ 87.149898] sd 0:0:0:0: [sda] Starting disk >May 24 03:35:45 BXT-2 kernel: [ 87.154170] r8169 0000:03:00.0 enp3s0: link down >May 24 03:35:45 BXT-2 kernel: [ 87.248366] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:35:45 BXT-2 kernel: [ 87.248456] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:35:45 BXT-2 kernel: [ 87.248499] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:35:45 BXT-2 kernel: [ 87.248590] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:35:45 BXT-2 kernel: [ 87.248713] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38 >May 24 03:35:45 BXT-2 kernel: [ 87.249104] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:35:45 BXT-2 kernel: [ 87.249177] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:35:45 BXT-2 kernel: [ 87.249283] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:35:45 BXT-2 kernel: [ 87.249391] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:35:45 BXT-2 kernel: [ 87.249499] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:35:45 BXT-2 kernel: [ 87.250232] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.250305] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:35:45 BXT-2 kernel: [ 87.250420] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.250463] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:35:45 BXT-2 kernel: [ 87.250514] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.250556] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:35:45 BXT-2 kernel: [ 87.250609] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.250650] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:35:45 BXT-2 kernel: [ 87.250697] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:35:45 BXT-2 kernel: [ 87.250742] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:35:45 BXT-2 kernel: [ 87.250786] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:35:45 BXT-2 kernel: [ 87.250832] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.250931] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.250973] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.251018] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:35:45 BXT-2 kernel: [ 87.251065] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.251109] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.251153] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.251197] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:35:45 BXT-2 kernel: [ 87.251290] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:35:45 BXT-2 kernel: [ 87.251347] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:35:45 BXT-2 kernel: [ 87.251401] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:35:45 BXT-2 kernel: [ 87.251443] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.251484] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.251525] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:45 BXT-2 kernel: [ 87.251535] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.251576] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:45 BXT-2 kernel: [ 87.251581] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.251623] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.251666] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:35:45 BXT-2 kernel: [ 87.251707] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.251751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:45 BXT-2 kernel: [ 87.251792] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.251837] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.251901] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:45 BXT-2 kernel: [ 87.251944] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.251987] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252030] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252074] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252118] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:35:45 BXT-2 kernel: [ 87.252160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252201] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252242] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:45 BXT-2 kernel: [ 87.252247] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.252288] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:45 BXT-2 kernel: [ 87.252292] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.252334] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.252376] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252417] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:45 BXT-2 kernel: [ 87.252500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252542] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.252584] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:45 BXT-2 kernel: [ 87.252627] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252670] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252714] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252755] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.252799] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:35:45 BXT-2 kernel: [ 87.252859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252900] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.252941] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:45 BXT-2 kernel: [ 87.252946] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.252987] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:45 BXT-2 kernel: [ 87.252991] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.253033] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.253075] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:35:45 BXT-2 kernel: [ 87.253116] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.253158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:45 BXT-2 kernel: [ 87.253199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.253241] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.253283] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:45 BXT-2 kernel: [ 87.253326] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.253368] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.253409] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.253589] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.253655] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:35:45 BXT-2 kernel: [ 87.253695] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.253784] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.253825] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.253882] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:35:45 BXT-2 kernel: [ 87.253922] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:35:45 BXT-2 kernel: [ 87.254467] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.254557] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:35:45 BXT-2 kernel: [ 87.254600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:35:45 BXT-2 kernel: [ 87.254646] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:35:45 BXT-2 kernel: [ 87.254689] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:35:45 BXT-2 kernel: [ 87.254730] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:35:45 BXT-2 kernel: [ 87.254773] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.254816] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:35:45 BXT-2 kernel: [ 87.254877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.254921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:35:45 BXT-2 kernel: [ 87.254963] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.255004] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:45 BXT-2 kernel: [ 87.255010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.255051] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:45 BXT-2 kernel: [ 87.255056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.255099] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.255140] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:45 BXT-2 kernel: [ 87.255182] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:45 BXT-2 kernel: [ 87.255223] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:45 BXT-2 kernel: [ 87.255264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.255308] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:35:45 BXT-2 kernel: [ 87.255349] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:45 BXT-2 kernel: [ 87.255390] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.255431] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.255473] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.255514] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.255562] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.255616] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.255661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.255707] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.255749] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.255932] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.255968] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.256255] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.256307] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.256346] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.256429] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.258157] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.258480] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.258525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 87.258568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.258612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.258655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.258697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 87.258739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.258783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.258825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.258910] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:45 BXT-2 kernel: [ 87.258961] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 87.259006] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 87.259050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.259125] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:35:45 BXT-2 kernel: [ 87.259167] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.261410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.261454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.261498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:45 BXT-2 kernel: [ 87.262292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.262333] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.263091] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:45 BXT-2 kernel: [ 87.263133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:45 BXT-2 kernel: [ 87.264185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:45 BXT-2 kernel: [ 87.266301] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:45 BXT-2 kernel: [ 87.267363] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.284299] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.284374] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:35:45 BXT-2 kernel: [ 87.284579] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.284712] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 87.284788] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:35:45 BXT-2 kernel: [ 87.285132] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:35:45 BXT-2 kernel: [ 87.285372] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:45 BXT-2 kernel: [ 87.285454] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 03:35:45 BXT-2 kernel: [ 87.285533] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.285835] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:35:45 BXT-2 kernel: [ 87.287724] PM: resume of devices complete after 149.404 msecs >May 24 03:35:45 BXT-2 kernel: [ 87.288148] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:35:45 BXT-2 kernel: [ 87.289768] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:35:45 BXT-2 kernel: [ 87.289833] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:45 BXT-2 kernel: [ 87.289929] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:35:45 BXT-2 kernel: [ 87.289990] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:35:45 BXT-2 kernel: [ 87.290468] PM: Finishing wakeup. >May 24 03:35:45 BXT-2 kernel: [ 87.290475] OOM killer enabled. >May 24 03:35:45 BXT-2 kernel: [ 87.290479] Restarting tasks ... >May 24 03:35:45 BXT-2 kernel: [ 87.290549] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:35:45 BXT-2 kernel: [ 87.291221] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:45 BXT-2 kernel: [ 87.298115] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:35:45 BXT-2 kernel: [ 87.317907] done. >May 24 03:35:45 BXT-2 NetworkManager[793]: <info> [1495614945.2568] device (enp3s0): link disconnected >May 24 03:35:45 BXT-2 kernel: [ 87.326223] video LNXVIDEO:00: Restoring backlight state >May 24 03:35:45 BXT-2 kernel: [ 87.329124] [drm:drm_mode_addfb2] [FB:79] >May 24 03:35:45 BXT-2 kernel: [ 87.454837] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:35:45 BXT-2 kernel: [ 87.624870] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:35:45 BXT-2 kernel: [ 87.665945] ata1.00: configured for UDMA/133 >May 24 03:35:45 BXT-2 kernel: [ 87.690427] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x1000181a, pins 0x00000020 >May 24 03:35:45 BXT-2 kernel: [ 87.690532] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long >May 24 03:35:45 BXT-2 kernel: [ 87.690629] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.690922] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long >May 24 03:35:45 BXT-2 kernel: [ 87.691682] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions >May 24 03:35:45 BXT-2 kernel: [ 87.692658] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event. >May 24 03:35:45 BXT-2 kernel: [ 87.692841] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:45 BXT-2 kernel: [ 87.694264] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:35:45 BXT-2 kernel: [ 87.708028] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:35:45 BXT-2 kernel: [ 87.708196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.708369] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:35:45 BXT-2 kernel: [ 87.718112] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:35:45 BXT-2 kernel: [ 87.718225] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.718342] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.718676] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.718723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 87.718767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.718810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.718886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.718934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 87.718984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.719031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.719076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.719123] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.719171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 87.719217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 87.719262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.719392] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.719533] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.719677] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.719751] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:35:45 BXT-2 kernel: [ 87.719805] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.719870] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:35:45 BXT-2 kernel: [ 87.719912] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:35:45 BXT-2 kernel: [ 87.720461] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.723338] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 87.723418] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.723579] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:35:45 BXT-2 kernel: [ 87.723646] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:35:45 BXT-2 kernel: [ 87.723711] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:35:45 BXT-2 kernel: [ 87.723777] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:35:45 BXT-2 kernel: [ 87.723838] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:35:45 BXT-2 kernel: [ 87.723946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.724016] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:35:45 BXT-2 kernel: [ 87.724084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.724151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:35:45 BXT-2 kernel: [ 87.724216] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.724278] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:45 BXT-2 kernel: [ 87.724288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.724349] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:45 BXT-2 kernel: [ 87.724358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.724422] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.724485] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:45 BXT-2 kernel: [ 87.724548] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:45 BXT-2 kernel: [ 87.724611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:45 BXT-2 kernel: [ 87.724674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.724741] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:35:45 BXT-2 kernel: [ 87.724803] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:45 BXT-2 kernel: [ 87.724908] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.724979] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.725046] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.725112] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.725199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.725272] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.725336] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.726244] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.726300] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.726607] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.726680] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.726738] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.727170] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.728738] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.729250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.729317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 87.729382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.729445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.729508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.729618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 87.729661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.729704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.729746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.729789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 87.729837] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 87.729911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.729988] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:35:45 BXT-2 kernel: [ 87.730031] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.731579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.731624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.731668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:45 BXT-2 kernel: [ 87.732449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.732491] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.733231] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:45 BXT-2 kernel: [ 87.733275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:45 BXT-2 kernel: [ 87.734322] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:45 BXT-2 kernel: [ 87.736420] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:45 BXT-2 kernel: [ 87.737461] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.754348] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.754413] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 87.754594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.770913] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:35:45 BXT-2 kernel: [ 87.838194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.839376] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.856118] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:35:45 BXT-2 kernel: [ 87.856328] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.856484] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.856843] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.857124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 87.857184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.857244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.857303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.857362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 87.857429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.857488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.857548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.857607] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.857672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 87.857734] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 87.857796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.858098] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.858292] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.858497] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.858609] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 87.858689] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.858747] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:35:45 BXT-2 kernel: [ 87.858799] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:35:45 BXT-2 kernel: [ 87.859459] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.860525] [drm:drm_mode_addfb2] [FB:77] >May 24 03:35:45 BXT-2 kernel: [ 87.881003] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 87.881088] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.881213] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:35:45 BXT-2 kernel: [ 87.881256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:35:45 BXT-2 kernel: [ 87.881303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:35:45 BXT-2 kernel: [ 87.881348] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:35:45 BXT-2 kernel: [ 87.881390] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:35:45 BXT-2 kernel: [ 87.881434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.881479] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:35:45 BXT-2 kernel: [ 87.881523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.881566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:35:45 BXT-2 kernel: [ 87.881608] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.881650] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:45 BXT-2 kernel: [ 87.881660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.881701] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:45 BXT-2 kernel: [ 87.881707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.881751] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:45 BXT-2 kernel: [ 87.881795] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:45 BXT-2 kernel: [ 87.881837] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:45 BXT-2 kernel: [ 87.882709] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:45 BXT-2 kernel: [ 87.882751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:45 BXT-2 kernel: [ 87.882797] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:35:45 BXT-2 kernel: [ 87.882838] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:45 BXT-2 kernel: [ 87.883084] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.883127] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.883170] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.883212] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:35:45 BXT-2 kernel: [ 87.883282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.883336] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.883380] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.884384] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:35:45 BXT-2 kernel: [ 87.884423] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:35:45 BXT-2 kernel: [ 87.884711] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:35:45 BXT-2 kernel: [ 87.884799] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.885068] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 87.885127] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 87.885403] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.885727] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.885770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 87.885813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.886134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.886177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.886219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 87.886262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 87.886304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 87.886347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 87.886390] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 87.886438] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 87.886482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.886555] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:35:45 BXT-2 kernel: [ 87.886598] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.888314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.888358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:45 BXT-2 kernel: [ 87.888402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:45 BXT-2 kernel: [ 87.889282] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:45 BXT-2 kernel: [ 87.889326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:45 BXT-2 kernel: [ 87.890426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:45 BXT-2 kernel: [ 87.892521] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:45 BXT-2 kernel: [ 87.893567] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:35:45 BXT-2 kernel: [ 87.910448] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 87.910506] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 87.910680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 87.994015] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:35:45 BXT-2 kernel: [ 87.994143] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:35:45 BXT-2 kernel: [ 88.012196] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:35:45 BXT-2 kernel: [ 88.012308] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 88.012398] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 88.012720] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:45 BXT-2 kernel: [ 88.012764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:45 BXT-2 kernel: [ 88.012807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 88.012911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 88.012955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 88.012997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:45 BXT-2 kernel: [ 88.013046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:45 BXT-2 kernel: [ 88.013089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:45 BXT-2 kernel: [ 88.013131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:45 BXT-2 kernel: [ 88.013174] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:45 BXT-2 kernel: [ 88.013222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:45 BXT-2 kernel: [ 88.013267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:45 BXT-2 kernel: [ 88.013312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:45 BXT-2 kernel: [ 88.013374] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:35:45 BXT-2 kernel: [ 88.013416] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 88.013469] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:35:45 BXT-2 kernel: [ 88.013530] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:35:45 BXT-2 kernel: [ 88.013575] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:35:45 BXT-2 kernel: [ 88.013618] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:35:45 BXT-2 kernel: [ 88.013656] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:35:45 BXT-2 kernel: [ 88.014245] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:35:45 BXT-2 kernel: [ 88.019161] [drm] RC6 on >May 24 03:35:46 BXT-2 kernel: [ 88.039750] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:35:46 BXT-2 kernel: [ 88.039807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:35:46 BXT-2 kernel: [ 88.039907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:35:46 BXT-2 kernel: [ 88.039950] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:35:46 BXT-2 kernel: [ 88.039991] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.040034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.040076] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:35:46 BXT-2 kernel: [ 88.040118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.040160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:35:46 BXT-2 kernel: [ 88.040201] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.040241] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:46 BXT-2 kernel: [ 88.040249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.040289] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:46 BXT-2 kernel: [ 88.040294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.040336] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.040377] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:46 BXT-2 kernel: [ 88.040418] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:46 BXT-2 kernel: [ 88.040460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:46 BXT-2 kernel: [ 88.040500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.040544] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:35:46 BXT-2 kernel: [ 88.040585] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:46 BXT-2 kernel: [ 88.040626] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.040667] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.040708] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.040749] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.040793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.040863] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.040905] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:35:46 BXT-2 kernel: [ 88.041116] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:35:46 BXT-2 kernel: [ 88.041183] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:35:46 BXT-2 kernel: [ 88.041501] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:35:46 BXT-2 kernel: [ 88.041556] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:35:46 BXT-2 kernel: [ 88.041595] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:35:46 BXT-2 kernel: [ 88.041772] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:35:46 BXT-2 kernel: [ 88.043034] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.043373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.043416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:46 BXT-2 kernel: [ 88.043458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:46 BXT-2 kernel: [ 88.043499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:46 BXT-2 kernel: [ 88.043541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:46 BXT-2 kernel: [ 88.043582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:46 BXT-2 kernel: [ 88.043624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:46 BXT-2 kernel: [ 88.043666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:46 BXT-2 kernel: [ 88.043708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:46 BXT-2 kernel: [ 88.043749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:46 BXT-2 kernel: [ 88.043795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:46 BXT-2 kernel: [ 88.043839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.043968] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:35:46 BXT-2 kernel: [ 88.044021] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.046619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.046662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.046706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:46 BXT-2 kernel: [ 88.047488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.047529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.048289] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:46 BXT-2 kernel: [ 88.048348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:46 BXT-2 kernel: [ 88.049407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:46 BXT-2 kernel: [ 88.051513] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:46 BXT-2 kernel: [ 88.052742] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:35:46 BXT-2 kernel: [ 88.068288] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x10001819, pins 0x00000020 >May 24 03:35:46 BXT-2 kernel: [ 88.068335] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short >May 24 03:35:46 BXT-2 kernel: [ 88.068434] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short >May 24 03:35:46 BXT-2 kernel: [ 88.069940] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.069995] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:35:46 BXT-2 kernel: [ 88.070179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.070602] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:35:46 BXT-2 kernel: [ 88.070604] Console: switching to colour frame buffer device 240x67 >May 24 03:35:46 BXT-2 kernel: [ 88.071890] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions >May 24 03:35:46 BXT-2 kernel: [ 88.071939] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event. >May 24 03:35:46 BXT-2 kernel: [ 88.071985] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.072639] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:35:46 BXT-2 kernel: [ 88.073888] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:35:46 BXT-2 kernel: [ 88.073931] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.073973] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.074014] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.074661] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:35:46 BXT-2 kernel: [ 88.075304] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:46 BXT-2 kernel: [ 88.076473] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.078547] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.079898] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.083359] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.084676] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.085980] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.087230] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.088523] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.089771] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.091159] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.092561] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.093971] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.095414] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.096794] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.098189] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.099662] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.101034] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.102418] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.103777] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.105035] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.106401] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.107904] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.109742] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.111174] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.113076] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.114765] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.116186] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.118173] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.119695] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.120488] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:35:46 BXT-2 kernel: [ 88.121008] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:52:DP-1] status updated from disconnected to connected >May 24 03:35:46 BXT-2 kernel: [ 88.137097] [drm:drm_fb_helper_hotplug_event] >May 24 03:35:46 BXT-2 kernel: [ 88.137104] [drm:drm_setup_crtcs] >May 24 03:35:46 BXT-2 kernel: [ 88.137197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.137313] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.139597] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:35:46 BXT-2 kernel: [ 88.140718] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:35:46 BXT-2 kernel: [ 88.140767] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.140810] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.140948] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.141451] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:35:46 BXT-2 kernel: [ 88.141930] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:46 BXT-2 kernel: [ 88.142914] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.144642] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.145925] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.147196] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.162879] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.164148] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.165397] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.166687] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.167963] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.169451] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.170901] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.172327] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.173699] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.175074] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.176450] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.177958] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.179330] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.180586] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.181861] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.183108] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.184382] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.185773] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.187153] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.188865] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.190243] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.191922] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.193447] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.194832] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.196191] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.197020] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:35:46 BXT-2 kernel: [ 88.197793] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.197799] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:35:46 BXT-2 kernel: [ 88.197850] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:35:46 BXT-2 kernel: [ 88.197854] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:35:46 BXT-2 kernel: [ 88.198531] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:35:46 BXT-2 kernel: [ 88.198541] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198547] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198552] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.198558] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.198563] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198569] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.198574] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:35:46 BXT-2 kernel: [ 88.198579] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198585] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198590] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:35:46 BXT-2 kernel: [ 88.198596] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198601] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198607] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198612] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198617] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198623] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198628] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198634] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198639] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198645] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198650] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198656] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198661] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198666] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198672] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198677] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.198683] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198688] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198693] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198699] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198704] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198710] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198715] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.198720] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:35:46 BXT-2 kernel: [ 88.198729] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.198793] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.199396] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:35:46 BXT-2 kernel: [ 88.200273] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:35:46 BXT-2 kernel: [ 88.200320] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.200365] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:35:46 BXT-2 kernel: [ 88.200513] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:35:46 BXT-2 kernel: [ 88.201007] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:35:46 BXT-2 kernel: [ 88.201053] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:46 BXT-2 kernel: [ 88.205770] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:35:46 BXT-2 kernel: [ 88.205905] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:35:46 BXT-2 kernel: [ 88.205913] [drm:drm_mode_debug_printmodeline] Modeline 65:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205918] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205923] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205931] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205939] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205946] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205952] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.205958] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205963] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.205968] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.205973] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.205982] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:35:46 BXT-2 kernel: [ 88.206036] [drm:drm_setup_crtcs] connector 52 enabled? yes >May 24 03:35:46 BXT-2 kernel: [ 88.206040] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:35:46 BXT-2 kernel: [ 88.206102] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:35:46 BXT-2 kernel: [ 88.206113] [drm:drm_setup_crtcs] looking for cmdline mode on connector 52 >May 24 03:35:46 BXT-2 kernel: [ 88.206117] [drm:drm_setup_crtcs] looking for preferred mode on connector 52 0 >May 24 03:35:46 BXT-2 kernel: [ 88.206121] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:35:46 BXT-2 kernel: [ 88.206125] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:35:46 BXT-2 kernel: [ 88.206129] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:35:46 BXT-2 kernel: [ 88.206132] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:35:46 BXT-2 kernel: [ 88.206136] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:35:46 BXT-2 kernel: [ 88.206201] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:35:46 BXT-2 kernel: [ 88.206213] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 43 (0,0) >May 24 03:35:46 BXT-2 kernel: [ 88.206478] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:35:46 BXT-2 kernel: [ 88.206522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:35:46 BXT-2 kernel: [ 88.206566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:35:46 BXT-2 kernel: [ 88.206609] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:35:46 BXT-2 kernel: [ 88.206651] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:35:46 BXT-2 kernel: [ 88.206696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.206739] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:35:46 BXT-2 kernel: [ 88.206782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.206825] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:35:46 BXT-2 kernel: [ 88.206915] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.206961] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:46 BXT-2 kernel: [ 88.206971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.207017] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:46 BXT-2 kernel: [ 88.207026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.207072] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.207117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:46 BXT-2 kernel: [ 88.207163] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:46 BXT-2 kernel: [ 88.207209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:46 BXT-2 kernel: [ 88.207254] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.207301] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:35:46 BXT-2 kernel: [ 88.207346] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:46 BXT-2 kernel: [ 88.207391] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 03:35:46 BXT-2 kernel: [ 88.207439] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 03:35:46 BXT-2 kernel: [ 88.207482] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.207525] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.207568] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.207615] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:35:46 BXT-2 kernel: [ 88.207659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:35:46 BXT-2 kernel: [ 88.207703] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:35:46 BXT-2 kernel: [ 88.207746] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:35:46 BXT-2 kernel: [ 88.207789] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.207833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.207924] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:35:46 BXT-2 kernel: [ 88.207968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.208015] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:35:46 BXT-2 kernel: [ 88.208060] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.208104] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:35:46 BXT-2 kernel: [ 88.208111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.208154] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:35:46 BXT-2 kernel: [ 88.208163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.208209] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.208252] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:35:46 BXT-2 kernel: [ 88.208295] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:35:46 BXT-2 kernel: [ 88.208338] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:35:46 BXT-2 kernel: [ 88.208381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:35:46 BXT-2 kernel: [ 88.208425] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:35:46 BXT-2 kernel: [ 88.208467] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:35:46 BXT-2 kernel: [ 88.208510] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.208553] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.208596] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.208639] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:35:46 BXT-2 kernel: [ 88.208684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.208740] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:35:46 BXT-2 kernel: [ 88.208783] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:35:46 BXT-2 kernel: [ 88.208828] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.208927] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:35:46 BXT-2 kernel: [ 88.210065] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:35:46 BXT-2 kernel: [ 88.220256] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 03:35:46 BXT-2 kernel: [ 88.220433] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.220517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:35:46 BXT-2 kernel: [ 88.220562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:35:46 BXT-2 kernel: [ 88.220605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:35:46 BXT-2 kernel: [ 88.220648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:35:46 BXT-2 kernel: [ 88.220691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:35:46 BXT-2 kernel: [ 88.220735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:35:46 BXT-2 kernel: [ 88.221265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:35:46 BXT-2 kernel: [ 88.221309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:35:46 BXT-2 kernel: [ 88.221353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:35:46 BXT-2 kernel: [ 88.221404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:46 BXT-2 kernel: [ 88.221449] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.221525] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:35:46 BXT-2 kernel: [ 88.221569] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:35:46 BXT-2 kernel: [ 88.225608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.225654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.225699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:46 BXT-2 kernel: [ 88.244693] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:46 BXT-2 kernel: [ 88.244741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 03:35:46 BXT-2 kernel: [ 88.264528] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:46 BXT-2 kernel: [ 88.266627] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 03:35:46 BXT-2 kernel: [ 88.267729] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:35:46 BXT-2 kernel: [ 88.267959] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:35:46 BXT-2 kernel: [ 88.268004] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:35:46 BXT-2 kernel: [ 88.268104] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:35:46 BXT-2 kernel: [ 88.284648] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:35:46 BXT-2 kernel: [ 88.284701] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.286169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.286219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.286271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:46 BXT-2 kernel: [ 88.287086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.287142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.287974] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:46 BXT-2 kernel: [ 88.288017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:46 BXT-2 kernel: [ 88.289141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:46 BXT-2 kernel: [ 88.291290] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:46 BXT-2 kernel: [ 88.292097] Console: switching to colour dummy device 80x25 >May 24 03:35:46 BXT-2 kernel: [ 88.292468] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:35:46 BXT-2 kernel: [ 88.309347] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.309422] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:35:46 BXT-2 kernel: [ 88.309606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:35:46 BXT-2 kernel: [ 88.309780] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.309921] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:35:46 BXT-2 kernel: [ 88.310400] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:35:46 BXT-2 kernel: [ 88.314611] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.314702] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.315337] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:35:46 BXT-2 kernel: [ 88.316304] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:35:46 BXT-2 kernel: [ 88.316375] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.316441] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.316508] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.317072] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:35:46 BXT-2 kernel: [ 88.317528] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:46 BXT-2 kernel: [ 88.318508] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.320548] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.321869] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.323145] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.324549] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.325974] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.327267] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.328596] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.329909] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.331332] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.332702] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.334075] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.335445] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.337020] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.338407] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.339782] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.341141] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.342399] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.343644] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.344898] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.346135] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.347514] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.348887] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.350309] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.351677] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.353053] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.354446] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.355846] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.357226] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.358024] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:35:46 BXT-2 kernel: [ 88.358892] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.358900] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:35:46 BXT-2 kernel: [ 88.358907] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:35:46 BXT-2 kernel: [ 88.358912] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:35:46 BXT-2 kernel: [ 88.359731] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:35:46 BXT-2 kernel: [ 88.359742] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359748] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359754] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.359760] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.359766] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359771] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.359777] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:35:46 BXT-2 kernel: [ 88.359783] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359789] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359795] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:35:46 BXT-2 kernel: [ 88.359801] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359872] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359882] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359890] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359899] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359909] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359916] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359922] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359928] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359934] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359940] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359946] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359951] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359957] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359963] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359971] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.359980] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359988] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.359997] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.360005] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.360013] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.360022] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.360030] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.360037] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:35:46 BXT-2 kernel: [ 88.360136] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.360201] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.360231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] status updated from connected to disconnected >May 24 03:35:46 BXT-2 kernel: [ 88.360250] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] disconnected >May 24 03:35:46 BXT-2 kernel: [ 88.360304] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x10001918, pins 0x00000040 >May 24 03:35:46 BXT-2 kernel: [ 88.360356] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short >May 24 03:35:46 BXT-2 kernel: [ 88.360454] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short >May 24 03:35:46 BXT-2 kernel: [ 88.361046] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:35:46 BXT-2 kernel: [ 88.363636] [drm:intel_dp_check_link_status [i915]] DDI C: channel EQ not ok, retraining >May 24 03:35:46 BXT-2 kernel: [ 88.364986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.365038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.365089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:35:46 BXT-2 kernel: [ 88.369311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.369375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:35:46 BXT-2 kernel: [ 88.370246] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:35:46 BXT-2 kernel: [ 88.370296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:35:46 BXT-2 kernel: [ 88.371646] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:35:46 BXT-2 kernel: [ 88.372947] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:35:46 BXT-2 kernel: [ 88.381262] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.381327] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:35:46 BXT-2 kernel: [ 88.381927] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 03:35:46 BXT-2 kernel: [ 88.382799] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 03:35:46 BXT-2 kernel: [ 88.382893] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.382940] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.382986] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.383473] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 03:35:46 BXT-2 kernel: [ 88.383896] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:46 BXT-2 kernel: [ 88.384769] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.386115] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.387376] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.388641] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.389913] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.391161] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.392412] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.393685] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.394938] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.396323] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.397735] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.399130] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.400528] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.401923] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.403328] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.404739] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.406132] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.407413] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.408706] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.410014] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.411330] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.412874] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.414393] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.415794] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.417191] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.418653] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.420033] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.421415] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.422799] [drm:drm_dp_i2c_do_msg] native defer >May 24 03:35:46 BXT-2 kernel: [ 88.423620] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 03:35:46 BXT-2 kernel: [ 88.424410] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 03:35:46 BXT-2 kernel: [ 88.424416] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 03:35:46 BXT-2 kernel: [ 88.424421] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 03:35:46 BXT-2 kernel: [ 88.424426] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 03:35:46 BXT-2 kernel: [ 88.424669] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 03:35:46 BXT-2 kernel: [ 88.424676] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424681] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424687] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.424692] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.424697] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424702] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 03:35:46 BXT-2 kernel: [ 88.424707] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 03:35:46 BXT-2 kernel: [ 88.424712] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424717] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424722] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 03:35:46 BXT-2 kernel: [ 88.424727] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424732] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424737] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424742] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424747] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424752] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424757] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424762] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424767] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424772] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424777] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424782] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424787] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424792] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424797] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424802] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.424854] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424862] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424872] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424880] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424886] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424893] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424900] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.424908] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:35:46 BXT-2 kernel: [ 88.425323] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.425381] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:35:46 BXT-2 kernel: [ 88.425931] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:35:46 BXT-2 kernel: [ 88.426791] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:35:46 BXT-2 kernel: [ 88.426835] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:35:46 BXT-2 kernel: [ 88.426908] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:35:46 BXT-2 kernel: [ 88.426954] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:35:46 BXT-2 kernel: [ 88.427448] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:35:46 BXT-2 kernel: [ 88.427490] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:35:46 BXT-2 kernel: [ 88.432136] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] status updated from disconnected to connected >May 24 03:35:46 BXT-2 kernel: [ 88.432388] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:35:46 BXT-2 kernel: [ 88.432399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:35:46 BXT-2 kernel: [ 88.432406] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432411] [drm:drm_mode_debug_printmodeline] Modeline 70:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432416] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432421] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432426] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432431] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432436] [drm:drm_mode_debug_printmodeline] Modeline 77:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.432441] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432446] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:35:46 BXT-2 kernel: [ 88.432451] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.432457] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:35:46 BXT-2 kernel: [ 88.432462] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:36:03 BXT-2 kernel: [ 88.520508] PM: Syncing filesystems ... done. >May 24 03:36:03 BXT-2 kernel: [ 88.528412] PM: Preparing system for sleep (mem) >May 24 03:36:03 BXT-2 kernel: [ 88.529058] Freezing user space processes ... (elapsed 0.008 seconds) done. >May 24 03:36:03 BXT-2 kernel: [ 88.537253] OOM killer disabled. >May 24 03:36:03 BXT-2 kernel: [ 88.537256] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 03:36:03 BXT-2 kernel: [ 88.538757] PM: Suspending system (mem) >May 24 03:36:03 BXT-2 kernel: [ 88.538888] Suspending console(s) (use no_console_suspend to debug) >May 24 03:36:03 BXT-2 kernel: [ 88.662546] sd 0:0:0:0: [sda] Synchronizing SCSI cache >May 24 03:36:03 BXT-2 kernel: [ 88.667132] system 00:00: System wakeup disabled by ACPI >May 24 03:36:03 BXT-2 kernel: [ 88.667858] ACPI : EC: event blocked >May 24 03:36:03 BXT-2 kernel: [ 88.669921] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:36:03 BXT-2 kernel: [ 88.670278] sd 0:0:0:0: [sda] Stopping disk >May 24 03:36:03 BXT-2 kernel: [ 88.694260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:36:03 BXT-2 kernel: [ 88.694392] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:36:03 BXT-2 kernel: [ 88.694499] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:36:03 BXT-2 kernel: [ 88.702198] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:36:03 BXT-2 kernel: [ 88.702307] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 88.702405] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:36:03 BXT-2 kernel: [ 88.710764] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:36:03 BXT-2 kernel: [ 88.710898] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 88.710982] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 88.711302] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 88.711346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 88.711392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 88.711435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 88.711479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 88.711523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 88.711569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 88.711611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 88.711655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 88.711699] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 88.711746] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 88.711792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 88.711836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 88.711896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 88.711966] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:36:03 BXT-2 kernel: [ 88.712023] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:36:03 BXT-2 kernel: [ 88.821149] PM: suspend of devices complete after 159.271 msecs >May 24 03:36:03 BXT-2 kernel: [ 88.831775] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 88.831819] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:36:03 BXT-2 kernel: [ 88.831919] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 88.831971] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 88.832010] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:36:03 BXT-2 kernel: [ 88.832051] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:36:03 BXT-2 kernel: [ 88.832089] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:36:03 BXT-2 kernel: [ 88.832638] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:36:03 BXT-2 kernel: [ 88.832677] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:36:03 BXT-2 kernel: [ 88.833025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 88.833062] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 03:36:03 BXT-2 kernel: [ 88.833105] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 03:36:03 BXT-2 kernel: [ 88.833148] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 03:36:03 BXT-2 kernel: [ 88.833194] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 03:36:03 BXT-2 kernel: [ 88.833236] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 03:36:03 BXT-2 kernel: [ 88.844931] PM: late suspend of devices complete after 23.774 msecs >May 24 03:36:03 BXT-2 kernel: [ 88.846972] r8169 0000:03:00.0: System wakeup enabled by ACPI >May 24 03:36:03 BXT-2 kernel: [ 88.847142] ACPI : EC: interrupt blocked >May 24 03:36:03 BXT-2 kernel: [ 88.848142] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI >May 24 03:36:03 BXT-2 kernel: [ 88.871014] PM: noirq suspend of devices complete after 26.075 msecs >May 24 03:36:03 BXT-2 kernel: [ 88.871241] ACPI: Preparing to enter system sleep state S3 >May 24 03:36:03 BXT-2 kernel: [ 88.875393] ACPI : EC: EC stopped >May 24 03:36:03 BXT-2 kernel: [ 88.875398] PM: Saving platform NVS memory >May 24 03:36:03 BXT-2 kernel: [ 88.875413] Disabling non-boot CPUs ... >May 24 03:36:03 BXT-2 kernel: [ 88.885937] Broke affinity for irq 369 >May 24 03:36:03 BXT-2 kernel: [ 88.885948] Broke affinity for irq 370 >May 24 03:36:03 BXT-2 kernel: [ 88.885959] Broke affinity for irq 371 >May 24 03:36:03 BXT-2 kernel: [ 88.885970] Broke affinity for irq 373 >May 24 03:36:03 BXT-2 kernel: [ 88.887494] smpboot: CPU 1 is now offline >May 24 03:36:03 BXT-2 kernel: [ 88.915839] Broke affinity for irq 369 >May 24 03:36:03 BXT-2 kernel: [ 88.915854] Broke affinity for irq 370 >May 24 03:36:03 BXT-2 kernel: [ 88.915867] Broke affinity for irq 371 >May 24 03:36:03 BXT-2 kernel: [ 88.915880] Broke affinity for irq 373 >May 24 03:36:03 BXT-2 kernel: [ 88.917919] smpboot: CPU 2 is now offline >May 24 03:36:03 BXT-2 kernel: [ 88.931862] Broke affinity for irq 1 >May 24 03:36:03 BXT-2 kernel: [ 88.931883] Broke affinity for irq 8 >May 24 03:36:03 BXT-2 kernel: [ 88.931897] Broke affinity for irq 9 >May 24 03:36:03 BXT-2 kernel: [ 88.931914] Broke affinity for irq 12 >May 24 03:36:03 BXT-2 kernel: [ 88.931929] Broke affinity for irq 14 >May 24 03:36:03 BXT-2 kernel: [ 88.932181] Broke affinity for irq 367 >May 24 03:36:03 BXT-2 kernel: [ 88.932195] Broke affinity for irq 368 >May 24 03:36:03 BXT-2 kernel: [ 88.932208] Broke affinity for irq 369 >May 24 03:36:03 BXT-2 kernel: [ 88.932221] Broke affinity for irq 370 >May 24 03:36:03 BXT-2 kernel: [ 88.932234] Broke affinity for irq 371 >May 24 03:36:03 BXT-2 kernel: [ 88.932248] Broke affinity for irq 372 >May 24 03:36:03 BXT-2 kernel: [ 88.932262] Broke affinity for irq 373 >May 24 03:36:03 BXT-2 kernel: [ 88.933516] smpboot: CPU 3 is now offline >May 24 03:36:03 BXT-2 kernel: [ 88.938959] ACPI: Low-level resume complete >May 24 03:36:03 BXT-2 kernel: [ 88.939555] ACPI : EC: EC started >May 24 03:36:03 BXT-2 kernel: [ 88.939565] PM: Restoring platform NVS memory >May 24 03:36:03 BXT-2 kernel: [ 88.940939] Suspended for 16.103 seconds >May 24 03:36:03 BXT-2 kernel: [ 88.942108] Enabling non-boot CPUs ... >May 24 03:36:03 BXT-2 kernel: [ 88.942662] x86: Booting SMP configuration: >May 24 03:36:03 BXT-2 kernel: [ 88.942679] smpboot: Booting Node 0 Processor 1 APIC 0x2 >May 24 03:36:03 BXT-2 kernel: [ 88.954378] cache: parent cpu1 should not be sleeping >May 24 03:36:03 BXT-2 kernel: [ 88.957330] CPU1 is up >May 24 03:36:03 BXT-2 kernel: [ 88.957605] smpboot: Booting Node 0 Processor 2 APIC 0x4 >May 24 03:36:03 BXT-2 kernel: [ 88.964961] cache: parent cpu2 should not be sleeping >May 24 03:36:03 BXT-2 kernel: [ 88.968224] CPU2 is up >May 24 03:36:03 BXT-2 kernel: [ 88.968512] smpboot: Booting Node 0 Processor 3 APIC 0x6 >May 24 03:36:03 BXT-2 kernel: [ 88.976805] cache: parent cpu3 should not be sleeping >May 24 03:36:03 BXT-2 kernel: [ 88.980562] CPU3 is up >May 24 03:36:03 BXT-2 kernel: [ 88.984074] ACPI: Waking up from system sleep state S3 >May 24 03:36:03 BXT-2 kernel: [ 88.993147] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI >May 24 03:36:03 BXT-2 kernel: [ 88.993225] ACPI : EC: interrupt unblocked >May 24 03:36:03 BXT-2 kernel: [ 89.016661] PM: noirq resume of devices complete after 24.375 msecs >May 24 03:36:03 BXT-2 kernel: [ 89.017406] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.017482] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 03:36:03 BXT-2 kernel: [ 89.017556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.017697] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 03:36:03 BXT-2 kernel: [ 89.017853] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.017940] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 03:36:03 BXT-2 kernel: [ 89.018045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.018129] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 03:36:03 BXT-2 kernel: [ 89.020552] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.023057] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.023136] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.023217] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.023317] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.023435] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:36:03 BXT-2 kernel: [ 89.023609] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.031593] PM: early resume of devices complete after 14.529 msecs >May 24 03:36:03 BXT-2 kernel: [ 89.032221] ACPI : EC: event unblocked >May 24 03:36:03 BXT-2 kernel: [ 89.033986] r8169 0000:03:00.0: System wakeup disabled by ACPI >May 24 03:36:03 BXT-2 kernel: [ 89.034034] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 03:36:03 BXT-2 kernel: [ 89.042706] sd 0:0:0:0: [sda] Starting disk >May 24 03:36:03 BXT-2 kernel: [ 89.046428] r8169 0000:03:00.0 enp3s0: link down >May 24 03:36:03 BXT-2 kernel: [ 89.142799] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 03:36:03 BXT-2 kernel: [ 89.142892] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 03:36:03 BXT-2 kernel: [ 89.142934] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 03:36:03 BXT-2 kernel: [ 89.143013] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 03:36:03 BXT-2 kernel: [ 89.143135] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38 >May 24 03:36:03 BXT-2 kernel: [ 89.143444] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 03:36:03 BXT-2 kernel: [ 89.143506] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 03:36:03 BXT-2 kernel: [ 89.143613] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 03:36:03 BXT-2 kernel: [ 89.143720] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 03:36:03 BXT-2 kernel: [ 89.143826] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 03:36:03 BXT-2 kernel: [ 89.143910] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.143967] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:36:03 BXT-2 kernel: [ 89.144043] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.144088] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 03:36:03 BXT-2 kernel: [ 89.144140] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.144182] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 03:36:03 BXT-2 kernel: [ 89.144232] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.144274] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 03:36:03 BXT-2 kernel: [ 89.144320] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:36:03 BXT-2 kernel: [ 89.144405] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:36:03 BXT-2 kernel: [ 89.144450] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 03:36:03 BXT-2 kernel: [ 89.144499] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.144543] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.144587] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 03:36:03 BXT-2 kernel: [ 89.144629] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 03:36:03 BXT-2 kernel: [ 89.144674] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.144717] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.144761] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 03:36:03 BXT-2 kernel: [ 89.144804] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 03:36:03 BXT-2 kernel: [ 89.144853] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 03:36:03 BXT-2 kernel: [ 89.144901] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 03:36:03 BXT-2 kernel: [ 89.144953] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 03:36:03 BXT-2 kernel: [ 89.144995] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145036] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145077] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.145085] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145126] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.145131] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145173] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145217] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145258] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.145379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145423] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145464] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.145514] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.145556] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.145597] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.145639] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.145684] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 03:36:03 BXT-2 kernel: [ 89.145725] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145767] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145808] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.145813] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145853] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.145858] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145900] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.145942] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:36:03 BXT-2 kernel: [ 89.145983] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.146066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146109] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.146152] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.146195] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.146236] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.146280] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.146321] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.146395] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 03:36:03 BXT-2 kernel: [ 89.146437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146478] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146519] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.146524] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.146565] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.146569] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.146611] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.146653] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146694] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.146777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.146820] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.146861] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.146904] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.146946] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.146991] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.147158] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.147201] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 03:36:03 BXT-2 kernel: [ 89.147241] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.147293] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.147353] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.147396] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:36:03 BXT-2 kernel: [ 89.147433] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:36:03 BXT-2 kernel: [ 89.147977] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.148057] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.148099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.148143] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.148186] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 03:36:03 BXT-2 kernel: [ 89.148227] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 03:36:03 BXT-2 kernel: [ 89.148270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.148312] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:36:03 BXT-2 kernel: [ 89.148370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.148412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 03:36:03 BXT-2 kernel: [ 89.148454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.148495] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.148500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.148541] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.148546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.148588] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.148629] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:36:03 BXT-2 kernel: [ 89.148671] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.148712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.148753] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.148797] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:36:03 BXT-2 kernel: [ 89.148838] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.148879] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.148920] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.148962] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.149003] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.149049] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.149090] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.149132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.149174] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:36:03 BXT-2 kernel: [ 89.149215] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:36:03 BXT-2 kernel: [ 89.149257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.149299] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 03:36:03 BXT-2 kernel: [ 89.149359] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.149401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:36:03 BXT-2 kernel: [ 89.149443] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.149484] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.149489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.149530] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.149535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.149577] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.149618] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:36:03 BXT-2 kernel: [ 89.149660] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.149701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.149742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.149785] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:36:03 BXT-2 kernel: [ 89.149826] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.149868] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.149909] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.149950] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.149992] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.150037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.150091] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.150135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.150180] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.150222] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 03:36:03 BXT-2 kernel: [ 89.150397] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.150434] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.150722] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.150775] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.150813] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.150869] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.151171] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.151491] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.151534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.151576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.151617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.151659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.151700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 89.151742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.151784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.151825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.151867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 89.151912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.151956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.152028] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 03:36:03 BXT-2 kernel: [ 89.152070] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.153493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.153534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.153579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:36:03 BXT-2 kernel: [ 89.189435] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -5 >May 24 03:36:03 BXT-2 kernel: [ 89.189528] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training >May 24 03:36:03 BXT-2 kernel: [ 89.189593] [drm:intel_dp_start_link_train [i915]] Link Training failed at link rate = 162000, lane count = 4 >May 24 03:36:03 BXT-2 kernel: [ 89.189829] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.191417] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.191550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.191612] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 03:36:03 BXT-2 kernel: [ 89.191709] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 03:36:03 BXT-2 kernel: [ 89.191985] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 03:36:03 BXT-2 kernel: [ 89.192049] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.193552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.193613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.193677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:36:03 BXT-2 kernel: [ 89.194532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.194592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.195401] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:36:03 BXT-2 kernel: [ 89.195462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:36:03 BXT-2 kernel: [ 89.196613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:36:03 BXT-2 kernel: [ 89.198753] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:36:03 BXT-2 kernel: [ 89.200137] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 03:36:03 BXT-2 kernel: [ 89.217061] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.217149] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:36:03 BXT-2 kernel: [ 89.217415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.217636] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 89.217722] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:36:03 BXT-2 kernel: [ 89.217948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.218095] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:36:03 BXT-2 kernel: [ 89.219733] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 03:36:03 BXT-2 kernel: [ 89.219835] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.219868] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from connected to disconnected >May 24 03:36:03 BXT-2 kernel: [ 89.219943] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 89.220078] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 03:36:03 BXT-2 kernel: [ 89.223246] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:36:03 BXT-2 kernel: [ 89.223917] PM: resume of devices complete after 192.312 msecs >May 24 03:36:03 BXT-2 kernel: [ 89.224315] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:36:03 BXT-2 kernel: [ 89.224435] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:36:03 BXT-2 kernel: [ 89.224519] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:36:03 BXT-2 kernel: [ 89.224602] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:36:03 BXT-2 kernel: [ 89.225273] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:36:03 BXT-2 kernel: [ 89.225357] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:36:03 BXT-2 kernel: [ 89.227158] PM: Finishing wakeup. >May 24 03:36:03 BXT-2 kernel: [ 89.227167] OOM killer enabled. >May 24 03:36:03 BXT-2 kernel: [ 89.227173] Restarting tasks ... >May 24 03:36:03 BXT-2 kernel: [ 89.237783] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 03:36:03 BXT-2 kernel: [ 89.251400] done. >May 24 03:36:03 BXT-2 kernel: [ 89.254866] video LNXVIDEO:00: Restoring backlight state >May 24 03:36:03 BXT-2 kernel: [ 89.257198] [drm:drm_mode_addfb2] [FB:103] >May 24 03:36:03 BXT-2 kernel: [ 89.274467] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 03:36:03 BXT-2 kernel: [ 89.274627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.278404] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.278557] [drm:i915_audio_component_get_eld [i915]] Not valid for port B >May 24 03:36:03 BXT-2 kernel: [ 89.278799] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.292646] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 34 >May 24 03:36:03 BXT-2 kernel: [ 89.292761] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.292851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.292898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.292941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.292983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.293026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 89.293069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.293112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.293154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.293197] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.293244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 89.293289] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.293377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.300374] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:36:03 BXT-2 kernel: [ 89.300768] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 03:36:03 BXT-2 kernel: [ 89.300902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.301093] [drm:intel_disable_pipe [i915]] disabling pipe B >May 24 03:36:03 BXT-2 kernel: [ 89.318683] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 43 >May 24 03:36:03 BXT-2 kernel: [ 89.318827] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.318956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.319300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.319444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.319516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.319585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.319658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.319725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 89.319800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.319868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.319936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.320004] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 89.320079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 89.320150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.320221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.320313] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.320444] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.320526] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.320621] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 03:36:03 BXT-2 kernel: [ 89.320693] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.320760] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:36:03 BXT-2 kernel: [ 89.320821] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:36:03 BXT-2 kernel: [ 89.321478] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.323834] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:36:03 BXT-2 kernel: [ 89.323882] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.324053] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.324120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.324190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 540000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.324258] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:36:03 BXT-2 kernel: [ 89.324324] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:36:03 BXT-2 kernel: [ 89.324440] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.324513] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 03:36:03 BXT-2 kernel: [ 89.324585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.324655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:36:03 BXT-2 kernel: [ 89.324723] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.324789] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.324801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.324866] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.324876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.324945] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.325013] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:36:03 BXT-2 kernel: [ 89.325081] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.325148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.325215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.325286] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 03:36:03 BXT-2 kernel: [ 89.325394] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.325469] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.325538] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.325610] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.325708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.325789] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.325857] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe C >May 24 03:36:03 BXT-2 kernel: [ 89.326614] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.326677] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.326996] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.327077] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.327139] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.327223] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.327749] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.328099] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.328168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.328235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.328301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.328457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.328517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 89.328591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.328635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.328678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.328723] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 89.328771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.328817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.328893] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 4, on? 0) for crtc 50 >May 24 03:36:03 BXT-2 kernel: [ 89.328937] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.330422] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.330467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.330511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:36:03 BXT-2 kernel: [ 89.348336] ata2: SATA link down (SStatus 4 SControl 300) >May 24 03:36:03 BXT-2 kernel: [ 89.365394] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -5 >May 24 03:36:03 BXT-2 kernel: [ 89.365470] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training >May 24 03:36:03 BXT-2 kernel: [ 89.365535] [drm:intel_dp_start_link_train [i915]] Link Training failed at link rate = 270000, lane count = 2 >May 24 03:36:03 BXT-2 kernel: [ 89.365624] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.367149] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 03:36:03 BXT-2 kernel: [ 89.384062] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.384136] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:36:03 BXT-2 kernel: [ 89.384339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.467549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.467680] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 03:36:03 BXT-2 kernel: [ 89.485717] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 4, on? 1) for crtc 50 >May 24 03:36:03 BXT-2 kernel: [ 89.485829] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.485910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.486234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.486279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.486411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.486479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.486546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.486610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 89.486672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.486738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.486801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.486863] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.486933] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 89.486999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.487064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.487147] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.487209] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.487285] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.487425] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 03:36:03 BXT-2 kernel: [ 89.487487] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.487549] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:36:03 BXT-2 kernel: [ 89.487604] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:36:03 BXT-2 kernel: [ 89.488170] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.489735] [drm:drm_mode_addfb2] [FB:103] >May 24 03:36:03 BXT-2 kernel: [ 89.508068] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 03:36:03 BXT-2 kernel: [ 89.508192] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.508318] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.508407] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.508453] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 162000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.508500] [drm:intel_atomic_check [i915]] Encoder config failure >May 24 03:36:03 BXT-2 kernel: [ 89.508542] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][failed] >May 24 03:36:03 BXT-2 kernel: [ 89.508588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.508631] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 0; gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.508674] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.508717] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.508724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.508766] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.508772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.508816] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.508861] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 1920x1080, pixel rate 0 >May 24 03:36:03 BXT-2 kernel: [ 89.508904] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.508949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.508992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.509039] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:36:03 BXT-2 kernel: [ 89.509081] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.509127] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.509171] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.509215] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.511336] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 03:36:03 BXT-2 kernel: [ 89.552339] ata1.00: configured for UDMA/133 >May 24 03:36:03 BXT-2 kernel: [ 89.562603] [drm] RC6 on >May 24 03:36:03 BXT-2 kernel: [ 89.589638] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.589706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.589774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 162000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.589840] [drm:intel_atomic_check [i915]] Encoder config failure >May 24 03:36:03 BXT-2 kernel: [ 89.589905] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][failed] >May 24 03:36:03 BXT-2 kernel: [ 89.589971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.590036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 0; gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.590101] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.590165] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.590175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.590238] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.590246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.590312] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.590416] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 1920x1080, pixel rate 0 >May 24 03:36:03 BXT-2 kernel: [ 89.590481] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.590547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.590611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.590680] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:36:03 BXT-2 kernel: [ 89.590744] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.590810] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.590875] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.590939] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.591004] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.591440] Console: switching to colour frame buffer device 240x67 >May 24 03:36:03 BXT-2 kernel: [ 89.604853] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.604928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.604974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 162000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.605019] [drm:intel_atomic_check [i915]] Encoder config failure >May 24 03:36:03 BXT-2 kernel: [ 89.605063] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][failed] >May 24 03:36:03 BXT-2 kernel: [ 89.605107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.605150] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 0; gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.605192] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.605233] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.605244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.605285] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.605332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.605380] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.605425] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 1920x1080, pixel rate 0 >May 24 03:36:03 BXT-2 kernel: [ 89.605471] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.605516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.605561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.605611] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:36:03 BXT-2 kernel: [ 89.605656] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.605702] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.605746] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.605792] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.605836] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.605978] [drm:drm_fb_helper_hotplug_event] >May 24 03:36:03 BXT-2 kernel: [ 89.606007] [drm:drm_setup_crtcs] >May 24 03:36:03 BXT-2 kernel: [ 89.606025] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.606107] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 03:36:03 BXT-2 kernel: [ 89.606237] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.606379] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.606706] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.606758] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.606797] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.606985] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.608279] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.608382] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.608482] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.608522] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.608566] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:36:03 BXT-2 kernel: [ 89.608609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:36:03 BXT-2 kernel: [ 89.609157] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.609169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 03:36:03 BXT-2 kernel: [ 89.609375] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 89.609427] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 89.609468] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.609505] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.609797] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.609847] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.609886] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.609940] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.611425] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 03:36:03 BXT-2 kernel: [ 89.612294] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 03:36:03 BXT-2 kernel: [ 89.612370] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 03:36:03 BXT-2 kernel: [ 89.612416] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 03:36:03 BXT-2 kernel: [ 89.612461] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 03:36:03 BXT-2 kernel: [ 89.612954] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 03:36:03 BXT-2 kernel: [ 89.612997] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 03:36:03 BXT-2 kernel: [ 89.617772] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.617817] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.617870] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.617911] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.617953] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 03:36:03 BXT-2 kernel: [ 89.617994] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 03:36:03 BXT-2 kernel: [ 89.618570] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.618679] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 03:36:03 BXT-2 kernel: [ 89.618745] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 03:36:03 BXT-2 kernel: [ 89.618754] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618760] [drm:drm_mode_debug_printmodeline] Modeline 70:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618765] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618770] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618775] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618781] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618788] [drm:drm_mode_debug_printmodeline] Modeline 77:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 03:36:03 BXT-2 kernel: [ 89.618793] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618798] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.618803] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 03:36:03 BXT-2 kernel: [ 89.618809] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 03:36:03 BXT-2 kernel: [ 89.618816] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 03:36:03 BXT-2 kernel: [ 89.618840] [drm:drm_setup_crtcs] connector 52 enabled? no >May 24 03:36:03 BXT-2 kernel: [ 89.618845] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 03:36:03 BXT-2 kernel: [ 89.618902] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 03:36:03 BXT-2 kernel: [ 89.618913] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 03:36:03 BXT-2 kernel: [ 89.618918] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 03:36:03 BXT-2 kernel: [ 89.618921] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 03:36:03 BXT-2 kernel: [ 89.618925] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 03:36:03 BXT-2 kernel: [ 89.618973] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 03:36:03 BXT-2 kernel: [ 89.619210] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 03:36:03 BXT-2 kernel: [ 89.619253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 03:36:03 BXT-2 kernel: [ 89.619300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 03:36:03 BXT-2 kernel: [ 89.619402] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 03:36:03 BXT-2 kernel: [ 89.619448] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 03:36:03 BXT-2 kernel: [ 89.619497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.619544] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 03:36:03 BXT-2 kernel: [ 89.619591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.619636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 03:36:03 BXT-2 kernel: [ 89.619681] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.619726] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 03:36:03 BXT-2 kernel: [ 89.619737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.619781] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 03:36:03 BXT-2 kernel: [ 89.619790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.619835] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 03:36:03 BXT-2 kernel: [ 89.619881] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 03:36:03 BXT-2 kernel: [ 89.619927] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 03:36:03 BXT-2 kernel: [ 89.619972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 03:36:03 BXT-2 kernel: [ 89.620014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 03:36:03 BXT-2 kernel: [ 89.620060] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 03:36:03 BXT-2 kernel: [ 89.620105] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 03:36:03 BXT-2 kernel: [ 89.620151] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.620194] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.620463] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.620506] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 03:36:03 BXT-2 kernel: [ 89.620554] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.620609] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.620652] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.620804] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 03:36:03 BXT-2 kernel: [ 89.620842] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 03:36:03 BXT-2 kernel: [ 89.621131] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 03:36:03 BXT-2 kernel: [ 89.621185] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.621225] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 03:36:03 BXT-2 kernel: [ 89.621280] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 03:36:03 BXT-2 kernel: [ 89.622162] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.622524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 03:36:03 BXT-2 kernel: [ 89.622569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 03:36:03 BXT-2 kernel: [ 89.622615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.622658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.622702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.622746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 03:36:03 BXT-2 kernel: [ 89.622791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 03:36:03 BXT-2 kernel: [ 89.622835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 03:36:03 BXT-2 kernel: [ 89.622879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 03:36:03 BXT-2 kernel: [ 89.622923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 03:36:03 BXT-2 kernel: [ 89.622972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 03:36:03 BXT-2 kernel: [ 89.623017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.623122] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 03:36:03 BXT-2 kernel: [ 89.623193] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 03:36:03 BXT-2 kernel: [ 89.625852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.625897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.625941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 03:36:03 BXT-2 kernel: [ 89.626738] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.626782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 03:36:03 BXT-2 kernel: [ 89.627518] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 03:36:03 BXT-2 kernel: [ 89.627561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 03:36:03 BXT-2 kernel: [ 89.628632] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 03:36:03 BXT-2 kernel: [ 89.630729] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 03:36:03 BXT-2 kernel: [ 89.631859] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 03:36:03 BXT-2 kernel: [ 89.648747] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 03:36:03 BXT-2 kernel: [ 89.648805] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 03:36:03 BXT-2 kernel: [ 89.648979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 03:36:07 BXT-2 kernel: [ 92.982584] r8169 0000:03:00.0 enp3s0: link up >May 24 03:36:07 BXT-2 NetworkManager[793]: <info> [1495614967.0429] device (enp3s0): link connected >May 24 03:36:37 BXT-2 kernel: [ 123.547528] blk_update_request: I/O error, dev mmcblk0rpmb, sector 0 >May 24 03:36:37 BXT-2 kernel: [ 123.844388] blk_update_request: I/O error, dev mmcblk0rpmb, sector 0 >May 24 03:36:39 BXT-2 kernel: [ 125.236605] [drm:sandybridge_pcode_read [i915]] warning: pcode (read) mailbox access failed: -6 >May 24 03:36:43 BXT-2 kernel: [ 129.896355] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 03:36:43 BXT-2 kernel: [ 129.897685] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 09:52:06 BXT-2 kernel: [22652.612072] Console: switching to colour dummy device 80x25 >May 24 09:52:06 BXT-2 kernel: [22652.736865] Console: switching to colour frame buffer device 240x67 >May 24 09:52:29 BXT-2 kernel: [22675.268554] Console: switching to colour dummy device 80x25 >May 24 09:52:29 BXT-2 kernel: [22675.289653] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 09:52:29 BXT-2 kernel: [22675.289738] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:29 BXT-2 kernel: [22675.289759] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 09:52:29 BXT-2 kernel: [22675.289794] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 09:52:29 BXT-2 kernel: [22675.289865] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:29 BXT-2 kernel: [22675.290917] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 09:52:29 BXT-2 kernel: [22675.291933] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 09:52:29 BXT-2 kernel: [22675.292004] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 09:52:29 BXT-2 kernel: [22675.292070] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 09:52:29 BXT-2 kernel: [22675.292136] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 09:52:29 BXT-2 kernel: [22675.292706] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 09:52:29 BXT-2 kernel: [22675.292775] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 09:52:29 BXT-2 kernel: [22675.298063] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 09:52:29 BXT-2 kernel: [22675.298127] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 09:52:29 BXT-2 kernel: [22675.298134] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298140] [drm:drm_mode_debug_printmodeline] Modeline 70:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298145] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298150] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298155] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298160] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298165] [drm:drm_mode_debug_printmodeline] Modeline 77:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 09:52:29 BXT-2 kernel: [22675.298170] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298175] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.298180] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 09:52:29 BXT-2 kernel: [22675.298185] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 09:52:29 BXT-2 kernel: [22675.298190] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 09:52:29 BXT-2 kernel: [22675.305169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 09:52:29 BXT-2 kernel: [22675.305229] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:29 BXT-2 kernel: [22675.305244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] disconnected >May 24 09:52:29 BXT-2 kernel: [22675.305649] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 09:52:29 BXT-2 kernel: [22675.305708] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:29 BXT-2 kernel: [22675.306255] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 09:52:29 BXT-2 kernel: [22675.307322] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 09:52:29 BXT-2 kernel: [22675.307367] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 09:52:29 BXT-2 kernel: [22675.307555] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 09:52:29 BXT-2 kernel: [22675.307597] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 09:52:29 BXT-2 kernel: [22675.308092] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 09:52:29 BXT-2 kernel: [22675.308134] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 09:52:29 BXT-2 kernel: [22675.312916] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 09:52:29 BXT-2 kernel: [22675.312980] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 09:52:29 BXT-2 kernel: [22675.312987] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.312992] [drm:drm_mode_debug_printmodeline] Modeline 70:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.312997] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.313002] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.313007] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.313012] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.313017] [drm:drm_mode_debug_printmodeline] Modeline 77:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 09:52:29 BXT-2 kernel: [22675.313022] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.313027] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 09:52:29 BXT-2 kernel: [22675.313032] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 09:52:29 BXT-2 kernel: [22675.313037] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 09:52:29 BXT-2 kernel: [22675.313042] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 09:52:29 BXT-2 kernel: [22675.395797] PM: Syncing filesystems ... done. >May 24 09:52:29 BXT-2 kernel: [22675.403520] PM: Preparing system for sleep (mem) >May 24 09:52:45 BXT-2 kernel: [22675.412271] Freezing user space processes ... (elapsed 0.003 seconds) done. >May 24 09:52:45 BXT-2 kernel: [22675.415750] OOM killer disabled. >May 24 09:52:45 BXT-2 kernel: [22675.415754] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. >May 24 09:52:45 BXT-2 kernel: [22675.417168] PM: Suspending system (mem) >May 24 09:52:45 BXT-2 kernel: [22675.417273] Suspending console(s) (use no_console_suspend to debug) >May 24 09:52:45 BXT-2 kernel: [22675.541642] sd 0:0:0:0: [sda] Synchronizing SCSI cache >May 24 09:52:45 BXT-2 kernel: [22675.545221] system 00:00: System wakeup disabled by ACPI >May 24 09:52:45 BXT-2 kernel: [22675.546149] ACPI : EC: event blocked >May 24 09:52:45 BXT-2 kernel: [22675.549135] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 09:52:45 BXT-2 kernel: [22675.549314] sd 0:0:0:0: [sda] Stopping disk >May 24 09:52:45 BXT-2 kernel: [22675.576293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 09:52:45 BXT-2 kernel: [22675.576486] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 09:52:45 BXT-2 kernel: [22675.587697] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 09:52:45 BXT-2 kernel: [22675.587806] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22675.587889] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22675.588204] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22675.588249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22675.588292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22675.588336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22675.588378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22675.588446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22675.588493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22675.588536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22675.588578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22675.588620] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22675.588671] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22675.588715] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22675.588759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22675.588823] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 09:52:45 BXT-2 kernel: [22675.697789] PM: suspend of devices complete after 158.327 msecs >May 24 09:52:45 BXT-2 kernel: [22675.708499] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22675.708543] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 09:52:45 BXT-2 kernel: [22675.708582] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22675.708633] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22675.708672] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 09:52:45 BXT-2 kernel: [22675.708713] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 09:52:45 BXT-2 kernel: [22675.708751] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 09:52:45 BXT-2 kernel: [22675.709311] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 09:52:45 BXT-2 kernel: [22675.709349] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 09:52:45 BXT-2 kernel: [22675.709699] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22675.709736] [drm:intel_power_well_disable [i915]] disabling power well 1 >May 24 09:52:45 BXT-2 kernel: [22675.709781] [drm:skl_set_power_well [i915]] Disabling power well 1 >May 24 09:52:45 BXT-2 kernel: [22675.709824] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC >May 24 09:52:45 BXT-2 kernel: [22675.709870] [drm:bxt_enable_dc9 [i915]] Enabling DC9 >May 24 09:52:45 BXT-2 kernel: [22675.709912] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08 >May 24 09:52:45 BXT-2 kernel: [22675.721488] PM: late suspend of devices complete after 23.692 msecs >May 24 09:52:45 BXT-2 kernel: [22675.723528] r8169 0000:03:00.0: System wakeup enabled by ACPI >May 24 09:52:45 BXT-2 kernel: [22675.724356] ACPI : EC: interrupt blocked >May 24 09:52:45 BXT-2 kernel: [22675.724607] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI >May 24 09:52:45 BXT-2 kernel: [22675.747545] PM: noirq suspend of devices complete after 26.048 msecs >May 24 09:52:45 BXT-2 kernel: [22675.747694] ACPI: Preparing to enter system sleep state S3 >May 24 09:52:45 BXT-2 kernel: [22675.750480] ACPI : EC: EC stopped >May 24 09:52:45 BXT-2 kernel: [22675.750483] PM: Saving platform NVS memory >May 24 09:52:45 BXT-2 kernel: [22675.750496] Disabling non-boot CPUs ... >May 24 09:52:45 BXT-2 kernel: [22675.764957] Broke affinity for irq 369 >May 24 09:52:45 BXT-2 kernel: [22675.764970] Broke affinity for irq 370 >May 24 09:52:45 BXT-2 kernel: [22675.764980] Broke affinity for irq 371 >May 24 09:52:45 BXT-2 kernel: [22675.764992] Broke affinity for irq 373 >May 24 09:52:45 BXT-2 kernel: [22675.766210] smpboot: CPU 1 is now offline >May 24 09:52:45 BXT-2 kernel: [22675.783442] Broke affinity for irq 369 >May 24 09:52:45 BXT-2 kernel: [22675.783455] Broke affinity for irq 370 >May 24 09:52:45 BXT-2 kernel: [22675.783466] Broke affinity for irq 371 >May 24 09:52:45 BXT-2 kernel: [22675.783477] Broke affinity for irq 373 >May 24 09:52:45 BXT-2 kernel: [22675.784944] smpboot: CPU 2 is now offline >May 24 09:52:45 BXT-2 kernel: [22675.802319] Broke affinity for irq 1 >May 24 09:52:45 BXT-2 kernel: [22675.802338] Broke affinity for irq 8 >May 24 09:52:45 BXT-2 kernel: [22675.802351] Broke affinity for irq 9 >May 24 09:52:45 BXT-2 kernel: [22675.802365] Broke affinity for irq 12 >May 24 09:52:45 BXT-2 kernel: [22675.802379] Broke affinity for irq 14 >May 24 09:52:45 BXT-2 kernel: [22675.802608] Broke affinity for irq 367 >May 24 09:52:45 BXT-2 kernel: [22675.802621] Broke affinity for irq 368 >May 24 09:52:45 BXT-2 kernel: [22675.802633] Broke affinity for irq 369 >May 24 09:52:45 BXT-2 kernel: [22675.802644] Broke affinity for irq 370 >May 24 09:52:45 BXT-2 kernel: [22675.802656] Broke affinity for irq 371 >May 24 09:52:45 BXT-2 kernel: [22675.802669] Broke affinity for irq 372 >May 24 09:52:45 BXT-2 kernel: [22675.802681] Broke affinity for irq 373 >May 24 09:52:45 BXT-2 kernel: [22675.803832] smpboot: CPU 3 is now offline >May 24 09:52:45 BXT-2 kernel: [22675.813355] ACPI: Low-level resume complete >May 24 09:52:45 BXT-2 kernel: [22675.813947] ACPI : EC: EC started >May 24 09:52:45 BXT-2 kernel: [22675.813957] PM: Restoring platform NVS memory >May 24 09:52:45 BXT-2 kernel: [22675.815350] Suspended for 15.131 seconds >May 24 09:52:45 BXT-2 kernel: [22675.815749] Enabling non-boot CPUs ... >May 24 09:52:45 BXT-2 kernel: [22675.817646] x86: Booting SMP configuration: >May 24 09:52:45 BXT-2 kernel: [22675.817663] smpboot: Booting Node 0 Processor 1 APIC 0x2 >May 24 09:52:45 BXT-2 kernel: [22675.828739] cache: parent cpu1 should not be sleeping >May 24 09:52:45 BXT-2 kernel: [22675.831729] CPU1 is up >May 24 09:52:45 BXT-2 kernel: [22675.832021] smpboot: Booting Node 0 Processor 2 APIC 0x4 >May 24 09:52:45 BXT-2 kernel: [22675.840389] cache: parent cpu2 should not be sleeping >May 24 09:52:45 BXT-2 kernel: [22675.843710] CPU2 is up >May 24 09:52:45 BXT-2 kernel: [22675.844027] smpboot: Booting Node 0 Processor 3 APIC 0x6 >May 24 09:52:45 BXT-2 kernel: [22675.852384] cache: parent cpu3 should not be sleeping >May 24 09:52:45 BXT-2 kernel: [22675.856424] CPU3 is up >May 24 09:52:45 BXT-2 kernel: [22675.859970] ACPI: Waking up from system sleep state S3 >May 24 09:52:45 BXT-2 kernel: [22675.868656] ACPI : EC: interrupt unblocked >May 24 09:52:45 BXT-2 kernel: [22675.870302] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI >May 24 09:52:45 BXT-2 kernel: [22675.892215] PM: noirq resume of devices complete after 24.366 msecs >May 24 09:52:45 BXT-2 kernel: [22675.892849] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00 >May 24 09:52:45 BXT-2 kernel: [22675.892955] [drm:bxt_disable_dc9 [i915]] Disabling DC9 >May 24 09:52:45 BXT-2 kernel: [22675.893037] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 09:52:45 BXT-2 kernel: [22675.893171] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 09:52:45 BXT-2 kernel: [22675.893325] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 09:52:45 BXT-2 kernel: [22675.893405] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 09:52:45 BXT-2 kernel: [22675.893502] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22675.893579] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os >May 24 09:52:45 BXT-2 kernel: [22675.895869] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22675.898001] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 09:52:45 BXT-2 kernel: [22675.898066] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 09:52:45 BXT-2 kernel: [22675.898134] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 09:52:45 BXT-2 kernel: [22675.898216] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22675.898287] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 09:52:45 BXT-2 kernel: [22675.898426] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22675.906840] PM: early resume of devices complete after 14.273 msecs >May 24 09:52:45 BXT-2 kernel: [22675.907673] r8169 0000:03:00.0: System wakeup disabled by ACPI >May 24 09:52:45 BXT-2 kernel: [22675.908451] ACPI : EC: event unblocked >May 24 09:52:45 BXT-2 kernel: [22675.909107] rtc_cmos 00:04: System wakeup disabled by ACPI >May 24 09:52:45 BXT-2 kernel: [22675.917581] sd 0:0:0:0: [sda] Starting disk >May 24 09:52:45 BXT-2 kernel: [22675.921638] r8169 0000:03:00.0 enp3s0: link down >May 24 09:52:45 BXT-2 kernel: [22676.018125] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 09:52:45 BXT-2 kernel: [22676.018219] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 09:52:45 BXT-2 kernel: [22676.018261] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 09:52:45 BXT-2 kernel: [22676.018338] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 09:52:45 BXT-2 kernel: [22676.018460] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38 >May 24 09:52:45 BXT-2 kernel: [22676.018755] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0 >May 24 09:52:45 BXT-2 kernel: [22676.018818] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 15 >May 24 09:52:45 BXT-2 kernel: [22676.018946] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0 >May 24 09:52:45 BXT-2 kernel: [22676.019054] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0 >May 24 09:52:45 BXT-2 kernel: [22676.019160] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0 >May 24 09:52:45 BXT-2 kernel: [22676.019243] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.019298] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 09:52:45 BXT-2 kernel: [22676.019387] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.019431] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: disabled >May 24 09:52:45 BXT-2 kernel: [22676.019481] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.019523] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 09:52:45 BXT-2 kernel: [22676.019573] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.019615] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 09:52:45 BXT-2 kernel: [22676.019663] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 09:52:45 BXT-2 kernel: [22676.019708] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 09:52:45 BXT-2 kernel: [22676.019753] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0 >May 24 09:52:45 BXT-2 kernel: [22676.019800] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 09:52:45 BXT-2 kernel: [22676.019844] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 09:52:45 BXT-2 kernel: [22676.019934] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 09:52:45 BXT-2 kernel: [22676.019978] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >May 24 09:52:45 BXT-2 kernel: [22676.020024] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI C] hw state readout: disabled, pipe A >May 24 09:52:45 BXT-2 kernel: [22676.020067] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A >May 24 09:52:45 BXT-2 kernel: [22676.020111] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B >May 24 09:52:45 BXT-2 kernel: [22676.020153] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C >May 24 09:52:45 BXT-2 kernel: [22676.020203] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:52:DP-1] hw state readout: disabled >May 24 09:52:45 BXT-2 kernel: [22676.020252] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-2] hw state readout: disabled >May 24 09:52:45 BXT-2 kernel: [22676.020305] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][setup_hw_state] >May 24 09:52:45 BXT-2 kernel: [22676.020349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.020390] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.020431] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.020439] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.020480] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.020485] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.020527] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.020570] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 09:52:45 BXT-2 kernel: [22676.020612] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 09:52:45 BXT-2 kernel: [22676.020653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.020695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.020742] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.020783] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.020824] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.020891] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.020933] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.020976] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.021020] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][setup_hw_state] >May 24 09:52:45 BXT-2 kernel: [22676.021062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.021103] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.021144] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.021149] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021190] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.021194] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021236] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021278] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 09:52:45 BXT-2 kernel: [22676.021319] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0 >May 24 09:52:45 BXT-2 kernel: [22676.021360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.021402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.021444] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021485] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.021529] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.021572] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.021615] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.021657] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.021701] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][setup_hw_state] >May 24 09:52:45 BXT-2 kernel: [22676.021742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.021784] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.021824] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.021853] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021895] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.021899] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021941] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.021983] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0 >May 24 09:52:45 BXT-2 kernel: [22676.022024] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0 >May 24 09:52:45 BXT-2 kernel: [22676.022067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.022109] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.022151] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0 >May 24 09:52:45 BXT-2 kernel: [22676.022192] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.022236] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.022277] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.022321] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.022488] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.022531] [drm:intel_power_well_disable [i915]] disabling dpio-common-a >May 24 09:52:45 BXT-2 kernel: [22676.022571] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.022625] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.022665] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.022709] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 09:52:45 BXT-2 kernel: [22676.022751] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 09:52:45 BXT-2 kernel: [22676.023318] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.023398] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 09:52:45 BXT-2 kernel: [22676.023440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 09:52:45 BXT-2 kernel: [22676.023486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 09:52:45 BXT-2 kernel: [22676.023528] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 09:52:45 BXT-2 kernel: [22676.023570] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 09:52:45 BXT-2 kernel: [22676.023613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.023654] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 09:52:45 BXT-2 kernel: [22676.023696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.023738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 09:52:45 BXT-2 kernel: [22676.023779] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.023820] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.023844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.023886] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.023891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.023933] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.023975] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 09:52:45 BXT-2 kernel: [22676.024016] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 09:52:45 BXT-2 kernel: [22676.024058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.024099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.024143] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 09:52:45 BXT-2 kernel: [22676.024184] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.024226] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.024267] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.024309] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.024350] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.024396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.024448] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.024490] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 09:52:45 BXT-2 kernel: [22676.024633] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.024669] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.024979] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 09:52:45 BXT-2 kernel: [22676.025033] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.025072] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.025127] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.025397] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.025711] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.025755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.025797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.025838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.025916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.025957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.025999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.026041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.026082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.026128] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:45 BXT-2 kernel: [22676.026175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.026220] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.026264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.026337] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 09:52:45 BXT-2 kernel: [22676.026381] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.027797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.027838] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.027913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 09:52:45 BXT-2 kernel: [22676.028691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.028732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.029473] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 09:52:45 BXT-2 kernel: [22676.029515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 09:52:45 BXT-2 kernel: [22676.030558] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 09:52:45 BXT-2 kernel: [22676.032666] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 09:52:45 BXT-2 kernel: [22676.033699] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 09:52:45 BXT-2 kernel: [22676.050608] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.050680] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 09:52:45 BXT-2 kernel: [22676.050928] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.051061] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 09:52:45 BXT-2 kernel: [22676.051136] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.051403] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:30 >May 24 09:52:45 BXT-2 kernel: [22676.051490] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:45 BXT-2 kernel: [22676.051507] [drm:drm_helper_hpd_irq_event] [CONNECTOR:52:DP-1] status updated from disconnected to disconnected >May 24 09:52:45 BXT-2 kernel: [22676.051572] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.051683] [drm:intel_opregion_register [i915]] 2 outputs detected >May 24 09:52:45 BXT-2 kernel: [22676.052533] PM: resume of devices complete after 145.683 msecs >May 24 09:52:45 BXT-2 kernel: [22676.054918] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 09:52:45 BXT-2 kernel: [22676.055186] PM: Finishing wakeup. >May 24 09:52:45 BXT-2 kernel: [22676.055280] OOM killer enabled. >May 24 09:52:45 BXT-2 kernel: [22676.055285] Restarting tasks ... >May 24 09:52:45 BXT-2 kernel: [22676.056211] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 09:52:45 BXT-2 kernel: [22676.056280] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 09:52:45 BXT-2 kernel: [22676.056344] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 09:52:45 BXT-2 kernel: [22676.056409] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 09:52:45 BXT-2 kernel: [22676.056998] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 09:52:45 BXT-2 kernel: [22676.057062] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 09:52:45 BXT-2 kernel: [22676.058972] done. >May 24 09:52:45 BXT-2 kernel: [22676.071155] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-2] status updated from connected to connected >May 24 09:52:45 BXT-2 kernel: [22676.079799] video LNXVIDEO:00: Restoring backlight state >May 24 09:52:45 BXT-2 kernel: [22676.082130] [drm:drm_mode_addfb2] [FB:66] >May 24 09:52:45 BXT-2 NetworkManager[793]: <info> [1495637565.2463] device (enp3s0): link disconnected >May 24 09:52:45 BXT-2 kernel: [22676.098440] [drm:drm_mode_setcrtc] [CRTC:34:pipe A] >May 24 09:52:45 BXT-2 kernel: [22676.098659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.098831] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 09:52:45 BXT-2 kernel: [22676.106205] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 09:52:45 BXT-2 kernel: [22676.106317] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.106406] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.106722] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.106766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.106809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.106852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.106965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.107014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.107067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.107111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.107154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.107202] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.107250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.107295] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.107341] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.107403] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.107446] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.107505] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.107567] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 09:52:45 BXT-2 kernel: [22676.107618] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.107662] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 09:52:45 BXT-2 kernel: [22676.107700] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 09:52:45 BXT-2 kernel: [22676.108888] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.110697] [drm:drm_mode_setcrtc] [CRTC:43:pipe B] >May 24 09:52:45 BXT-2 kernel: [22676.112595] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.112644] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.112760] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 09:52:45 BXT-2 kernel: [22676.112803] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 09:52:45 BXT-2 kernel: [22676.112848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 09:52:45 BXT-2 kernel: [22676.112923] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 09:52:45 BXT-2 kernel: [22676.112968] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 09:52:45 BXT-2 kernel: [22676.113016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.113062] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 09:52:45 BXT-2 kernel: [22676.113107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.113151] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 09:52:45 BXT-2 kernel: [22676.113196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.113240] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.113247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.113290] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.113296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.113340] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.113383] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 09:52:45 BXT-2 kernel: [22676.113427] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 09:52:45 BXT-2 kernel: [22676.113469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.113512] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.113557] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 09:52:45 BXT-2 kernel: [22676.113600] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.113650] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.113693] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.113736] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.113800] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.113872] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.113916] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 09:52:45 BXT-2 kernel: [22676.114487] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.114526] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.114823] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 09:52:45 BXT-2 kernel: [22676.114918] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.114958] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.115016] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.115265] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.115582] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.115627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.115670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.115712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.115755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.115803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.115849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.115961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.116006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.116049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.116099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.116144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.116220] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 09:52:45 BXT-2 kernel: [22676.116263] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.117700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.117745] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.117790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 09:52:45 BXT-2 kernel: [22676.118595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.118641] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.119464] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 09:52:45 BXT-2 kernel: [22676.119511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 09:52:45 BXT-2 kernel: [22676.120585] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 09:52:45 BXT-2 kernel: [22676.121929] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 09:52:45 BXT-2 kernel: [22676.123007] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 09:52:45 BXT-2 kernel: [22676.139971] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.140032] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.140256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.223657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.223887] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 09:52:45 BXT-2 kernel: [22676.226743] ata2: SATA link down (SStatus 4 SControl 300) >May 24 09:52:45 BXT-2 kernel: [22676.240365] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 09:52:45 BXT-2 kernel: [22676.240541] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.240702] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.241117] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.241216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.241312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.241407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.241504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.241599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.241704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.241800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.241894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.242108] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.242213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.242312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.242410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.242535] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.242627] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.242738] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.242865] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.243018] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.243117] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 09:52:45 BXT-2 kernel: [22676.243206] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 09:52:45 BXT-2 kernel: [22676.243833] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.246910] [drm:drm_mode_addfb2] [FB:64] >May 24 09:52:45 BXT-2 kernel: [22676.265849] [drm:drm_mode_setcrtc] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.265910] [drm:drm_mode_setcrtc] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.266038] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 09:52:45 BXT-2 kernel: [22676.266081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 09:52:45 BXT-2 kernel: [22676.266127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 09:52:45 BXT-2 kernel: [22676.266173] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 09:52:45 BXT-2 kernel: [22676.266214] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 09:52:45 BXT-2 kernel: [22676.266259] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.266303] [drm:intel_dump_pipe_config [i915]] [CRTC:50:pipe C][modeset] >May 24 09:52:45 BXT-2 kernel: [22676.266348] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.266390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 09:52:45 BXT-2 kernel: [22676.266432] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.266474] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.266484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.266525] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.266531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.266573] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.266618] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 09:52:45 BXT-2 kernel: [22676.266660] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1 >May 24 09:52:45 BXT-2 kernel: [22676.266702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.266744] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.266792] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 09:52:45 BXT-2 kernel: [22676.266834] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.266921] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 1C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.266973] [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 2C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.267020] [drm:intel_dump_pipe_config [i915]] [PLANE:48:cursor C] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.267084] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.267137] [drm:bxt_get_dpll [i915]] [CRTC:50:pipe C] using pre-allocated PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.267182] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C >May 24 09:52:45 BXT-2 kernel: [22676.267763] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.267802] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.268127] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 09:52:45 BXT-2 kernel: [22676.268184] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.268226] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.268283] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.268540] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.268922] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.268967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.269011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.269054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.269097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.269142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.269188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.269233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.269277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.269322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.269369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.269417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.269491] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 50 >May 24 09:52:45 BXT-2 kernel: [22676.269536] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.271012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.271057] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.271103] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 09:52:45 BXT-2 kernel: [22676.271940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.271982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.272728] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 09:52:45 BXT-2 kernel: [22676.272771] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 09:52:45 BXT-2 kernel: [22676.273829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 09:52:45 BXT-2 kernel: [22676.275947] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 09:52:45 BXT-2 kernel: [22676.276928] [drm:intel_enable_pipe [i915]] enabling pipe C >May 24 09:52:45 BXT-2 kernel: [22676.293864] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.293983] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.294195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.377477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 144000 kHz, actual 144000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.377668] [drm:intel_disable_pipe [i915]] disabling pipe C >May 24 09:52:45 BXT-2 kernel: [22676.387898] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 09:52:45 BXT-2 kernel: [22676.395410] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 50 >May 24 09:52:45 BXT-2 kernel: [22676.395576] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.395722] [drm:intel_set_cdclk [i915]] Changing CDCLK to 144000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.396143] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.396232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.396322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.396409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.396496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.396583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.396678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.396765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.396852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.397027] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.397131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.397230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.397330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.397455] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.397548] [drm:intel_power_well_disable [i915]] disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.397658] [drm:skl_set_power_well [i915]] Disabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.397785] [drm:intel_atomic_commit_tail [i915]] [CRTC:50:pipe C] >May 24 09:52:45 BXT-2 kernel: [22676.397878] [drm:intel_power_well_disable [i915]] disabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.398009] [drm:gen9_enable_dc5 [i915]] Enabling DC5 >May 24 09:52:45 BXT-2 kernel: [22676.398100] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01 >May 24 09:52:45 BXT-2 kernel: [22676.398699] [drm:intel_power_well_disable [i915]] disabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.404495] [drm] RC6 on >May 24 09:52:45 BXT-2 kernel: [22676.424970] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 09:52:45 BXT-2 kernel: [22676.425022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 09:52:45 BXT-2 kernel: [22676.425076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 09:52:45 BXT-2 kernel: [22676.425127] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 09:52:45 BXT-2 kernel: [22676.425177] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 09:52:45 BXT-2 kernel: [22676.425229] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.425284] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 09:52:45 BXT-2 kernel: [22676.425336] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 09:52:45 BXT-2 kernel: [22676.425387] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 09:52:45 BXT-2 kernel: [22676.425438] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:45 BXT-2 kernel: [22676.425488] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:45 BXT-2 kernel: [22676.425498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.425547] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:45 BXT-2 kernel: [22676.425553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.425604] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 09:52:45 BXT-2 kernel: [22676.425657] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 09:52:45 BXT-2 kernel: [22676.425707] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 09:52:45 BXT-2 kernel: [22676.425757] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:45 BXT-2 kernel: [22676.425807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:45 BXT-2 kernel: [22676.425861] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 09:52:45 BXT-2 kernel: [22676.425944] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:45 BXT-2 kernel: [22676.425995] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.426047] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.426098] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.426150] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 09:52:45 BXT-2 kernel: [22676.426205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 09:52:45 BXT-2 kernel: [22676.426268] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.426319] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A >May 24 09:52:45 BXT-2 kernel: [22676.426462] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 09:52:45 BXT-2 kernel: [22676.426505] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 09:52:45 BXT-2 kernel: [22676.426806] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00 >May 24 09:52:45 BXT-2 kernel: [22676.426897] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.426944] [drm:skl_set_power_well [i915]] Enabling power well 2 >May 24 09:52:45 BXT-2 kernel: [22676.427011] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 09:52:45 BXT-2 kernel: [22676.427295] [drm:intel_set_cdclk [i915]] Changing CDCLK to 288000 kHz, VCO 1152000 kHz, ref 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.427613] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz >May 24 09:52:45 BXT-2 kernel: [22676.427666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:45 BXT-2 kernel: [22676.427719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.427771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.427821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.427898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:45 BXT-2 kernel: [22676.427951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:45 BXT-2 kernel: [22676.428003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:45 BXT-2 kernel: [22676.428055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:45 BXT-2 kernel: [22676.428107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:45 BXT-2 kernel: [22676.428163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:45 BXT-2 kernel: [22676.428217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.428302] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 34 >May 24 09:52:45 BXT-2 kernel: [22676.428355] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.428896] ata1.00: configured for UDMA/133 >May 24 09:52:45 BXT-2 kernel: [22676.429867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.429989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.430046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 09:52:45 BXT-2 kernel: [22676.430938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:45 BXT-2 kernel: [22676.431002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:45 BXT-2 kernel: [22676.431820] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 09:52:45 BXT-2 kernel: [22676.431927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 09:52:45 BXT-2 kernel: [22676.433068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 09:52:45 BXT-2 kernel: [22676.435185] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 09:52:45 BXT-2 kernel: [22676.436820] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 09:52:45 BXT-2 kernel: [22676.453804] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:45 BXT-2 kernel: [22676.453916] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 09:52:45 BXT-2 kernel: [22676.454119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:45 BXT-2 kernel: [22676.454532] Console: switching to colour frame buffer device 240x67 >May 24 09:52:45 BXT-2 kernel: [22676.459265] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x1000181a, pins 0x00000020 >May 24 09:52:45 BXT-2 kernel: [22676.459333] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long >May 24 09:52:45 BXT-2 kernel: [22676.459398] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0 >May 24 09:52:45 BXT-2 kernel: [22676.459527] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long >May 24 09:52:45 BXT-2 kernel: [22676.459618] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions >May 24 09:52:45 BXT-2 kernel: [22676.459691] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event. >May 24 09:52:45 BXT-2 kernel: [22676.459760] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:45 BXT-2 kernel: [22676.460661] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 09:52:46 BXT-2 kernel: [22676.837058] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x10001819, pins 0x00000020 >May 24 09:52:46 BXT-2 kernel: [22676.837162] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short >May 24 09:52:46 BXT-2 kernel: [22676.837309] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short >May 24 09:52:46 BXT-2 kernel: [22676.838502] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 09:52:46 BXT-2 kernel: [22676.839825] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions >May 24 09:52:46 BXT-2 kernel: [22676.840027] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event. >May 24 09:52:46 BXT-2 kernel: [22676.840141] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:46 BXT-2 kernel: [22676.840815] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 09:52:46 BXT-2 kernel: [22676.842420] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 09:52:46 BXT-2 kernel: [22676.842535] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.842639] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.842743] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.843721] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 09:52:46 BXT-2 kernel: [22676.844410] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 09:52:46 BXT-2 kernel: [22676.845591] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.846965] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.848215] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.849531] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.850792] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.852049] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.853345] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.854622] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.855873] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.857249] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.858724] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.860115] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.861493] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.862911] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.864456] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.865863] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.867255] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.868487] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.869765] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.871041] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.872469] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.873876] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.875267] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.876646] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.878053] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.879487] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.880894] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.882456] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.883858] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.884652] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 09:52:46 BXT-2 kernel: [22676.885245] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:52:DP-1] status updated from disconnected to connected >May 24 09:52:46 BXT-2 kernel: [22676.885932] [drm:drm_fb_helper_hotplug_event] >May 24 09:52:46 BXT-2 kernel: [22676.885940] [drm:drm_setup_crtcs] >May 24 09:52:46 BXT-2 kernel: [22676.885951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] >May 24 09:52:46 BXT-2 kernel: [22676.886018] [drm:intel_dp_detect [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:46 BXT-2 kernel: [22676.886652] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 09:52:46 BXT-2 kernel: [22676.887801] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes >May 24 09:52:46 BXT-2 kernel: [22676.887859] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.887966] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.888214] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.888742] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 09:52:46 BXT-2 kernel: [22676.889372] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 09:52:46 BXT-2 kernel: [22676.890265] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.891633] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.892892] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.894143] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.895459] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.896730] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.897991] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.899243] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.900467] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.901861] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.903246] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.904614] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.906008] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.907461] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.908858] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.910241] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.911769] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.913060] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.914481] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.915756] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.917023] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.918484] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.919888] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.921321] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.922813] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.924249] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.925630] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.927043] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.928493] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:52:46 BXT-2 kernel: [22676.929301] [drm:drm_detect_monitor_audio] Monitor has basic audio support >May 24 09:52:46 BXT-2 kernel: [22676.930292] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz >May 24 09:52:46 BXT-2 kernel: [22676.930300] [drm:drm_edid_to_eld] ELD monitor ASUS VE258 >May 24 09:52:46 BXT-2 kernel: [22676.930307] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 >May 24 09:52:46 BXT-2 kernel: [22676.930312] [drm:drm_edid_to_eld] ELD size 36, SAD count 1 >May 24 09:52:46 BXT-2 kernel: [22676.930451] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:52:DP-1] probed modes : >May 24 09:52:46 BXT-2 kernel: [22676.930459] [drm:drm_mode_debug_printmodeline] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930466] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930472] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 09:52:46 BXT-2 kernel: [22676.930479] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 >May 24 09:52:46 BXT-2 kernel: [22676.930485] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930491] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 >May 24 09:52:46 BXT-2 kernel: [22676.930497] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9 >May 24 09:52:46 BXT-2 kernel: [22676.930504] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930510] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930516] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9 >May 24 09:52:46 BXT-2 kernel: [22676.930523] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930529] [drm:drm_mode_debug_printmodeline] Modeline 85:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930535] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930542] [drm:drm_mode_debug_printmodeline] Modeline 120:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930548] [drm:drm_mode_debug_printmodeline] Modeline 83:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930554] [drm:drm_mode_debug_printmodeline] Modeline 114:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930561] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930567] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930573] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930580] [drm:drm_mode_debug_printmodeline] Modeline 127:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930586] [drm:drm_mode_debug_printmodeline] Modeline 112:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930592] [drm:drm_mode_debug_printmodeline] Modeline 100:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930598] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930605] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930611] [drm:drm_mode_debug_printmodeline] Modeline 90:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930617] [drm:drm_mode_debug_printmodeline] Modeline 91:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.930624] [drm:drm_mode_debug_printmodeline] Modeline 84:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930630] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930636] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930642] [drm:drm_mode_debug_printmodeline] Modeline 92:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930649] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930655] [drm:drm_mode_debug_printmodeline] Modeline 121:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930661] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.930667] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 09:52:46 BXT-2 kernel: [22676.930677] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] >May 24 09:52:46 BXT-2 kernel: [22676.930746] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:46 BXT-2 kernel: [22676.931961] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00 >May 24 09:52:46 BXT-2 kernel: [22676.932911] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no >May 24 09:52:46 BXT-2 kernel: [22676.933153] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 >May 24 09:52:46 BXT-2 kernel: [22676.933205] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000 >May 24 09:52:46 BXT-2 kernel: [22676.933256] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000 >May 24 09:52:46 BXT-2 kernel: [22676.933785] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00(NS) dev-ID HW-rev 0.0 SW-rev 0.0 >May 24 09:52:46 BXT-2 kernel: [22676.933837] [drm:intel_dp_detect [i915]] Sink is not MST capable >May 24 09:52:46 BXT-2 kernel: [22676.938803] [drm:drm_edid_to_eld] ELD: no CEA Extension found >May 24 09:52:46 BXT-2 kernel: [22676.939121] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-2] probed modes : >May 24 09:52:46 BXT-2 kernel: [22676.939129] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939135] [drm:drm_mode_debug_printmodeline] Modeline 70:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939140] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939145] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939150] [drm:drm_mode_debug_printmodeline] Modeline 68:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939155] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939161] [drm:drm_mode_debug_printmodeline] Modeline 77:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.939166] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939171] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.939176] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.939181] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa >May 24 09:52:46 BXT-2 kernel: [22676.939186] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 >May 24 09:52:46 BXT-2 kernel: [22676.939213] [drm:drm_setup_crtcs] connector 52 enabled? yes >May 24 09:52:46 BXT-2 kernel: [22676.939217] [drm:drm_setup_crtcs] connector 59 enabled? yes >May 24 09:52:46 BXT-2 kernel: [22676.939279] [drm:intel_fb_initial_config [i915]] Not using firmware configuration >May 24 09:52:46 BXT-2 kernel: [22676.939290] [drm:drm_setup_crtcs] looking for cmdline mode on connector 52 >May 24 09:52:46 BXT-2 kernel: [22676.939295] [drm:drm_setup_crtcs] looking for preferred mode on connector 52 0 >May 24 09:52:46 BXT-2 kernel: [22676.939299] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 09:52:46 BXT-2 kernel: [22676.939302] [drm:drm_setup_crtcs] looking for cmdline mode on connector 59 >May 24 09:52:46 BXT-2 kernel: [22676.939306] [drm:drm_setup_crtcs] looking for preferred mode on connector 59 0 >May 24 09:52:46 BXT-2 kernel: [22676.939310] [drm:drm_setup_crtcs] found mode 1920x1080 >May 24 09:52:46 BXT-2 kernel: [22676.939314] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config >May 24 09:52:46 BXT-2 kernel: [22676.939370] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 34 (0,0) >May 24 09:52:46 BXT-2 kernel: [22676.939381] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 43 (0,0) >May 24 09:52:46 BXT-2 kernel: [22676.939649] [drm:intel_atomic_check [i915]] [CONNECTOR:52:DP-1] checking for sink bpp constrains >May 24 09:52:46 BXT-2 kernel: [22676.939693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24 >May 24 09:52:46 BXT-2 kernel: [22676.939738] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz >May 24 09:52:46 BXT-2 kernel: [22676.939782] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24 >May 24 09:52:46 BXT-2 kernel: [22676.939824] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000 >May 24 09:52:46 BXT-2 kernel: [22676.939958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 09:52:46 BXT-2 kernel: [22676.940006] [drm:intel_dump_pipe_config [i915]] [CRTC:34:pipe A][modeset] >May 24 09:52:46 BXT-2 kernel: [22676.940053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 >May 24 09:52:46 BXT-2 kernel: [22676.940098] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 180224, gmch_n: 262144, link_m: 60074, link_n: 65536, tu: 64 >May 24 09:52:46 BXT-2 kernel: [22676.940584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0 >May 24 09:52:46 BXT-2 kernel: [22676.940628] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:46 BXT-2 kernel: [22676.940637] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.940679] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:46 BXT-2 kernel: [22676.940688] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.940732] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.940778] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500 >May 24 09:52:46 BXT-2 kernel: [22676.940821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 09:52:46 BXT-2 kernel: [22676.940909] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:46 BXT-2 kernel: [22676.940955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:46 BXT-2 kernel: [22676.941004] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 09:52:46 BXT-2 kernel: [22676.941050] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:46 BXT-2 kernel: [22676.941098] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:78, fb = 1920x1080 format = XR24 little-endian (0x34325258) >May 24 09:52:46 BXT-2 kernel: [22676.941145] [drm:intel_dump_pipe_config [i915]] scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080 >May 24 09:52:46 BXT-2 kernel: [22676.941434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.941478] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.941522] [drm:intel_dump_pipe_config [i915]] [PLANE:32:cursor A] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.941577] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-2] checking for sink bpp constrains >May 24 09:52:46 BXT-2 kernel: [22676.941622] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24 >May 24 09:52:46 BXT-2 kernel: [22676.941669] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz >May 24 09:52:46 BXT-2 kernel: [22676.941713] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 >May 24 09:52:46 BXT-2 kernel: [22676.941756] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 540000 >May 24 09:52:46 BXT-2 kernel: [22676.941802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0 >May 24 09:52:46 BXT-2 kernel: [22676.941846] [drm:intel_dump_pipe_config [i915]] [CRTC:43:pipe B][modeset] >May 24 09:52:46 BXT-2 kernel: [22676.941916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 >May 24 09:52:46 BXT-2 kernel: [22676.941963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 216268, gmch_n: 262144, link_m: 72089, link_n: 131072, tu: 64 >May 24 09:52:46 BXT-2 kernel: [22676.942010] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0 >May 24 09:52:46 BXT-2 kernel: [22676.942056] [drm:intel_dump_pipe_config [i915]] requested mode: >May 24 09:52:46 BXT-2 kernel: [22676.942068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.942112] [drm:intel_dump_pipe_config [i915]] adjusted mode: >May 24 09:52:46 BXT-2 kernel: [22676.942120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.942165] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5 >May 24 09:52:46 BXT-2 kernel: [22676.942388] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500 >May 24 09:52:46 BXT-2 kernel: [22676.942431] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 >May 24 09:52:46 BXT-2 kernel: [22676.942475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled >May 24 09:52:46 BXT-2 kernel: [22676.942518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 >May 24 09:52:46 BXT-2 kernel: [22676.942564] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d >May 24 09:52:46 BXT-2 kernel: [22676.942607] [drm:intel_dump_pipe_config [i915]] planes on this crtc >May 24 09:52:46 BXT-2 kernel: [22676.942654] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 1B] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.942698] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2B] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.942743] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 3B] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.942787] [drm:intel_dump_pipe_config [i915]] [PLANE:41:cursor B] disabled, scaler_id = -1 >May 24 09:52:46 BXT-2 kernel: [22676.942835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 288000 kHz, actual 288000 kHz >May 24 09:52:46 BXT-2 kernel: [22676.942918] [drm:bxt_get_dpll [i915]] [CRTC:34:pipe A] using pre-allocated PORT PLL B >May 24 09:52:46 BXT-2 kernel: [22676.942963] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe A >May 24 09:52:46 BXT-2 kernel: [22676.943010] [drm:bxt_get_dpll [i915]] [CRTC:43:pipe B] using pre-allocated PORT PLL C >May 24 09:52:46 BXT-2 kernel: [22676.943055] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B >May 24 09:52:46 BXT-2 kernel: [22676.943478] [drm:intel_disable_pipe [i915]] disabling pipe A >May 24 09:52:46 BXT-2 kernel: [22676.953923] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 34 >May 24 09:52:46 BXT-2 kernel: [22676.954035] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C >May 24 09:52:46 BXT-2 kernel: [22676.954097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DDI B] >May 24 09:52:46 BXT-2 kernel: [22676.954140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST A] >May 24 09:52:46 BXT-2 kernel: [22676.954182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST B] >May 24 09:52:46 BXT-2 kernel: [22676.954225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DP-MST C] >May 24 09:52:46 BXT-2 kernel: [22676.954267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI C] >May 24 09:52:46 BXT-2 kernel: [22676.954310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A] >May 24 09:52:46 BXT-2 kernel: [22676.954354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B] >May 24 09:52:46 BXT-2 kernel: [22676.954398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C] >May 24 09:52:46 BXT-2 kernel: [22676.954441] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A >May 24 09:52:46 BXT-2 kernel: [22676.954486] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:46 BXT-2 kernel: [22676.954531] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:46 BXT-2 kernel: [22676.954603] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 1, on? 0) for crtc 34 >May 24 09:52:46 BXT-2 kernel: [22676.954645] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B >May 24 09:52:46 BXT-2 kernel: [22676.956246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:46 BXT-2 kernel: [22676.956291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:46 BXT-2 kernel: [22676.956335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 09:52:46 BXT-2 kernel: [22676.975468] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 09:52:46 BXT-2 kernel: [22676.975513] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 >May 24 09:52:46 BXT-2 kernel: [22676.993730] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 09:52:46 BXT-2 kernel: [22676.995890] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4 >May 24 09:52:46 BXT-2 kernel: [22676.996961] [drm:intel_enable_pipe [i915]] enabling pipe A >May 24 09:52:46 BXT-2 kernel: [22676.997029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:52:DP-1], [ENCODER:51:DDI B] >May 24 09:52:46 BXT-2 kernel: [22676.997073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD >May 24 09:52:46 BXT-2 kernel: [22676.997129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud >May 24 09:52:46 BXT-2 kernel: [22677.013808] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 43 >May 24 09:52:46 BXT-2 kernel: [22677.013896] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C >May 24 09:52:46 BXT-2 kernel: [22677.015560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 >May 24 09:52:46 BXT-2 kernel: [22677.015607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 >May 24 09:52:46 BXT-2 kernel: [22677.015653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 >May 24 09:52:46 BXT-2 kernel: [22677.016617] [drm:intel_dp_start_link_train [i915]] clock recovery OK >May 24 09:52:46 BXT-2 kernel: [22677.016663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2 >May 24 09:52:46 BXT-2 kernel: [22677.017919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful >May 24 09:52:46 BXT-2 kernel: [22677.020050] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2 >May 24 09:52:46 BXT-2 kernel: [22677.021603] [drm:intel_enable_pipe [i915]] enabling pipe B >May 24 09:52:46 BXT-2 kernel: [22677.038563] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:52:DP-1] >May 24 09:52:46 BXT-2 kernel: [22677.038665] [drm:intel_atomic_commit_tail [i915]] [CRTC:34:pipe A] >May 24 09:52:46 BXT-2 kernel: [22677.039169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B >May 24 09:52:46 BXT-2 kernel: [22677.039409] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:59:DP-2] >May 24 09:52:46 BXT-2 kernel: [22677.039493] [drm:intel_atomic_commit_tail [i915]] [CRTC:43:pipe B] >May 24 09:52:46 BXT-2 kernel: [22677.039705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C >May 24 09:52:48 BXT-2 kernel: [22679.354055] r8169 0000:03:00.0 enp3s0: link up >May 24 09:52:48 BXT-2 NetworkManager[793]: <info> [1495637568.5401] device (enp3s0): link connected >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Linux version 4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ (gfx@bifrost) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4) ) #1 SMP PREEMPT Wed May 24 08:04:21 CDT 2017 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0xe auto panic=1 nmi_watchdog=panic resume=/dev/sda3 fastboot >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: xstate_offset[3]: 576, xstate_sizes[3]: 64 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: xstate_offset[4]: 640, xstate_sizes[4]: 64 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 704 bytes, using 'compacted' format. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] e820: BIOS-provided physical RAM map: >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000003efff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000000003f000-0x000000000003ffff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000040000-0x000000000009dfff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000012151000-0x0000000077716fff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000077717000-0x0000000079838fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079839000-0x0000000079853fff] ACPI data >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079854000-0x00000000798b3fff] ACPI NVS >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000798b4000-0x0000000079bdefff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079bdf000-0x0000000079c43fff] type 20 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079c44000-0x0000000079fc5fff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079fc6000-0x0000000079fc6fff] ACPI NVS >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079fc7000-0x0000000079ff0fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000079ff1000-0x000000007a9defff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007a9df000-0x000000007a9e0fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007a9e1000-0x000000007affffff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000d0000000-0x00000000d0ffffff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fe042000-0x00000000fe044fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fe900000-0x00000000fe902fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000047fffffff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] tsc: Using PIT calibration value >May 24 09:53:41 BXT-2 kernel: [ 0.000000] NX (Execute Disable) protection: active >May 24 09:53:41 BXT-2 kernel: [ 0.000000] efi: EFI v2.50 by American Megatrends >May 24 09:53:41 BXT-2 kernel: [ 0.000000] efi: ACPI=0x79846000 ACPI 2.0=0x79846000 SMBIOS=0x79aa8000 SMBIOS 3.0=0x79aa7000 ESRT=0x79aa2a58 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] SMBIOS 3.0.0 present. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMI: Intel corporation NUC6CAYS/NUC6CAYB, BIOS AYAPLCEL.86A.0038.2017.0310.1633 03/10/2017 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] e820: last_pfn = 0x480000 max_arch_pfn = 0x400000000 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] MTRR default type: uncachable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] MTRR fixed ranges enabled: >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 00000-6FFFF write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 70000-7FFFF uncachable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 80000-9FFFF write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] A0000-BFFFF uncachable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] C0000-FFFFF write-protect >May 24 09:53:41 BXT-2 kernel: [ 0.000000] MTRR variable ranges enabled: >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 0 base 0000000000 mask 7F80000000 write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 1 base 007C000000 mask 7FFC000000 uncachable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 2 base 007B000000 mask 7FFF000000 uncachable >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 3 base 0100000000 mask 7F00000000 write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 4 base 0200000000 mask 7F00000000 write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 5 base 0300000000 mask 7F00000000 write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 6 base 0400000000 mask 7F80000000 write-back >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 7 base 00FF000000 mask 7FFF000000 write-combining >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 8 disabled >May 24 09:53:41 BXT-2 kernel: [ 0.000000] 9 disabled >May 24 09:53:41 BXT-2 kernel: [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT >May 24 09:53:41 BXT-2 kernel: [ 0.000000] e820: last_pfn = 0x7b000 max_arch_pfn = 0x400000000 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] esrt: Reserving ESRT space from 0x0000000079aa2a58 to 0x0000000079aa2a90. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Using GB pages for direct mapping >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BRK [0x056c2000, 0x056c2fff] PGTABLE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BRK [0x056c3000, 0x056c3fff] PGTABLE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BRK [0x056c4000, 0x056c4fff] PGTABLE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BRK [0x056c5000, 0x056c5fff] PGTABLE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BRK [0x056c6000, 0x056c6fff] PGTABLE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] BRK [0x056c7000, 0x056c7fff] PGTABLE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Secure boot could not be determined >May 24 09:53:41 BXT-2 kernel: [ 0.000000] RAMDISK: [mem 0x369f4000-0x374f1fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: Early table checksum verification disabled >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: RSDP 0x0000000079846000 000024 (v02 INTEL ) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: XSDT 0x00000000798460D0 0000FC (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: FACP 0x000000007984EF60 000114 (v06 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: DSDT 0x0000000079846260 008CF8 (v02 INTEL NUC6CAYB 01072009 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: FACS 0x0000000079883080 000040 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: FPDT 0x000000007984F080 000044 (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: FIDT 0x000000007984F0D0 00009C (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: MCFG 0x000000007984F170 00003C (v01 INTEL NUC6CAYB 01072009 MSFT 00000097) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: DBG2 0x000000007984F1B0 000072 (v00 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: DBGP 0x000000007984F230 000034 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: HPET 0x000000007984F270 000038 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: LPIT 0x000000007984F2B0 00005C (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: APIC 0x000000007984F310 000084 (v03 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: NPKT 0x000000007984F3A0 000065 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: PRAM 0x000000007984F410 000030 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: WSMT 0x000000007984F440 000028 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x000000007984F470 00002B (v02 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x000000007984F4A0 000A19 (v01 INTEL NUC6CAYB 00001000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x000000007984FEC0 000442 (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850310 00072B (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850A40 00032D (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850D70 00017C (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079850EF0 002740 (v02 INTEL NUC6CAYB 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: UEFI 0x0000000079853630 000042 (v01 INTEL NUC6CAYB 00000000 00000000) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: BGRT 0x0000000079853680 000038 (v01 INTEL NUC6CAYB 01072009 AMI 00010013) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: TPM2 0x00000000798536C0 000034 (v03 INTEL NUC6CAYB 00000001 AMI 00000000) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: SSDT 0x0000000079853700 0001F8 (v01 INTEL NUC6CAYB 00001000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: MSDM 0x0000000079853900 000055 (v03 INTEL NUC6CAYB 01072009 AMI AFAFAFAF) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: DMAR 0x0000000079853960 0000A8 (v01 INTEL NUC6CAYB 00000003 BRXT 0100000D) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: WDAT 0x0000000079853A10 000104 (v01 INTEL NUC6CAYB 00000000 00000000) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: NHLT 0x0000000079853B20 00002D (v00 INTEL NUC6CAYB 00000002 01000013) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Zone ranges: >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Normal [mem 0x0000000100000000-0x000000047fffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Movable zone start for each node >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Early memory node ranges >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000000001000-0x000000000003efff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000000040000-0x000000000009dfff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000000100000-0x000000000fffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000012151000-0x0000000077716fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000079c44000-0x0000000079fc5fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000079ff1000-0x000000007a9defff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x000000007a9e1000-0x000000007affffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] node 0: [mem 0x0000000100000000-0x000000047fffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000047fffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] On node 0 totalpages: 4155633 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA zone: 64 pages used for memmap >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA zone: 22 pages reserved >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA zone: 3996 pages, LIFO batch:0 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA32 zone: 7526 pages used for memmap >May 24 09:53:41 BXT-2 kernel: [ 0.000000] DMA32 zone: 481621 pages, LIFO batch:31 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Normal zone: 57344 pages used for memmap >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Normal zone: 3670016 pages, LIFO batch:31 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Reserving Intel graphics memory at 0x000000007c000000-0x000000007fffffff >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: PM-Timer IO Port: 0x408 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1]) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1]) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1]) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1]) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: IRQ0 used by override. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: IRQ9 used by override. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Using ACPI (MADT) for SMP configuration information >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x0003f000-0x0003ffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x10000000-0x12150fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x77717000-0x79838fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79839000-0x79853fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79854000-0x798b3fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x798b4000-0x79bdefff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79bdf000-0x79c43fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79fc6000-0x79fc6fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x79fc7000-0x79ff0fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x7a9df000-0x7a9e0fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x80000000-0xcfffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xd0000000-0xd0ffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xd1000000-0xdfffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfe041fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe042000-0xfe044fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe045000-0xfe8fffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe900000-0xfe902fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfe903000-0xfebfffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfed00fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xfedfffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff] >May 24 09:53:41 BXT-2 kernel: [ 0.000000] e820: [mem 0x80000000-0xcfffffff] available for PCI devices >May 24 09:53:41 BXT-2 kernel: [ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns >May 24 09:53:41 BXT-2 kernel: [ 0.000000] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] percpu: Embedded 37 pages/cpu @ffff88047fc00000 s114376 r8192 d28984 u524288 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] pcpu-alloc: s114376 r8192 d28984 u524288 alloc=1*2097152 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] pcpu-alloc: [0] 0 1 2 3 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 4090677 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0xe auto panic=1 nmi_watchdog=panic resume=/dev/sda3 fastboot >May 24 09:53:41 BXT-2 kernel: [ 0.000000] log_buf_len individual max cpu contribution: 262144 bytes >May 24 09:53:41 BXT-2 kernel: [ 0.000000] log_buf_len total cpu_extra contributions: 786432 bytes >May 24 09:53:41 BXT-2 kernel: [ 0.000000] log_buf_len min size: 262144 bytes >May 24 09:53:41 BXT-2 kernel: [ 0.000000] log_buf_len: 1048576 bytes >May 24 09:53:41 BXT-2 kernel: [ 0.000000] early log buf free: 247796(94%) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Memory: 16128012K/16622532K available (8664K kernel code, 1377K rwdata, 3444K rodata, 1200K init, 22640K bss, 494520K reserved, 0K cma-reserved) >May 24 09:53:41 BXT-2 kernel: [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Running RCU self tests >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Preemptible hierarchical RCU implementation. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] RCU lockdep checking is enabled. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4. >May 24 09:53:41 BXT-2 kernel: [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] kmemleak: Kernel memory leak detector disabled >May 24 09:53:41 BXT-2 kernel: [ 0.000000] NR_IRQS:4352 nr_irqs:1024 16 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Console: colour dummy device 80x25 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] console [tty0] enabled >May 24 09:53:41 BXT-2 kernel: [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... MAX_LOCK_DEPTH: 48 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... CLASSHASH_SIZE: 4096 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 32768 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... MAX_LOCKDEP_CHAINS: 65536 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] ... CHAINHASH_SIZE: 32768 >May 24 09:53:41 BXT-2 kernel: [ 0.000000] memory used by lock dependency info: 8159 kB >May 24 09:53:41 BXT-2 kernel: [ 0.000000] per task-struct memory footprint: 1920 bytes >May 24 09:53:41 BXT-2 kernel: [ 0.000000] kmemleak: Early log buffer exceeded (2891), please increase DEBUG_KMEMLEAK_EARLY_LOG_SIZE >May 24 09:53:41 BXT-2 kernel: [ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns >May 24 09:53:41 BXT-2 kernel: [ 0.000000] hpet clockevent registered >May 24 09:53:41 BXT-2 kernel: [ 0.002000] tsc: PIT calibration matches HPET. 1 loops >May 24 09:53:41 BXT-2 kernel: [ 0.002000] tsc: Detected 1497.624 MHz processor >May 24 09:53:41 BXT-2 kernel: [ 0.002000] Calibrating delay loop (skipped), value calculated using timer frequency.. 2995.20 BogoMIPS (lpj=1497600) >May 24 09:53:41 BXT-2 kernel: [ 0.002000] pid_max: default: 32768 minimum: 301 >May 24 09:53:41 BXT-2 kernel: [ 0.002000] ACPI: Core revision 20170303 >May 24 09:53:41 BXT-2 kernel: [ 0.201822] ACPI: 9 ACPI AML tables successfully acquired and loaded >May 24 09:53:41 BXT-2 kernel: [ 0.203267] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.203276] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.204955] CPU: Physical Processor ID: 0 >May 24 09:53:41 BXT-2 kernel: [ 0.205012] CPU: Processor Core ID: 0 >May 24 09:53:41 BXT-2 kernel: [ 0.205040] mce: CPU supports 7 MCE banks >May 24 09:53:41 BXT-2 kernel: [ 0.205104] CPU0: Thermal monitoring enabled (TM1) >May 24 09:53:41 BXT-2 kernel: [ 0.205196] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0 >May 24 09:53:41 BXT-2 kernel: [ 0.205200] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 >May 24 09:53:41 BXT-2 kernel: [ 0.205786] Freeing SMP alternatives memory: 32K >May 24 09:53:41 BXT-2 kernel: [ 0.233585] smpboot: Max logical packages: 1 >May 24 09:53:41 BXT-2 kernel: [ 0.233604] DMAR: Host address width 39 >May 24 09:53:41 BXT-2 kernel: [ 0.233610] DMAR: DRHD base: 0x000000fed64000 flags: 0x0 >May 24 09:53:41 BXT-2 kernel: [ 0.233685] DMAR: dmar0: reg_base_addr fed64000 ver 1:0 cap 1c0000c40660462 ecap 7e3ff0505e >May 24 09:53:41 BXT-2 kernel: [ 0.233690] DMAR: DRHD base: 0x000000fed65000 flags: 0x1 >May 24 09:53:41 BXT-2 kernel: [ 0.233737] DMAR: dmar1: reg_base_addr fed65000 ver 1:0 cap d2008c40660462 ecap f050da >May 24 09:53:41 BXT-2 kernel: [ 0.233743] DMAR: RMRR base: 0x000000797d4000 end: 0x000000797f3fff >May 24 09:53:41 BXT-2 kernel: [ 0.233764] DMAR: RMRR base: 0x0000007b800000 end: 0x0000007fffffff >May 24 09:53:41 BXT-2 kernel: [ 0.233784] DMAR-IR: IOAPIC id 1 under DRHD base 0xfed65000 IOMMU 1 >May 24 09:53:41 BXT-2 kernel: [ 0.233789] DMAR-IR: HPET id 0 under DRHD base 0xfed65000 >May 24 09:53:41 BXT-2 kernel: [ 0.233793] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping. >May 24 09:53:41 BXT-2 kernel: [ 0.236168] DMAR-IR: Enabled IRQ remapping in x2apic mode >May 24 09:53:41 BXT-2 kernel: [ 0.236175] x2apic enabled >May 24 09:53:41 BXT-2 kernel: [ 0.236199] Switched APIC routing to cluster x2apic. >May 24 09:53:41 BXT-2 kernel: [ 0.242000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 >May 24 09:53:41 BXT-2 kernel: [ 0.251145] TSC deadline timer enabled >May 24 09:53:41 BXT-2 kernel: [ 0.251168] smpboot: CPU0: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz (family: 0x6, model: 0x5c, stepping: 0x9) >May 24 09:53:41 BXT-2 kernel: [ 0.255097] Performance Events: PEBS fmt3+, Goldmont events, 32-deep LBR, full-width counters, Intel PMU driver. >May 24 09:53:41 BXT-2 kernel: [ 0.255153] ... version: 4 >May 24 09:53:41 BXT-2 kernel: [ 0.255157] ... bit width: 48 >May 24 09:53:41 BXT-2 kernel: [ 0.255160] ... generic registers: 4 >May 24 09:53:41 BXT-2 kernel: [ 0.255165] ... value mask: 0000ffffffffffff >May 24 09:53:41 BXT-2 kernel: [ 0.255168] ... max period: 00007fffffffffff >May 24 09:53:41 BXT-2 kernel: [ 0.255172] ... fixed-purpose events: 3 >May 24 09:53:41 BXT-2 kernel: [ 0.255175] ... event mask: 000000070000000f >May 24 09:53:41 BXT-2 kernel: [ 0.263746] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. >May 24 09:53:41 BXT-2 kernel: [ 0.265023] smp: Bringing up secondary CPUs ... >May 24 09:53:41 BXT-2 kernel: [ 0.273202] x86: Booting SMP configuration: >May 24 09:53:41 BXT-2 kernel: [ 0.273215] .... node #0, CPUs: #1 #2 #3 >May 24 09:53:41 BXT-2 kernel: [ 0.469284] smp: Brought up 1 node, 4 CPUs >May 24 09:53:41 BXT-2 kernel: [ 0.469284] smpboot: Total of 4 processors activated (12087.00 BogoMIPS) >May 24 09:53:41 BXT-2 kernel: [ 0.470801] sched_clock: Marking stable (470000000, 0)->(472839693, -2839693) >May 24 09:53:41 BXT-2 kernel: [ 0.472814] devtmpfs: initialized >May 24 09:53:41 BXT-2 kernel: [ 0.475196] PM: Registering ACPI NVS region [mem 0x79854000-0x798b3fff] (393216 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.475655] PM: Registering ACPI NVS region [mem 0x79fc6000-0x79fc6fff] (4096 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.477750] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns >May 24 09:53:41 BXT-2 kernel: [ 0.477765] futex hash table entries: 1024 (order: 5, 131072 bytes) >May 24 09:53:41 BXT-2 kernel: [ 0.478233] xor: measuring software checksum speed >May 24 09:53:41 BXT-2 kernel: [ 0.488219] prefetch64-sse: 7536.000 MB/sec >May 24 09:53:41 BXT-2 kernel: [ 0.498285] generic_sse: 6484.000 MB/sec >May 24 09:53:41 BXT-2 kernel: [ 0.498290] xor: using function: prefetch64-sse (7536.000 MB/sec) >May 24 09:53:41 BXT-2 kernel: [ 0.498325] pinctrl core: initialized pinctrl subsystem >May 24 09:53:41 BXT-2 kernel: [ 0.503866] NET: Registered protocol family 16 >May 24 09:53:41 BXT-2 kernel: [ 0.506809] cpuidle: using governor menu >May 24 09:53:41 BXT-2 kernel: [ 0.506821] PCCT header not found. >May 24 09:53:41 BXT-2 kernel: [ 0.507135] ACPI: bus type PCI registered >May 24 09:53:41 BXT-2 kernel: [ 0.507718] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) >May 24 09:53:41 BXT-2 kernel: [ 0.507727] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 >May 24 09:53:41 BXT-2 kernel: [ 0.507787] PCI: Using configuration type 1 for base access >May 24 09:53:41 BXT-2 kernel: [ 0.534481] HugeTLB registered 2 MB page size, pre-allocated 0 pages >May 24 09:53:41 BXT-2 kernel: [ 0.552891] raid6: sse2x1 gen() 3230 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.570062] raid6: sse2x1 xor() 1951 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.587259] raid6: sse2x2 gen() 3742 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.604436] raid6: sse2x2 xor() 2287 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.621623] raid6: sse2x4 gen() 4269 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.638806] raid6: sse2x4 xor() 2261 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.638811] raid6: using algorithm sse2x4 gen() 4269 MB/s >May 24 09:53:41 BXT-2 kernel: [ 0.638815] raid6: .... xor() 2261 MB/s, rmw enabled >May 24 09:53:41 BXT-2 kernel: [ 0.638819] raid6: using ssse3x2 recovery algorithm >May 24 09:53:41 BXT-2 kernel: [ 0.639214] ACPI: Added _OSI(Module Device) >May 24 09:53:41 BXT-2 kernel: [ 0.639219] ACPI: Added _OSI(Processor Device) >May 24 09:53:41 BXT-2 kernel: [ 0.639224] ACPI: Added _OSI(3.0 _SCP Extensions) >May 24 09:53:41 BXT-2 kernel: [ 0.639229] ACPI: Added _OSI(Processor Aggregator Device) >May 24 09:53:41 BXT-2 kernel: [ 0.643417] ACPI: Executed 3 blocks of module-level executable AML code >May 24 09:53:41 BXT-2 kernel: [ 0.778265] ACPI: Dynamic OEM Table Load: >May 24 09:53:41 BXT-2 kernel: [ 0.778325] ACPI: SSDT 0xFFFF88046CE8A7C8 000102 (v02 PmRef Cpu0Cst 00003001 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.786562] ACPI: Dynamic OEM Table Load: >May 24 09:53:41 BXT-2 kernel: [ 0.786618] ACPI: SSDT 0xFFFF88046CE89A88 00015F (v02 PmRef ApIst 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.790577] ACPI: Dynamic OEM Table Load: >May 24 09:53:41 BXT-2 kernel: [ 0.790632] ACPI: SSDT 0xFFFF88046CEAEB58 00008D (v02 PmRef ApCst 00003000 INTL 20120913) >May 24 09:53:41 BXT-2 kernel: [ 0.812935] ACPI : EC: EC started >May 24 09:53:41 BXT-2 kernel: [ 0.812946] ACPI : EC: interrupt blocked >May 24 09:53:41 BXT-2 kernel: [ 0.813423] ACPI: \_SB_.PCI0.SBRG.H_EC: Used as first EC >May 24 09:53:41 BXT-2 kernel: [ 0.813441] ACPI: \_SB_.PCI0.SBRG.H_EC: GPE=0x40, EC_CMD/EC_SC=0x66, EC_DATA=0x62 >May 24 09:53:41 BXT-2 kernel: [ 0.813457] ACPI: \_SB_.PCI0.SBRG.H_EC: Used as boot DSDT EC to handle transactions >May 24 09:53:41 BXT-2 kernel: [ 0.813465] ACPI: Interpreter enabled >May 24 09:53:41 BXT-2 kernel: [ 0.813703] ACPI: (supports S0 S3 S4 S5) >May 24 09:53:41 BXT-2 kernel: [ 0.813709] ACPI: Using IOAPIC for interrupt routing >May 24 09:53:41 BXT-2 kernel: [ 0.814164] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug >May 24 09:53:41 BXT-2 kernel: [ 1.001370] ACPI: Power Resource [FN00] (on) >May 24 09:53:41 BXT-2 kernel: [ 1.019567] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) >May 24 09:53:41 BXT-2 kernel: [ 1.019602] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] >May 24 09:53:41 BXT-2 kernel: [ 1.036754] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] >May 24 09:53:41 BXT-2 kernel: [ 1.040912] PCI host bridge to bus 0000:00 >May 24 09:53:41 BXT-2 kernel: [ 1.040925] pci_bus 0000:00: root bus resource [io 0x0070-0x0077] >May 24 09:53:41 BXT-2 kernel: [ 1.040935] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window] >May 24 09:53:41 BXT-2 kernel: [ 1.040945] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window] >May 24 09:53:41 BXT-2 kernel: [ 1.040954] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.040963] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.040973] pci_bus 0000:00: root bus resource [mem 0x7b800001-0x7bffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.040991] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.041001] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.041013] pci_bus 0000:00: root bus resource [bus 00-ff] >May 24 09:53:41 BXT-2 kernel: [ 1.041094] pci 0000:00:00.0: [8086:5af0] type 00 class 0x060000 >May 24 09:53:41 BXT-2 kernel: [ 1.045548] pci 0000:00:02.0: [8086:5a85] type 00 class 0x030000 >May 24 09:53:41 BXT-2 kernel: [ 1.045589] pci 0000:00:02.0: reg 0x10: [mem 0x90000000-0x90ffffff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.045614] pci 0000:00:02.0: reg 0x18: [mem 0x80000000-0x8fffffff 64bit pref] >May 24 09:53:41 BXT-2 kernel: [ 1.045632] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f] >May 24 09:53:41 BXT-2 kernel: [ 1.050448] pci 0000:00:0e.0: [8086:5a98] type 00 class 0x040380 >May 24 09:53:41 BXT-2 kernel: [ 1.050504] pci 0000:00:0e.0: reg 0x10: [mem 0x91410000-0x91413fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.050582] pci 0000:00:0e.0: reg 0x20: [mem 0x91000000-0x910fffff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.050782] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.055894] pci 0000:00:0e.0: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.056309] pci 0000:00:0f.0: [8086:5a9a] type 00 class 0x078000 >May 24 09:53:41 BXT-2 kernel: [ 1.056376] pci 0000:00:0f.0: reg 0x10: [mem 0x91429000-0x91429fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.056661] pci 0000:00:0f.0: PME# supported from D3hot >May 24 09:53:41 BXT-2 kernel: [ 1.060842] pci 0000:00:12.0: [8086:5ae3] type 00 class 0x010601 >May 24 09:53:41 BXT-2 kernel: [ 1.060888] pci 0000:00:12.0: reg 0x10: [mem 0x91414000-0x91415fff] >May 24 09:53:41 BXT-2 kernel: [ 1.060912] pci 0000:00:12.0: reg 0x14: [mem 0x91426000-0x914260ff] >May 24 09:53:41 BXT-2 kernel: [ 1.060953] pci 0000:00:12.0: reg 0x18: [io 0xf090-0xf097] >May 24 09:53:41 BXT-2 kernel: [ 1.060983] pci 0000:00:12.0: reg 0x1c: [io 0xf080-0xf083] >May 24 09:53:41 BXT-2 kernel: [ 1.061006] pci 0000:00:12.0: reg 0x20: [io 0xf060-0xf07f] >May 24 09:53:41 BXT-2 kernel: [ 1.061029] pci 0000:00:12.0: reg 0x24: [mem 0x91425000-0x914257ff] >May 24 09:53:41 BXT-2 kernel: [ 1.061196] pci 0000:00:12.0: PME# supported from D3hot >May 24 09:53:41 BXT-2 kernel: [ 1.065307] pci 0000:00:13.0: [8086:5ad8] type 01 class 0x060400 >May 24 09:53:41 BXT-2 kernel: [ 1.065577] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.069425] pci 0000:00:13.0: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.069819] pci 0000:00:13.1: [8086:5ad9] type 01 class 0x060400 >May 24 09:53:41 BXT-2 kernel: [ 1.070103] pci 0000:00:13.1: PME# supported from D0 D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.073930] pci 0000:00:13.1: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.074359] pci 0000:00:13.2: [8086:5ada] type 01 class 0x060400 >May 24 09:53:41 BXT-2 kernel: [ 1.074624] pci 0000:00:13.2: PME# supported from D0 D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.078465] pci 0000:00:13.2: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.078907] pci 0000:00:15.0: [8086:5aa8] type 00 class 0x0c0330 >May 24 09:53:41 BXT-2 kernel: [ 1.078972] pci 0000:00:15.0: reg 0x10: [mem 0x91400000-0x9140ffff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.079258] pci 0000:00:15.0: PME# supported from D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.083244] pci 0000:00:15.0: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.083711] pci 0000:00:16.0: [8086:5aac] type 00 class 0x118000 >May 24 09:53:41 BXT-2 kernel: [ 1.083767] pci 0000:00:16.0: reg 0x10: [mem 0x91424000-0x91424fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.083803] pci 0000:00:16.0: reg 0x18: [mem 0x91423000-0x91423fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.088117] pci 0000:00:18.0: [8086:5abc] type 00 class 0x118000 >May 24 09:53:41 BXT-2 kernel: [ 1.088174] pci 0000:00:18.0: reg 0x10: [mem 0x91422000-0x91422fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.088211] pci 0000:00:18.0: reg 0x18: [mem 0x91421000-0x91421fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.092514] pci 0000:00:19.0: [8086:5ac2] type 00 class 0x118000 >May 24 09:53:41 BXT-2 kernel: [ 1.092570] pci 0000:00:19.0: reg 0x10: [mem 0x91420000-0x91420fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.092607] pci 0000:00:19.0: reg 0x18: [mem 0x9141f000-0x9141ffff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.096836] pci 0000:00:19.1: [8086:5ac4] type 00 class 0x118000 >May 24 09:53:41 BXT-2 kernel: [ 1.096897] pci 0000:00:19.1: reg 0x10: [mem 0x9141e000-0x9141efff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.096933] pci 0000:00:19.1: reg 0x18: [mem 0x9141d000-0x9141dfff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.101168] pci 0000:00:19.2: [8086:5ac6] type 00 class 0x118000 >May 24 09:53:41 BXT-2 kernel: [ 1.101225] pci 0000:00:19.2: reg 0x10: [mem 0x9141c000-0x9141cfff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.101261] pci 0000:00:19.2: reg 0x18: [mem 0x9141b000-0x9141bfff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.105544] pci 0000:00:1a.0: [8086:5ac8] type 00 class 0x0c8000 >May 24 09:53:41 BXT-2 kernel: [ 1.105618] pci 0000:00:1a.0: reg 0x10: [mem 0x9141a000-0x9141afff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.105657] pci 0000:00:1a.0: reg 0x18: [mem 0x91419000-0x91419fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.105860] pci 0000:00:1a.0: PME# supported from D0 D3hot >May 24 09:53:41 BXT-2 kernel: [ 1.109987] pci 0000:00:1c.0: [8086:5acc] type 00 class 0x080501 >May 24 09:53:41 BXT-2 kernel: [ 1.110045] pci 0000:00:1c.0: reg 0x10: [mem 0x91418000-0x91418fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.110083] pci 0000:00:1c.0: reg 0x18: [mem 0x91417000-0x91417fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.114815] pci 0000:00:1f.0: [8086:5ae8] type 00 class 0x060100 >May 24 09:53:41 BXT-2 kernel: [ 1.119150] pci 0000:00:1f.1: [8086:5ad4] type 00 class 0x0c0500 >May 24 09:53:41 BXT-2 kernel: [ 1.119231] pci 0000:00:1f.1: reg 0x10: [mem 0x91416000-0x914160ff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.119345] pci 0000:00:1f.1: reg 0x20: [io 0xf040-0xf05f] >May 24 09:53:41 BXT-2 kernel: [ 1.123731] pci 0000:01:00.0: [10ec:5229] type 00 class 0xff0000 >May 24 09:53:41 BXT-2 kernel: [ 1.123780] pci 0000:01:00.0: reg 0x10: [mem 0x91300000-0x91300fff] >May 24 09:53:41 BXT-2 kernel: [ 1.123941] pci 0000:01:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug >May 24 09:53:41 BXT-2 kernel: [ 1.124156] pci 0000:01:00.0: supports D1 D2 >May 24 09:53:41 BXT-2 kernel: [ 1.124162] pci 0000:01:00.0: PME# supported from D1 D2 D3hot >May 24 09:53:41 BXT-2 kernel: [ 1.124541] pci 0000:01:00.0: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.125021] pci 0000:00:13.0: PCI bridge to [bus 01] >May 24 09:53:41 BXT-2 kernel: [ 1.125037] pci 0000:00:13.0: bridge window [mem 0x91300000-0x913fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.125381] pci 0000:02:00.0: [8086:24fb] type 00 class 0x028000 >May 24 09:53:41 BXT-2 kernel: [ 1.125456] pci 0000:02:00.0: reg 0x10: [mem 0x91200000-0x91201fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.125566] pci 0000:02:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug >May 24 09:53:41 BXT-2 kernel: [ 1.125822] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.126238] pci 0000:02:00.0: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.126666] pci 0000:00:13.1: PCI bridge to [bus 02] >May 24 09:53:41 BXT-2 kernel: [ 1.126681] pci 0000:00:13.1: bridge window [mem 0x91200000-0x912fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.127029] pci 0000:03:00.0: [10ec:8168] type 00 class 0x020000 >May 24 09:53:41 BXT-2 kernel: [ 1.127083] pci 0000:03:00.0: reg 0x10: [io 0xe000-0xe0ff] >May 24 09:53:41 BXT-2 kernel: [ 1.127144] pci 0000:03:00.0: reg 0x18: [mem 0x91104000-0x91104fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.127180] pci 0000:03:00.0: reg 0x20: [mem 0x91100000-0x91103fff 64bit] >May 24 09:53:41 BXT-2 kernel: [ 1.127216] pci 0000:03:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug >May 24 09:53:41 BXT-2 kernel: [ 1.127475] pci 0000:03:00.0: supports D1 D2 >May 24 09:53:41 BXT-2 kernel: [ 1.127480] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold >May 24 09:53:41 BXT-2 kernel: [ 1.127940] pci 0000:03:00.0: System wakeup disabled by ACPI >May 24 09:53:41 BXT-2 kernel: [ 1.128373] pci 0000:00:13.2: PCI bridge to [bus 03] >May 24 09:53:41 BXT-2 kernel: [ 1.128383] pci 0000:00:13.2: bridge window [io 0xe000-0xefff] >May 24 09:53:41 BXT-2 kernel: [ 1.128395] pci 0000:00:13.2: bridge window [mem 0x91100000-0x911fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.128448] pci_bus 0000:00: on NUMA node 0 >May 24 09:53:41 BXT-2 kernel: [ 1.141276] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.142856] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.144469] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.146041] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.147644] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.149219] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.150805] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.152384] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled. >May 24 09:53:41 BXT-2 kernel: [ 1.198231] ACPI: Enabled 1 GPEs in block 00 to 7F >May 24 09:53:41 BXT-2 kernel: [ 1.199356] ACPI : EC: interrupt unblocked >May 24 09:53:41 BXT-2 kernel: [ 1.199410] ACPI : EC: event unblocked >May 24 09:53:41 BXT-2 kernel: [ 1.199451] ACPI: \_SB_.PCI0.SBRG.H_EC: GPE=0x40, EC_CMD/EC_SC=0x66, EC_DATA=0x62 >May 24 09:53:41 BXT-2 kernel: [ 1.199470] ACPI: \_SB_.PCI0.SBRG.H_EC: Used as boot DSDT EC to handle transactions and events >May 24 09:53:41 BXT-2 kernel: [ 1.200452] pci 0000:00:02.0: vgaarb: setting as boot VGA device >May 24 09:53:41 BXT-2 kernel: [ 1.200462] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none >May 24 09:53:41 BXT-2 kernel: [ 1.200493] pci 0000:00:02.0: vgaarb: bridge control possible >May 24 09:53:41 BXT-2 kernel: [ 1.200498] vgaarb: loaded >May 24 09:53:41 BXT-2 kernel: [ 1.202065] SCSI subsystem initialized >May 24 09:53:41 BXT-2 kernel: [ 1.202553] libata version 3.00 loaded. >May 24 09:53:41 BXT-2 kernel: [ 1.202876] ACPI: bus type USB registered >May 24 09:53:41 BXT-2 kernel: [ 1.203192] usbcore: registered new interface driver usbfs >May 24 09:53:41 BXT-2 kernel: [ 1.203319] usbcore: registered new interface driver hub >May 24 09:53:41 BXT-2 kernel: [ 1.203500] usbcore: registered new device driver usb >May 24 09:53:41 BXT-2 kernel: [ 1.204464] Registered efivars operations >May 24 09:53:41 BXT-2 kernel: [ 1.232461] Advanced Linux Sound Architecture Driver Initialized. >May 24 09:53:41 BXT-2 kernel: [ 1.232581] PCI: Using ACPI for IRQ routing >May 24 09:53:41 BXT-2 kernel: [ 1.265511] PCI: pci_cache_line_size set to 64 bytes >May 24 09:53:41 BXT-2 kernel: [ 1.265701] e820: reserve RAM buffer [mem 0x0003f000-0x0003ffff] >May 24 09:53:41 BXT-2 kernel: [ 1.265729] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff] >May 24 09:53:41 BXT-2 kernel: [ 1.265745] e820: reserve RAM buffer [mem 0x77717000-0x77ffffff] >May 24 09:53:41 BXT-2 kernel: [ 1.265759] e820: reserve RAM buffer [mem 0x79fc6000-0x7bffffff] >May 24 09:53:41 BXT-2 kernel: [ 1.265775] e820: reserve RAM buffer [mem 0x7a9df000-0x7bffffff] >May 24 09:53:41 BXT-2 kernel: [ 1.265789] e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff] >May 24 09:53:41 BXT-2 kernel: [ 1.267764] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 >May 24 09:53:41 BXT-2 kernel: [ 1.267802] hpet0: 8 comparators, 64-bit 19.200000 MHz counter >May 24 09:53:41 BXT-2 kernel: [ 1.270003] clocksource: Switched to clocksource hpet >May 24 09:53:41 BXT-2 kernel: [ 1.469846] pnp: PnP ACPI init >May 24 09:53:41 BXT-2 kernel: [ 1.477047] system 00:00: [io 0x0a00-0x0a1f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.477076] system 00:00: [io 0x0a20-0x0a2f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.477091] system 00:00: [io 0x0a30-0x0a3f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.477106] system 00:00: [io 0x0a40-0x0a4f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.477120] system 00:00: [io 0x0a50-0x0a5f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.477135] system 00:00: [io 0x0a60-0x0a6f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.477182] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) >May 24 09:53:41 BXT-2 kernel: [ 1.481397] pnp 00:01: [dma 0 disabled] >May 24 09:53:41 BXT-2 kernel: [ 1.481730] pnp 00:01: Plug and Play ACPI device, IDs ITE8708 (active) >May 24 09:53:41 BXT-2 kernel: [ 1.482399] system 00:02: [io 0x0680-0x069f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.482415] system 00:02: [io 0x0400-0x047f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.482431] system 00:02: [io 0x0500-0x05fe] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.482446] system 00:02: [io 0x0600-0x061f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.482461] system 00:02: [io 0x164e-0x164f] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.482478] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active) >May 24 09:53:41 BXT-2 kernel: [ 1.489403] system 00:03: [mem 0xe0000000-0xefffffff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489420] system 00:03: [mem 0xfea00000-0xfeafffff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489435] system 00:03: [mem 0xfed01000-0xfed01fff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489450] system 00:03: [mem 0xfed03000-0xfed03fff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489465] system 00:03: [mem 0xfed06000-0xfed06fff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489479] system 00:03: [mem 0xfed08000-0xfed09fff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489495] system 00:03: [mem 0xfed80000-0xfedbffff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489518] system 00:03: [mem 0xfed1c000-0xfed1cfff] has been reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489548] system 00:03: [mem 0xfee00000-0xfeefffff] could not be reserved >May 24 09:53:41 BXT-2 kernel: [ 1.489567] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) >May 24 09:53:41 BXT-2 kernel: [ 1.492616] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) >May 24 09:53:41 BXT-2 kernel: [ 1.496154] pnp: PnP ACPI: found 5 devices >May 24 09:53:41 BXT-2 kernel: [ 1.529942] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns >May 24 09:53:41 BXT-2 kernel: [ 1.530064] pci 0000:00:13.0: PCI bridge to [bus 01] >May 24 09:53:41 BXT-2 kernel: [ 1.530079] pci 0000:00:13.0: bridge window [mem 0x91300000-0x913fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.530097] pci 0000:00:13.1: PCI bridge to [bus 02] >May 24 09:53:41 BXT-2 kernel: [ 1.530108] pci 0000:00:13.1: bridge window [mem 0x91200000-0x912fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.530126] pci 0000:00:13.2: PCI bridge to [bus 03] >May 24 09:53:41 BXT-2 kernel: [ 1.530134] pci 0000:00:13.2: bridge window [io 0xe000-0xefff] >May 24 09:53:41 BXT-2 kernel: [ 1.530145] pci 0000:00:13.2: bridge window [mem 0x91100000-0x911fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.530169] pci_bus 0000:00: resource 4 [io 0x0070-0x0077] >May 24 09:53:41 BXT-2 kernel: [ 1.530175] pci_bus 0000:00: resource 5 [io 0x0000-0x006f window] >May 24 09:53:41 BXT-2 kernel: [ 1.530180] pci_bus 0000:00: resource 6 [io 0x0078-0x0cf7 window] >May 24 09:53:41 BXT-2 kernel: [ 1.530185] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.530191] pci_bus 0000:00: resource 8 [mem 0x7c000001-0x7fffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.530196] pci_bus 0000:00: resource 9 [mem 0x7b800001-0x7bffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.530201] pci_bus 0000:00: resource 10 [mem 0x80000000-0xcfffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.530206] pci_bus 0000:00: resource 11 [mem 0xe0000000-0xefffffff window] >May 24 09:53:41 BXT-2 kernel: [ 1.530212] pci_bus 0000:01: resource 1 [mem 0x91300000-0x913fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.530218] pci_bus 0000:02: resource 1 [mem 0x91200000-0x912fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.530223] pci_bus 0000:03: resource 0 [io 0xe000-0xefff] >May 24 09:53:41 BXT-2 kernel: [ 1.530228] pci_bus 0000:03: resource 1 [mem 0x91100000-0x911fffff] >May 24 09:53:41 BXT-2 kernel: [ 1.532249] NET: Registered protocol family 2 >May 24 09:53:41 BXT-2 kernel: [ 1.533717] TCP established hash table entries: 131072 (order: 8, 1048576 bytes) >May 24 09:53:41 BXT-2 kernel: [ 1.534426] TCP bind hash table entries: 65536 (order: 10, 4194304 bytes) >May 24 09:53:41 BXT-2 kernel: [ 1.545089] TCP: Hash tables configured (established 131072 bind 65536) >May 24 09:53:41 BXT-2 kernel: [ 1.545724] UDP hash table entries: 8192 (order: 8, 1310720 bytes) >May 24 09:53:41 BXT-2 kernel: [ 1.548864] UDP-Lite hash table entries: 8192 (order: 8, 1310720 bytes) >May 24 09:53:41 BXT-2 kernel: [ 1.552286] NET: Registered protocol family 1 >May 24 09:53:41 BXT-2 kernel: [ 1.552363] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] >May 24 09:53:41 BXT-2 kernel: [ 1.557379] PCI: CLS 0 bytes, default 64 >May 24 09:53:41 BXT-2 kernel: [ 1.558205] Unpacking initramfs... >May 24 09:53:41 BXT-2 kernel: [ 2.038270] Freeing initrd memory: 11256K >May 24 09:53:41 BXT-2 kernel: [ 2.038509] DMAR: No ATSR found >May 24 09:53:41 BXT-2 kernel: [ 2.040246] DMAR: dmar0: Using Queued invalidation >May 24 09:53:41 BXT-2 kernel: [ 2.040343] DMAR: dmar1: Using Queued invalidation >May 24 09:53:41 BXT-2 kernel: [ 2.040521] DMAR: Setting RMRR: >May 24 09:53:41 BXT-2 kernel: [ 2.041268] DMAR: Setting identity map for device 0000:00:02.0 [0x7b800000 - 0x7fffffff] >May 24 09:53:41 BXT-2 kernel: [ 2.041794] DMAR: Setting identity map for device 0000:00:15.0 [0x797d4000 - 0x797f3fff] >May 24 09:53:41 BXT-2 kernel: [ 2.041822] DMAR: Prepare 0-16MiB unity mapping for LPC >May 24 09:53:41 BXT-2 kernel: [ 2.042392] DMAR: Setting identity map for device 0000:00:1f.0 [0x0 - 0xffffff] >May 24 09:53:41 BXT-2 kernel: [ 2.042494] DMAR: Intel(R) Virtualization Technology for Directed I/O >May 24 09:53:41 BXT-2 kernel: [ 2.043305] iommu: Adding device 0000:00:00.0 to group 0 >May 24 09:53:41 BXT-2 kernel: [ 2.043445] iommu: Adding device 0000:00:02.0 to group 1 >May 24 09:53:41 BXT-2 kernel: [ 2.043569] iommu: Adding device 0000:00:0e.0 to group 2 >May 24 09:53:41 BXT-2 kernel: [ 2.043723] iommu: Adding device 0000:00:0f.0 to group 3 >May 24 09:53:41 BXT-2 kernel: [ 2.043847] iommu: Adding device 0000:00:12.0 to group 4 >May 24 09:53:41 BXT-2 kernel: [ 2.044126] iommu: Adding device 0000:00:13.0 to group 5 >May 24 09:53:41 BXT-2 kernel: [ 2.044231] iommu: Adding device 0000:00:13.1 to group 5 >May 24 09:53:41 BXT-2 kernel: [ 2.044343] iommu: Adding device 0000:00:13.2 to group 5 >May 24 09:53:41 BXT-2 kernel: [ 2.044494] iommu: Adding device 0000:00:15.0 to group 6 >May 24 09:53:41 BXT-2 kernel: [ 2.044644] iommu: Adding device 0000:00:16.0 to group 7 >May 24 09:53:41 BXT-2 kernel: [ 2.044797] iommu: Adding device 0000:00:18.0 to group 8 >May 24 09:53:41 BXT-2 kernel: [ 2.045049] iommu: Adding device 0000:00:19.0 to group 9 >May 24 09:53:41 BXT-2 kernel: [ 2.045143] iommu: Adding device 0000:00:19.1 to group 9 >May 24 09:53:41 BXT-2 kernel: [ 2.045231] iommu: Adding device 0000:00:19.2 to group 9 >May 24 09:53:41 BXT-2 kernel: [ 2.045385] iommu: Adding device 0000:00:1a.0 to group 10 >May 24 09:53:41 BXT-2 kernel: [ 2.045512] iommu: Adding device 0000:00:1c.0 to group 11 >May 24 09:53:41 BXT-2 kernel: [ 2.045689] iommu: Adding device 0000:00:1f.0 to group 12 >May 24 09:53:41 BXT-2 kernel: [ 2.045786] iommu: Adding device 0000:00:1f.1 to group 12 >May 24 09:53:41 BXT-2 kernel: [ 2.045853] iommu: Adding device 0000:01:00.0 to group 5 >May 24 09:53:41 BXT-2 kernel: [ 2.045920] iommu: Adding device 0000:02:00.0 to group 5 >May 24 09:53:41 BXT-2 kernel: [ 2.046049] iommu: Adding device 0000:03:00.0 to group 5 >May 24 09:53:41 BXT-2 kernel: [ 2.072557] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer >May 24 09:53:41 BXT-2 kernel: [ 2.072565] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules >May 24 09:53:41 BXT-2 kernel: [ 2.072569] RAPL PMU: hw unit of domain package 2^-14 Joules >May 24 09:53:41 BXT-2 kernel: [ 2.072573] RAPL PMU: hw unit of domain dram 2^-14 Joules >May 24 09:53:41 BXT-2 kernel: [ 2.072576] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules >May 24 09:53:41 BXT-2 kernel: [ 2.072590] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x159647815e3, max_idle_ns: 440795269835 ns >May 24 09:53:41 BXT-2 kernel: [ 2.072665] clocksource: Switched to clocksource tsc >May 24 09:53:41 BXT-2 kernel: [ 2.084081] workingset: timestamp_bits=46 max_order=22 bucket_order=0 >May 24 09:53:41 BXT-2 kernel: [ 2.125305] ntfs: driver 2.1.32 [Flags: R/O]. >May 24 09:53:41 BXT-2 kernel: [ 2.155564] NET: Registered protocol family 38 >May 24 09:53:41 BXT-2 kernel: [ 2.156110] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250) >May 24 09:53:41 BXT-2 kernel: [ 2.156131] io scheduler noop registered >May 24 09:53:41 BXT-2 kernel: [ 2.156738] io scheduler cfq registered (default) >May 24 09:53:41 BXT-2 kernel: [ 2.156743] io scheduler mq-deadline registered >May 24 09:53:41 BXT-2 kernel: [ 2.156748] io scheduler kyber registered >May 24 09:53:41 BXT-2 kernel: [ 2.156751] start plist test >May 24 09:53:41 BXT-2 kernel: [ 2.160195] end plist test >May 24 09:53:41 BXT-2 kernel: [ 2.171905] pcieport 0000:00:13.0: Signaling PME with IRQ 367 >May 24 09:53:41 BXT-2 kernel: [ 2.172097] pcieport 0000:00:13.1: Signaling PME with IRQ 368 >May 24 09:53:41 BXT-2 kernel: [ 2.172271] pcieport 0000:00:13.2: Signaling PME with IRQ 369 >May 24 09:53:41 BXT-2 kernel: [ 2.173429] uvesafb: failed to execute /sbin/v86d >May 24 09:53:41 BXT-2 kernel: [ 2.173488] uvesafb: make sure that the v86d helper is installed and executable >May 24 09:53:41 BXT-2 kernel: [ 2.173535] uvesafb: Getting VBE info block failed (eax=0x4f00, err=-2) >May 24 09:53:41 BXT-2 kernel: [ 2.173580] uvesafb: vbe_init() failed with -22 >May 24 09:53:41 BXT-2 kernel: [ 2.173673] uvesafb: probe of uvesafb.0 failed with error -22 >May 24 09:53:41 BXT-2 kernel: [ 2.173849] intel_idle: does not run on family 6 model 92 >May 24 09:53:41 BXT-2 kernel: [ 2.174800] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 >May 24 09:53:41 BXT-2 kernel: [ 2.175359] ACPI: Power Button [PWRB] >May 24 09:53:41 BXT-2 kernel: [ 2.175847] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input1 >May 24 09:53:41 BXT-2 kernel: [ 2.175954] ACPI: Sleep Button [SLPB] >May 24 09:53:41 BXT-2 kernel: [ 2.176448] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 >May 24 09:53:41 BXT-2 kernel: [ 2.176541] ACPI: Power Button [PWRF] >May 24 09:53:41 BXT-2 kernel: [ 2.221974] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). >May 24 09:53:41 BXT-2 kernel: [ 2.246295] thermal LNXTHERM:00: registered as thermal_zone0 >May 24 09:53:41 BXT-2 kernel: [ 2.246302] ACPI: Thermal Zone [TZ01] (53 C) >May 24 09:53:41 BXT-2 kernel: [ 2.246705] GHES: HEST is not enabled! >May 24 09:53:41 BXT-2 kernel: [ 2.247340] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled >May 24 09:53:41 BXT-2 kernel: [ 2.253159] Non-volatile memory driver v1.3 >May 24 09:53:41 BXT-2 kernel: [ 2.253861] Linux agpgart interface v0.103 >May 24 09:53:41 BXT-2 kernel: [ 2.258291] loop: module loaded >May 24 09:53:41 BXT-2 kernel: [ 2.260084] ahci 0000:00:12.0: version 3.0 >May 24 09:53:41 BXT-2 kernel: [ 2.273271] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode >May 24 09:53:41 BXT-2 kernel: [ 2.273281] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst >May 24 09:53:41 BXT-2 kernel: [ 2.278232] scsi host0: ahci >May 24 09:53:41 BXT-2 kernel: [ 2.280367] scsi host1: ahci >May 24 09:53:41 BXT-2 kernel: [ 2.281044] ata1: SATA max UDMA/133 abar m2048@0x91425000 port 0x91425100 irq 370 >May 24 09:53:41 BXT-2 kernel: [ 2.281052] ata2: SATA max UDMA/133 abar m2048@0x91425000 port 0x91425180 irq 370 >May 24 09:53:41 BXT-2 kernel: [ 2.281529] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver >May 24 09:53:41 BXT-2 kernel: [ 2.281572] ehci-pci: EHCI PCI platform driver >May 24 09:53:41 BXT-2 kernel: [ 2.281751] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver >May 24 09:53:41 BXT-2 kernel: [ 2.281776] ohci-pci: OHCI PCI platform driver >May 24 09:53:41 BXT-2 kernel: [ 2.281898] uhci_hcd: USB Universal Host Controller Interface driver >May 24 09:53:41 BXT-2 kernel: [ 2.284972] xhci_hcd 0000:00:15.0: xHCI Host Controller >May 24 09:53:41 BXT-2 kernel: [ 2.285171] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1 >May 24 09:53:41 BXT-2 kernel: [ 2.286880] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x01109810 >May 24 09:53:41 BXT-2 kernel: [ 2.286897] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported >May 24 09:53:41 BXT-2 kernel: [ 2.288099] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 >May 24 09:53:41 BXT-2 kernel: [ 2.288112] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 >May 24 09:53:41 BXT-2 kernel: [ 2.288117] usb usb1: Product: xHCI Host Controller >May 24 09:53:41 BXT-2 kernel: [ 2.288123] usb usb1: Manufacturer: Linux 4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ xhci-hcd >May 24 09:53:41 BXT-2 kernel: [ 2.288128] usb usb1: SerialNumber: 0000:00:15.0 >May 24 09:53:41 BXT-2 kernel: [ 2.290160] hub 1-0:1.0: USB hub found >May 24 09:53:41 BXT-2 kernel: [ 2.290389] hub 1-0:1.0: 8 ports detected >May 24 09:53:41 BXT-2 kernel: [ 2.305619] xhci_hcd 0000:00:15.0: xHCI Host Controller >May 24 09:53:41 BXT-2 kernel: [ 2.305664] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2 >May 24 09:53:41 BXT-2 kernel: [ 2.306385] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003 >May 24 09:53:41 BXT-2 kernel: [ 2.306395] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 >May 24 09:53:41 BXT-2 kernel: [ 2.306400] usb usb2: Product: xHCI Host Controller >May 24 09:53:41 BXT-2 kernel: [ 2.306405] usb usb2: Manufacturer: Linux 4.12.0-rc2-drm-tip-ww21-commit-7808a0f+ xhci-hcd >May 24 09:53:41 BXT-2 kernel: [ 2.306410] usb usb2: SerialNumber: 0000:00:15.0 >May 24 09:53:41 BXT-2 kernel: [ 2.308284] hub 2-0:1.0: USB hub found >May 24 09:53:41 BXT-2 kernel: [ 2.308495] hub 2-0:1.0: 7 ports detected >May 24 09:53:41 BXT-2 kernel: [ 2.322055] usbcore: registered new interface driver usb-storage >May 24 09:53:41 BXT-2 kernel: [ 2.322657] i8042: PNP: No PS/2 controller found. >May 24 09:53:41 BXT-2 kernel: [ 2.322661] i8042: Probing ports directly. >May 24 09:53:41 BXT-2 kernel: [ 2.338240] serio: i8042 KBD port at 0x60,0x64 irq 1 >May 24 09:53:41 BXT-2 kernel: [ 2.339015] serio: i8042 AUX port at 0x60,0x64 irq 12 >May 24 09:53:41 BXT-2 kernel: [ 2.340074] mousedev: PS/2 mouse device common for all mice >May 24 09:53:41 BXT-2 kernel: [ 2.342670] rtc_cmos 00:04: RTC can wake from S4 >May 24 09:53:41 BXT-2 kernel: [ 2.343972] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0 >May 24 09:53:41 BXT-2 kernel: [ 2.344150] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs >May 24 09:53:41 BXT-2 kernel: [ 2.345446] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0) >May 24 09:53:41 BXT-2 kernel: [ 2.346734] device-mapper: uevent: version 1.0.3 >May 24 09:53:41 BXT-2 kernel: [ 2.347926] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com >May 24 09:53:41 BXT-2 kernel: [ 2.347940] intel_pstate: Intel P-state driver initializing >May 24 09:53:41 BXT-2 kernel: [ 2.348562] random: fast init done >May 24 09:53:41 BXT-2 kernel: [ 2.356896] input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 >May 24 09:53:41 BXT-2 kernel: [ 2.359394] EFI Variables Facility v0.08 2004-May-17 >May 24 09:53:41 BXT-2 kernel: [ 2.396107] hidraw: raw HID events driver (C) Jiri Kosina >May 24 09:53:41 BXT-2 kernel: [ 2.396882] usbcore: registered new interface driver usbhid >May 24 09:53:41 BXT-2 kernel: [ 2.396885] usbhid: USB HID core driver >May 24 09:53:41 BXT-2 kernel: [ 2.397523] intel_rapl: Found RAPL domain package >May 24 09:53:41 BXT-2 kernel: [ 2.397530] intel_rapl: Found RAPL domain core >May 24 09:53:41 BXT-2 kernel: [ 2.397535] intel_rapl: Found RAPL domain uncore >May 24 09:53:41 BXT-2 kernel: [ 2.397539] intel_rapl: Found RAPL domain dram >May 24 09:53:41 BXT-2 kernel: [ 2.400354] Initializing XFRM netlink socket >May 24 09:53:41 BXT-2 kernel: [ 2.401924] NET: Registered protocol family 10 >May 24 09:53:41 BXT-2 kernel: [ 2.404528] Segment Routing with IPv6 >May 24 09:53:41 BXT-2 kernel: [ 2.404590] mip6: Mobile IPv6 >May 24 09:53:41 BXT-2 kernel: [ 2.404617] NET: Registered protocol family 17 >May 24 09:53:41 BXT-2 kernel: [ 2.404643] NET: Registered protocol family 15 >May 24 09:53:41 BXT-2 kernel: [ 2.406899] SSE version of gcm_enc/dec engaged. >May 24 09:53:41 BXT-2 kernel: [ 2.501071] alg: No test for pcbc(aes) (pcbc-aes-aesni) >May 24 09:53:41 BXT-2 kernel: [ 2.502685] registered taskstats version 1 >May 24 09:53:41 BXT-2 kernel: [ 2.508112] Btrfs loaded, crc32c=crc32c-generic >May 24 09:53:41 BXT-2 kernel: [ 2.513419] rtc_cmos 00:04: setting system clock to 2017-05-24 14:53:36 UTC (1495637616) >May 24 09:53:41 BXT-2 kernel: [ 2.514498] PM: Checking hibernation image partition /dev/sda3 >May 24 09:53:41 BXT-2 kernel: [ 2.598194] ata2: SATA link down (SStatus 4 SControl 300) >May 24 09:53:41 BXT-2 kernel: [ 2.672363] usb 1-8: new full-speed USB device number 2 using xhci_hcd >May 24 09:53:41 BXT-2 kernel: [ 2.755596] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) >May 24 09:53:41 BXT-2 kernel: [ 2.771049] ata1.00: ATA-9: INTEL SSDSC2BW080A4, DC22, max UDMA/133 >May 24 09:53:41 BXT-2 kernel: [ 2.771059] ata1.00: 156301488 sectors, multi 16: LBA48 NCQ (depth 31/32), AA >May 24 09:53:41 BXT-2 kernel: [ 2.796930] ata1.00: configured for UDMA/133 >May 24 09:53:41 BXT-2 kernel: [ 2.800443] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSC2BW08 DC22 PQ: 0 ANSI: 5 >May 24 09:53:41 BXT-2 kernel: [ 2.805292] sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB) >May 24 09:53:41 BXT-2 kernel: [ 2.805357] sd 0:0:0:0: Attached scsi generic sg0 type 0 >May 24 09:53:41 BXT-2 kernel: [ 2.805469] sd 0:0:0:0: [sda] Write Protect is off >May 24 09:53:41 BXT-2 kernel: [ 2.805478] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 >May 24 09:53:41 BXT-2 kernel: [ 2.805765] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA >May 24 09:53:41 BXT-2 kernel: [ 2.812753] sda: sda1 sda2 sda3 >May 24 09:53:41 BXT-2 kernel: [ 2.816433] sd 0:0:0:0: [sda] Attached SCSI disk >May 24 09:53:41 BXT-2 kernel: [ 2.816566] PM: Hibernation image partition 8:3 present >May 24 09:53:41 BXT-2 kernel: [ 2.816571] PM: Looking for hibernation image. >May 24 09:53:41 BXT-2 kernel: [ 2.818297] PM: Image not found (code -22) >May 24 09:53:41 BXT-2 kernel: [ 2.818304] PM: Hibernation image not present or could not be loaded. >May 24 09:53:41 BXT-2 kernel: [ 2.818321] ALSA device list: >May 24 09:53:41 BXT-2 kernel: [ 2.818324] No soundcards found. >May 24 09:53:41 BXT-2 kernel: [ 2.821969] Freeing unused kernel memory: 1200K >May 24 09:53:41 BXT-2 kernel: [ 2.821975] Write protecting the kernel read-only data: 14336k >May 24 09:53:41 BXT-2 kernel: [ 2.824469] Freeing unused kernel memory: 1556K >May 24 09:53:41 BXT-2 kernel: [ 2.827422] Freeing unused kernel memory: 652K >May 24 09:53:41 BXT-2 kernel: [ 2.844126] usb 1-8: New USB device found, idVendor=8087, idProduct=0aa7 >May 24 09:53:41 BXT-2 kernel: [ 2.844139] usb 1-8: New USB device strings: Mfr=0, Product=0, SerialNumber=0 >May 24 09:53:41 BXT-2 kernel: [ 3.207496] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded >May 24 09:53:41 BXT-2 kernel: [ 3.215879] r8169 0000:03:00.0 eth0: RTL8168h/8111h at 0xffffc900000a1000, f4:4d:30:68:3e:74, XID 14100800 IRQ 372 >May 24 09:53:41 BXT-2 kernel: [ 3.215886] r8169 0000:03:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko] >May 24 09:53:41 BXT-2 kernel: [ 3.227637] sdhci: Secure Digital Host Controller Interface driver >May 24 09:53:41 BXT-2 kernel: [ 3.227641] sdhci: Copyright(c) Pierre Ossman >May 24 09:53:41 BXT-2 kernel: [ 3.228930] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev b) >May 24 09:53:41 BXT-2 kernel: [ 3.241399] mmc0: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit >May 24 09:53:41 BXT-2 kernel: [ 3.246598] [drm:i915_driver_load [i915]] No PCH found. >May 24 09:53:41 BXT-2 kernel: [ 3.246659] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09 >May 24 09:53:41 BXT-2 kernel: [ 3.248715] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a85 rev=0x0b >May 24 09:53:41 BXT-2 kernel: [ 3.248767] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no >May 24 09:53:41 BXT-2 kernel: [ 3.248816] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes >May 24 09:53:41 BXT-2 kernel: [ 3.248865] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no >May 24 09:53:41 BXT-2 kernel: [ 3.248913] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes >May 24 09:53:41 BXT-2 kernel: [ 3.248962] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249010] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249188] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249237] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249285] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249334] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249383] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249432] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249480] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249529] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249577] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no >May 24 09:53:41 BXT-2 kernel: [ 3.249626] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249674] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249723] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no >May 24 09:53:41 BXT-2 kernel: [ 3.249772] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no >May 24 09:53:41 BXT-2 kernel: [ 3.249820] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes >May 24 09:53:41 BXT-2 kernel: [ 3.249869] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no >May 24 09:53:41 BXT-2 kernel: [ 3.249918] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no >May 24 09:53:41 BXT-2 kernel: [ 3.249966] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no >May 24 09:53:41 BXT-2 kernel: [ 3.250015] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no >May 24 09:53:41 BXT-2 kernel: [ 3.250238] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes >May 24 09:53:41 BXT-2 kernel: [ 3.250287] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no >May 24 09:53:41 BXT-2 kernel: [ 3.250336] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes >May 24 09:53:41 BXT-2 kernel: [ 3.250384] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes >May 24 09:53:41 BXT-2 kernel: [ 3.250433] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no >May 24 09:53:41 BXT-2 kernel: [ 3.250481] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no >May 24 09:53:41 BXT-2 kernel: [ 3.250530] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no >May 24 09:53:41 BXT-2 kernel: [ 3.250578] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no >May 24 09:53:41 BXT-2 kernel: [ 3.250627] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no >May 24 09:53:41 BXT-2 kernel: [ 3.250675] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no >May 24 09:53:41 BXT-2 kernel: [ 3.253688] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001 >May 24 09:53:41 BXT-2 kernel: [ 3.253741] [drm:intel_device_info_runtime_init [i915]] slice total: 1 >May 24 09:53:41 BXT-2 kernel: [ 3.253790] [drm:intel_device_info_runtime_init [i915]] subslice total: 2 >May 24 09:53:41 BXT-2 kernel: [ 3.253838] [drm:intel_device_info_runtime_init [i915]] subslice mask 0006 >May 24 09:53:41 BXT-2 kernel: [ 3.253887] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 2 >May 24 09:53:41 BXT-2 kernel: [ 3.253936] [drm:intel_device_info_runtime_init [i915]] EU total: 12 >May 24 09:53:41 BXT-2 kernel: [ 3.253984] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6 >May 24 09:53:41 BXT-2 kernel: [ 3.254062] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n >May 24 09:53:41 BXT-2 kernel: [ 3.254111] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y >May 24 09:53:41 BXT-2 kernel: [ 3.254161] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y >May 24 09:53:41 BXT-2 kernel: [ 3.254210] [drm:i915_driver_load [i915]] ppgtt mode: 3 >May 24 09:53:41 BXT-2 kernel: [ 3.254259] [drm:i915_driver_load [i915]] use GPU semaphores? no >May 24 09:53:41 BXT-2 kernel: [ 3.254348] [drm] Memory usable by graphics device = 4096M >May 24 09:53:41 BXT-2 kernel: [ 3.254409] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M >May 24 09:53:41 BXT-2 kernel: [ 3.254462] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M >May 24 09:53:41 BXT-2 kernel: [ 3.254464] [drm] VT-d active for gfx access >May 24 09:53:41 BXT-2 kernel: [ 3.254549] [drm] Replacing VGA console driver >May 24 09:53:41 BXT-2 kernel: [ 3.254733] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K >May 24 09:53:41 BXT-2 kernel: [ 3.254800] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4 >May 24 09:53:41 BXT-2 kernel: [ 3.254983] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7987e018 >May 24 09:53:41 BXT-2 kernel: [ 3.255143] [drm:intel_opregion_setup [i915]] Public ACPI methods supported >May 24 09:53:41 BXT-2 kernel: [ 3.255198] [drm:intel_opregion_setup [i915]] ASLE supported >May 24 09:53:41 BXT-2 kernel: [ 3.255278] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA) >May 24 09:53:41 BXT-2 kernel: [ 3.255650] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params >May 24 09:53:41 BXT-2 kernel: [ 3.257157] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). >May 24 09:53:41 BXT-2 kernel: [ 3.257160] [drm] Driver supports precise vblank timestamp query. >May 24 09:53:41 BXT-2 kernel: [ 3.257242] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz >May 24 09:53:41 BXT-2 kernel: [ 3.257300] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON ", BDB version 207 >May 24 09:53:41 BXT-2 kernel: [ 3.257357] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 >May 24 09:53:41 BXT-2 kernel: [ 3.257413] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 >May 24 09:53:41 BXT-2 kernel: [ 3.257471] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19) >May 24 09:53:41 BXT-2 kernel: [ 3.257528] [drm:intel_bios_init [i915]] Panel type: 0 (VBT) >May 24 09:53:41 BXT-2 kernel: [ 3.257583] [drm:intel_bios_init [i915]] DRRS supported mode is static >May 24 09:53:41 BXT-2 kernel: [ 3.257648] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables: >May 24 09:53:41 BXT-2 kernel: [ 3.257657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 0 148350 1920 1960 2000 2040 1200 1204 1208 1212 0x8 0xa >May 24 09:53:41 BXT-2 kernel: [ 3.257714] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 1 >May 24 09:53:41 BXT-2 kernel: [ 3.257770] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping. >May 24 09:53:41 BXT-2 kernel: [ 3.257827] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38 >May 24 09:53:41 BXT-2 kernel: [ 3.257888] [drm:intel_bios_init [i915]] DRRS State Enabled:1 >May 24 09:53:41 BXT-2 kernel: [ 3.257946] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0 >May 24 09:53:41 BXT-2 kernel: [ 3.258002] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 0 >May 24 09:53:41 BXT-2 kernel: [ 3.258083] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:0 DVI:0 EDP:0 CRT:0 >May 24 09:53:41 BXT-2 kernel: [ 3.258139] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 0 >May 24 09:53:41 BXT-2 kernel: [ 3.258724] [drm:intel_dsm_detect [i915]] no _DSM method for intel device >May 24 09:53:41 BXT-2 kernel: [ 3.258795] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 09:53:41 BXT-2 kernel: [ 3.258952] [drm:intel_power_well_enable [i915]] enabling power well 1 >May 24 09:53:41 BXT-2 kernel: [ 3.259035] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 09:53:41 BXT-2 kernel: [ 3.259252] [drm:intel_power_well_enable [i915]] enabling always-on >May 24 09:53:41 BXT-2 kernel: [ 3.259303] [drm:intel_power_well_enable [i915]] enabling DC off >May 24 09:53:41 BXT-2 kernel: [ 3.259355] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 >May 24 09:53:41 BXT-2 kernel: [ 3.259417] [drm:intel_power_well_enable [i915]] enabling power well 2 >May 24 09:53:41 BXT-2 kernel: [ 3.259472] [drm:intel_power_well_enable [i915]] enabling dpio-common-a >May 24 09:53:41 BXT-2 kernel: [ 3.259942] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc >May 24 09:53:41 BXT-2 kernel: [ 3.260146] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it >May 24 09:53:41 BXT-2 kernel: [ 3.260231] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin >May 24 09:53:41 BXT-2 kernel: [ 3.262277] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7) >May 24 09:53:41 BXT-2 kernel: [ 3.262557] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001818 hp_port:38 >May 24 09:53:41 BXT-2 kernel: [ 3.264650] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled >May 24 09:53:41 BXT-2 kernel: [ 3.264731] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 >May 24 09:53:41 BXT-2 kernel: [ 3.264802] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.264852] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.264901] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.264950] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.264999] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.265074] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.265123] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.265172] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec) >May 24 09:53:41 BXT-2 kernel: [ 3.265229] [drm:intel_modeset_init [i915]] 3 display pipes available. >May 24 09:53:41 BXT-2 kernel: [ 3.265891] [drm:intel_update_cdclk [i915]] Current CD clock rate: 624000 kHz, VCO: 1248000 kHz, ref: 19200 kHz >May 24 09:53:41 BXT-2 kernel: [ 3.266352] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz >May 24 09:53:41 BXT-2 kernel: [ 3.266410] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz >May 24 09:53:41 BXT-2 kernel: [ 3.266434] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem >May 24 09:53:41 BXT-2 kernel: [ 3.266894] [drm:intel_ddi_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it >May 24 09:53:41 BXT-2 kernel: [ 3.266951] [drm:intel_ddi_init [i915]] VBT says port B has lspcon >May 24 09:53:41 BXT-2 kernel: [ 3.267145] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B >May 24 09:53:41 BXT-2 kernel: [ 3.267294] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT) >May 24 09:53:41 BXT-2 kernel: [ 3.268842] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2 >May 24 09:53:41 BXT-2 kernel: [ 3.270523] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.272480] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.273664] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.275187] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.276603] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.279572] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0) >May 24 09:53:41 BXT-2 kernel: [ 3.281200] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.284621] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.287421] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.288822] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.290124] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.290978] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0) >May 24 09:53:41 BXT-2 kernel: [ 3.291058] [drm:lspcon_init [i915]] LSPCON detected >May 24 09:53:41 BXT-2 kernel: [ 3.291611] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.293679] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.295067] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.297840] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.299143] [drm:drm_dp_i2c_do_msg] native defer >May 24 09:53:41 BXT-2 kernel: [ 3.300267] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON >May 24 09:53:41 BXT-2 kernel: [ 3.300810] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04 >May 24 09:53:41 BXT-2 kernel: [ 3.301367] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.2 SW-rev 1.60 >May 24 09:53:41 BXT-2 kernel: [ 3.301426] [drm:lspcon_init [i915]] Success: LSPCON init >May 24 09:53:41 BXT-2 kernel: [ 3.301482] [drm:intel_ddi_init [i915]] LSPCON init success on port B >May 24 09:53:41 BXT-2 kernel: [ 3.301583] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C >May 24 09:53:41 BXT-2 kernel: [ 3.301652] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT) >May 24 09:53:41 BXT-2 kernel: [ 3.301809] [drm:intel_dsi_init [i915]] >May 24 09:53:41 BXT-2 kernel: [ 3.302202] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x1 >May 24 09:53:41 BXT-2 kernel: [ 3.302268] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:34:pipe A] hw state readout: enabled >May 24 09:53:41 BXT-2 kernel: [ 3.302335] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0 >May 24 09:53:41 BXT-2 kernel: [ 3.302391] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:43:pipe B] hw state readout: disabled >May 24 09:53:41 BXT-2 kernel: [ 3.302456] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0 >May 24 09:53:41 BXT-2 kernel: [ 3.302523] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:50:pipe C] hw state readout: disabled >May 24 09:53:41 BXT-2 kernel: [ 3.302583] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0 >May 24 09:53:41 BXT-2 kernel: [ 3.302642] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0 >May 24 09:53:41 BXT-2 kernel: [ 3.302762] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000001, on 1 >May 24 09:53:41 BXT-2 kernel: [ 3.302822] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DDI B] hw state readout: disabled, pipe A >May 24 09:53:41 BXT-2 kernel: [ 3.302878] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST A] hw state readout: disabled, pipe A >May 24 09:53:41 BXT-2 kernel: [ 3.302934] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST B] hw state readout: disabled, pipe B >May 24 09:53:41 BXT-2 kernel: [ 3.302990] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DP-MST C] hw state readout: disabled, pipe C >