Attachment 135086 Details for Bug 103472 – Lines added to dmesg when the VGA cable is connected

Lines added to dmesg when the VGA cable is connected

dmesg-3-diff-after-vga.log (text/x-log), 67.93 KB, created by Pablo on 2017-10-26 18:42:38 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Pablo

Created: 2017-10-26 18:42:38 UTC

Size: 67.93 KB

patch

obsolete

>[  281.413806] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f495c00
>[  281.413835] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802756c0840 state to ffff88006f495c00
>[  281.413855] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea0800 state to ffff88006f495c00
>[  281.413873] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802756c0840 to [CRTC:26]
>[  281.413888] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802756c0840
>[  281.413902] [drm:drm_atomic_check_only] checking ffff88006f495c00
>[  281.413931] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.413946] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 0 -> 1, off 0, on 1, ms 0
>[  281.413960] [drm:drm_atomic_commit] commiting ffff88006f495c00
>[  281.414021] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  281.414063] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=383, cursor=0, sprite0=0, sprite1=0, SR: plane=1407, cursor=0 level=2 cxsr=1
>[  281.414141] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f495c00
>[  281.414160] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f495c00
>[  281.419577] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f495c00
>[  281.419605] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802756c09c0 state to ffff88006f495c00
>[  281.419625] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea3800 state to ffff88006f495c00
>[  281.419652] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802756c09c0 to [CRTC:26]
>[  281.419665] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802756c09c0
>[  281.419678] [drm:drm_atomic_check_only] checking ffff88006f495c00
>[  281.419706] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.419721] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.419735] [drm:drm_atomic_commit] commiting ffff88006f495c00
>[  281.419841] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f495c00
>[  281.419860] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f495c00
>[  281.427607] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355c00
>[  281.427636] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2180 state to ffff880270355c00
>[  281.427656] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636d800 state to ffff880270355c00
>[  281.427670] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2180 to [CRTC:26]
>[  281.427685] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2180
>[  281.427697] [drm:drm_atomic_check_only] checking ffff880270355c00
>[  281.427729] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.427744] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.427758] [drm:drm_atomic_commit] commiting ffff880270355c00
>[  281.427861] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355c00
>[  281.427880] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355c00
>[  281.435573] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355600
>[  281.435599] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2840 state to ffff880270355600
>[  281.435618] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636f000 state to ffff880270355600
>[  281.435632] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2840 to [CRTC:26]
>[  281.435646] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2840
>[  281.435659] [drm:drm_atomic_check_only] checking ffff880270355600
>[  281.435713] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.435728] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.435742] [drm:drm_atomic_commit] commiting ffff880270355600
>[  281.435835] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355600
>[  281.435855] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355600
>[  281.443513] [drm:drm_atomic_state_init] Allocated atomic state ffff880270354c00
>[  281.443528] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2180 state to ffff880270354c00
>[  281.443540] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636d800 state to ffff880270354c00
>[  281.443546] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2180 to [CRTC:26]
>[  281.443552] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2180
>[  281.443558] [drm:drm_atomic_check_only] checking ffff880270354c00
>[  281.443570] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.443577] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.443584] [drm:drm_atomic_commit] commiting ffff880270354c00
>[  281.443633] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270354c00
>[  281.443644] [drm:drm_atomic_state_free] Freeing atomic state ffff880270354c00
>[  281.451452] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355000
>[  281.451466] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2840 state to ffff880270355000
>[  281.451475] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636f000 state to ffff880270355000
>[  281.451482] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2840 to [CRTC:26]
>[  281.451488] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2840
>[  281.451493] [drm:drm_atomic_check_only] checking ffff880270355000
>[  281.451504] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.451512] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.451518] [drm:drm_atomic_commit] commiting ffff880270355000
>[  281.451567] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355000
>[  281.451578] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355000
>[  281.452176] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355c00
>[  281.452188] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2180 state to ffff880270355c00
>[  281.452197] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636d800 state to ffff880270355c00
>[  281.452203] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2180 to [CRTC:26]
>[  281.452210] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2180
>[  281.452215] [drm:drm_atomic_check_only] checking ffff880270355c00
>[  281.452227] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.452234] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.452240] [drm:drm_atomic_commit] commiting ffff880270355c00
>[  281.452288] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355c00
>[  281.452297] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355c00
>[  281.459495] [drm:drm_atomic_state_init] Allocated atomic state ffff880270354c00
>[  281.459505] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2840 state to ffff880270354c00
>[  281.459511] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636f000 state to ffff880270354c00
>[  281.459515] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2840 to [CRTC:26]
>[  281.459519] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2840
>[  281.459523] [drm:drm_atomic_check_only] checking ffff880270354c00
>[  281.459533] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.459538] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.459543] [drm:drm_atomic_commit] commiting ffff880270354c00
>[  281.459589] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270354c00
>[  281.459597] [drm:drm_atomic_state_free] Freeing atomic state ffff880270354c00
>[  281.467441] [drm:drm_atomic_state_init] Allocated atomic state ffff880271e20600
>[  281.467451] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2b40 state to ffff880271e20600
>[  281.467457] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636d800 state to ffff880271e20600
>[  281.467461] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2b40 to [CRTC:26]
>[  281.467464] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2b40
>[  281.467467] [drm:drm_atomic_check_only] checking ffff880271e20600
>[  281.467478] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.467481] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.467485] [drm:drm_atomic_commit] commiting ffff880271e20600
>[  281.467529] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880271e20600
>[  281.467535] [drm:drm_atomic_state_free] Freeing atomic state ffff880271e20600
>[  281.475606] [drm:drm_atomic_state_init] Allocated atomic state ffff880271e21e00
>[  281.475617] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2840 state to ffff880271e21e00
>[  281.475623] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636f000 state to ffff880271e21e00
>[  281.475627] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2840 to [CRTC:26]
>[  281.475631] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2840
>[  281.475637] [drm:drm_atomic_check_only] checking ffff880271e21e00
>[  281.475647] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.475652] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.475659] [drm:drm_atomic_commit] commiting ffff880271e21e00
>[  281.475703] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880271e21e00
>[  281.475711] [drm:drm_atomic_state_free] Freeing atomic state ffff880271e21e00
>[  281.483407] [drm:drm_atomic_state_init] Allocated atomic state ffff880271e21e00
>[  281.483417] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802714d2780 state to ffff880271e21e00
>[  281.483425] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027636d800 state to ffff880271e21e00
>[  281.483430] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802714d2780 to [CRTC:26]
>[  281.483436] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802714d2780
>[  281.483442] [drm:drm_atomic_check_only] checking ffff880271e21e00
>[  281.483453] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 57
>[  281.483458] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  281.483464] [drm:drm_atomic_commit] commiting ffff880271e21e00
>[  281.483516] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880271e21e00
>[  281.483523] [drm:drm_atomic_state_free] Freeing atomic state ffff880271e21e00
>[  292.904056] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00040000, dig 0x00040000, pins 0x00000020
>[  292.904070] [drm:intel_hpd_irq_handler] digital hpd port B - long
>[  292.904079] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 5 - cnt: 0
>[  292.904141] [drm:intel_dp_hpd_pulse] got hpd irq on port B - long
>[  292.904799] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00
>[  292.904809] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[  292.904817] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[  292.904823] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[  292.904831] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[  292.905583] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[  292.905607] [drm:i915_hotplug_work_func] Connector DP-1 (pin 5) received hotplug event.
>[  292.905620] [drm:intel_dp_detect] [CONNECTOR:40:DP-1]
>[  292.906747] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00
>[  292.906765] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[  292.906779] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[  292.906793] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[  292.906807] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[  292.914796] [drm:intel_hpd_irq_event] [CONNECTOR:40:DP-1] status updated from disconnected to connected
>[  292.914814] [drm:i915_hotplug_work_func] Connector HDMI-A-1 (pin 5) received hotplug event.
>[  292.914829] [drm:intel_hdmi_detect] [CONNECTOR:44:HDMI-A-1]
>[  292.915059] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  292.915073] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  292.915282] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  292.915299] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  293.033330] [drm:drm_mode_getresources] [CONNECTOR:47:eDP-1]
>[  293.033337] [drm:drm_mode_getresources] [CONNECTOR:40:DP-1]
>[  293.033340] [drm:drm_mode_getresources] [CONNECTOR:44:HDMI-A-1]
>[  293.033342] [drm:drm_mode_getresources] [CONNECTOR:53:DP-2]
>[  293.033344] [drm:drm_mode_getresources] [CONNECTOR:55:HDMI-A-2]
>[  293.033347] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  293.033353] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  293.033360] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  293.033363] [drm:drm_mode_getconnector] [CONNECTOR:53:?]
>[  293.033366] [drm:drm_mode_getconnector] [CONNECTOR:44:?]
>[  293.033369] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  293.033383] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  293.033679] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  293.033685] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-1]
>[  293.033689] [drm:intel_dp_detect] [CONNECTOR:40:DP-1]
>[  293.035772] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 01 00 03 01 01 02 00 00 00 00 00 00
>[  293.035779] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source no, sink no
>[  293.035782] [drm:intel_dp_print_rates] source rates: 162000, 270000
>[  293.035785] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[  293.035788] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[  293.042154] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  293.042170] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-1] probed modes :
>[  293.042174] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  293.042178] [drm:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  293.042182] [drm:drm_mode_debug_printmodeline] Modeline 66:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  293.042186] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  293.042189] [drm:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  293.042193] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  293.042196] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  293.042200] [drm:drm_mode_debug_printmodeline] Modeline 64:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  293.042204] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  293.042208] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  293.042211] [drm:drm_mode_debug_printmodeline] Modeline 75:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  293.042215] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  293.042219] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  293.042222] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  293.042226] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  293.042229] [drm:drm_mode_debug_printmodeline] Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  293.042278] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  293.051639] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f494000
>[  293.051651] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880275682a80 state to ffff88006f494000
>[  293.051657] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff8802729e7000 state to ffff88006f494000
>[  293.051660] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880275682a80 to [NOCRTC]
>[  293.051662] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880275682a80
>[  293.051665] [drm:drm_atomic_check_only] checking ffff88006f494000
>[  293.051674] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb -1
>[  293.051677] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 0, off 1, on 0, ms 0
>[  293.051680] [drm:drm_atomic_commit] commiting ffff88006f494000
>[  293.051726] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  293.051734] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=383, cursor=63, sprite0=0, sprite1=0, SR: plane=1407, cursor=0 level=2 cxsr=1
>[  293.051741] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f494000
>[  293.051746] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f494000
>[  293.065407] [drm:drm_mode_addfb2] [FB:57]
>[  293.065991] [drm:drm_mode_setcrtc] [CRTC:26]
>[  293.066001] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1]
>[  293.066008] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f495e00
>[  293.066014] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff8802729e5800 state to ffff88006f495e00
>[  293.066019] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8802756829c0 state to ffff88006f495e00
>[  293.066024] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:] for CRTC state ffff8802729e5800
>[  293.066027] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802756829c0 to [CRTC:26]
>[  293.066030] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8802756829c0
>[  293.066034] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:47] ffff880272490cc0 state to ffff88006f495e00
>[  293.066037] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26] to ffff88006f495e00
>[  293.066041] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880272490cc0 to [NOCRTC]
>[  293.066043] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880272490cc0 to [CRTC:26]
>[  293.066046] [drm:drm_atomic_check_only] checking ffff88006f495e00
>[  293.066051] [drm:update_connector_routing] Updating routing for [CONNECTOR:47:eDP-1]
>[  293.066055] [drm:update_connector_routing] [CONNECTOR:47:eDP-1] keeps [ENCODER:46:TMDS-46], now on [CRTC:26]
>[  293.066063] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:23] with fb 57
>[  293.066066] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 1, off 0, on 0, ms 0
>[  293.066070] [drm:drm_atomic_commit] commiting ffff88006f495e00
>[  293.080608] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f495e00
>[  293.080627] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f495e00
>[  293.082039] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f494c00
>[  293.082052] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8800756cdb40 state to ffff88006f494c00
>[  293.082057] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff8802729e7000 state to ffff88006f494c00
>[  293.082060] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800756cdb40 to [CRTC:26]
>[  293.082063] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff8800756cdb40
>[  293.082066] [drm:drm_atomic_check_only] checking ffff88006f494c00
>[  293.082078] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  293.082081] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 0 -> 1, off 0, on 1, ms 0
>[  293.082085] [drm:drm_atomic_commit] commiting ffff88006f494c00
>[  293.082108] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  293.082117] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=383, cursor=0, sprite0=0, sprite1=0, SR: plane=1407, cursor=0 level=2 cxsr=1
>[  293.082152] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f494c00
>[  293.082156] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f494c00
>[  293.083043] [drm:drm_atomic_state_init] Allocated atomic state ffff880271e21a00
>[  293.083051] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880275682a80 state to ffff880271e21a00
>[  293.083055] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff8802729e5800 state to ffff880271e21a00
>[  293.083059] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880275682a80 to [CRTC:26]
>[  293.083062] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880275682a80
>[  293.083064] [drm:drm_atomic_check_only] checking ffff880271e21a00
>[  293.083073] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  293.083076] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  293.083079] [drm:drm_atomic_commit] commiting ffff880271e21a00
>[  293.083120] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880271e21a00
>[  293.083125] [drm:drm_atomic_state_free] Freeing atomic state ffff880271e21a00
>[  293.083372] [drm:drm_mode_setcrtc] [CRTC:31]
>[  293.083384] [drm:drm_mode_setcrtc] [CONNECTOR:40:DP-1]
>[  293.083388] [drm:drm_atomic_state_init] Allocated atomic state ffff880271e21a00
>[  293.083392] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff8802729e7000 state to ffff880271e21a00
>[  293.083396] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff8800756cdb40 state to ffff880271e21a00
>[  293.083403] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:] for CRTC state ffff8802729e7000
>[  293.083406] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800756cdb40 to [CRTC:31]
>[  293.083408] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff8800756cdb40
>[  293.083413] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:40] ffff880272490d80 state to ffff880271e21a00
>[  293.083416] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880271e21a00
>[  293.083420] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880272490d80 to [CRTC:31]
>[  293.083422] [drm:drm_atomic_check_only] checking ffff880271e21a00
>[  293.083425] [drm:drm_atomic_helper_check_modeset] [CRTC:31] mode changed
>[  293.083428] [drm:drm_atomic_helper_check_modeset] [CRTC:31] enable changed
>[  293.083431] [drm:update_connector_routing] Updating routing for [CONNECTOR:40:DP-1]
>[  293.083435] [drm:update_connector_routing] [CONNECTOR:40:DP-1] using [ENCODER:39:TMDS-39] on [CRTC:31]
>[  293.083438] [drm:drm_atomic_helper_check_modeset] [CRTC:31] active changed
>[  293.083440] [drm:drm_atomic_helper_check_modeset] [CRTC:31] needs all connectors, enable: y, active: y
>[  293.083443] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880271e21a00
>[  293.083446] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880271e21a00
>[  293.083451] [drm:connected_sink_compute_bpp] [CONNECTOR:40:DP-1] checking for sink bpp constrains
>[  293.083454] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 24
>[  293.083460] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  293.083466] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  293.083468] [drm:intel_dp_compute_config] DP link bw required 356400 available 432000
>[  293.083473] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  293.083478] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff8802729e7000 for pipe B
>[  293.083480] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  293.083482] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  293.083485] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  293.083488] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  293.083491] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  293.083493] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  293.083495] [drm:intel_dump_pipe_config] requested mode:
>[  293.083500] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  293.083502] [drm:intel_dump_pipe_config] adjusted mode:
>[  293.083505] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  293.083508] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[  293.083510] [drm:intel_dump_pipe_config] port clock: 270000
>[  293.083512] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  293.083515] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  293.083517] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  293.083519] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.083521] [drm:intel_dump_pipe_config] ips: 0
>[  293.083523] [drm:intel_dump_pipe_config] double wide: 0
>[  293.083526] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  293.083528] [drm:intel_dump_pipe_config] planes on this crtc
>[  293.083531] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  293.083535] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  293.083538] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  293.083541] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  293.083547] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff8802729e7400 state to ffff880271e21a00
>[  293.083550] [drm:drm_atomic_get_crtc_state] Added [CRTC:36] ffff8802729e7800 state to ffff880271e21a00
>[  293.083555] [drm:intel_plane_atomic_calc_changes] [CRTC:31] has [PLANE:29] with fb 57
>[  293.083557] [drm:intel_plane_atomic_calc_changes] [PLANE:29] visible 0 -> 1, off 0, on 1, ms 1
>[  293.083562] [drm:drm_atomic_commit] commiting ffff880271e21a00
>[  293.083572] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.083611] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0xc (PHY_CONTROL=0x1d0667fd)
>[  293.209636] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  293.209644] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  293.245581] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  293.245587] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  293.246435] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  293.284212] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  293.284218] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  293.321632] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  293.321638] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
>[  293.322765] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  293.323036] [drm:intel_enable_pipe] enabling pipe B
>[  293.323056] [drm:intel_psr_enable] PSR not supported by this panel
>[  293.335681] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  293.335697] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  293.339837] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  293.356497] [drm:intel_connector_check_state] [CONNECTOR:40:DP-1]
>[  293.356508] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[  293.356513] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  293.356518] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  293.356522] [drm:check_encoder_state] [ENCODER:52:TMDS-52]
>[  293.356525] [drm:check_encoder_state] [ENCODER:54:TMDS-54]
>[  293.356529] [drm:check_crtc_state] [CRTC:31]
>[  293.366948] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880271e21a00
>[  293.366962] [drm:drm_atomic_state_free] Freeing atomic state ffff880271e21a00
>[  293.367013] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f494800
>[  293.367022] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff880272ea0c00 state to ffff88006f494800
>[  293.367026] [drm:drm_atomic_check_only] checking ffff88006f494800
>[  293.367033] [drm:drm_atomic_commit] commiting ffff88006f494800
>[  293.367060] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f494800
>[  293.367065] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f494800
>[  293.367109] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f494800
>[  293.367115] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802762e5b40 state to ffff88006f494800
>[  293.367120] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea3000 state to ffff88006f494800
>[  293.367124] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802762e5b40 to [CRTC:26]
>[  293.367128] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff8802762e5b40
>[  293.367131] [drm:drm_atomic_check_only] checking ffff88006f494800
>[  293.367140] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  293.367145] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  293.367149] [drm:drm_atomic_commit] commiting ffff88006f494800
>[  293.367182] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f494800
>[  293.367188] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f494800
>[  293.367209] [drm:drm_atomic_state_init] Allocated atomic state ffff88006f494800
>[  293.367215] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8802762e56c0 state to ffff88006f494800
>[  293.367220] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea0400 state to ffff88006f494800
>[  293.367223] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802762e56c0 to [CRTC:26]
>[  293.367227] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff8802762e56c0
>[  293.367230] [drm:drm_atomic_check_only] checking ffff88006f494800
>[  293.367236] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  293.367241] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  293.367244] [drm:drm_atomic_commit] commiting ffff88006f494800
>[  293.367270] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88006f494800
>[  293.367275] [drm:drm_atomic_state_free] Freeing atomic state ffff88006f494800
>[  293.385490] [drm:drm_atomic_state_init] Allocated atomic state ffff88027391f800
>[  293.385551] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff88027003cb40 state to ffff88027391f800
>[  293.385558] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea2400 state to ffff88027391f800
>[  293.385561] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88027003cb40 to [NOCRTC]
>[  293.385564] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88027003cb40
>[  293.385567] [drm:drm_atomic_check_only] checking ffff88027391f800
>[  293.385579] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb -1
>[  293.385582] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 0, off 1, on 0, ms 0
>[  293.385585] [drm:drm_atomic_commit] commiting ffff88027391f800
>[  293.385640] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  293.385649] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=447, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  293.385657] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88027391f800
>[  293.385662] [drm:drm_atomic_state_free] Freeing atomic state ffff88027391f800
>[  293.386261] [drm:drm_atomic_state_init] Allocated atomic state ffff880270bece00
>[  293.386266] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880035543480 state to ffff880270bece00
>[  293.386270] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea0400 state to ffff880270bece00
>[  293.386273] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880035543480 to [CRTC:26]
>[  293.386275] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880035543480
>[  293.386277] [drm:drm_atomic_check_only] checking ffff880270bece00
>[  293.386284] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  293.386287] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 0 -> 1, off 0, on 1, ms 0
>[  293.386289] [drm:drm_atomic_commit] commiting ffff880270bece00
>[  293.386304] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  293.386313] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=447, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  293.386337] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270bece00
>[  293.386342] [drm:drm_atomic_state_free] Freeing atomic state ffff880270bece00
>[  293.386614] [drm:drm_atomic_state_init] Allocated atomic state ffff880270bece00
>[  293.386619] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff88027003cb40 state to ffff880270bece00
>[  293.386622] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea2400 state to ffff880270bece00
>[  293.386625] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88027003cb40 to [NOCRTC]
>[  293.386627] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88027003cb40
>[  293.386629] [drm:drm_atomic_check_only] checking ffff880270bece00
>[  293.386634] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb -1
>[  293.386636] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 0, off 1, on 0, ms 0
>[  293.386639] [drm:drm_atomic_commit] commiting ffff880270bece00
>[  293.386662] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  293.386670] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=447, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  293.386674] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270bece00
>[  293.386677] [drm:drm_atomic_state_free] Freeing atomic state ffff880270bece00
>[  293.397038] [drm:drm_mode_setcrtc] [CRTC:26]
>[  293.397049] [drm:drm_mode_setcrtc] [CONNECTOR:40:DP-1]
>[  293.397055] [drm:drm_atomic_state_init] Allocated atomic state ffff880270bece00
>[  293.397060] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272ea1800 state to ffff880270bece00
>[  293.397063] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff88027003cf00 state to ffff880270bece00
>[  293.397070] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:] for CRTC state ffff880272ea1800
>[  293.397072] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88027003cf00 to [CRTC:26]
>[  293.397075] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff88027003cf00
>[  293.397080] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:40] ffff880270f47320 state to ffff880270bece00
>[  293.397083] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff880272ea2000 state to ffff880270bece00
>[  293.397086] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26] to ffff880270bece00
>[  293.397089] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:47] ffff880270f475a0 state to ffff880270bece00
>[  293.397092] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880270bece00
>[  293.397095] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880270f475a0 to [NOCRTC]
>[  293.397097] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880270f47320 to [CRTC:26]
>[  293.397100] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff880272ea2000
>[  293.397102] [drm:drm_atomic_check_only] checking ffff880270bece00
>[  293.397106] [drm:drm_atomic_helper_check_modeset] [CRTC:26] mode changed
>[  293.397108] [drm:drm_atomic_helper_check_modeset] [CRTC:31] mode changed
>[  293.397110] [drm:drm_atomic_helper_check_modeset] [CRTC:31] enable changed
>[  293.397113] [drm:update_connector_routing] Updating routing for [CONNECTOR:47:eDP-1]
>[  293.397115] [drm:update_connector_routing] Disabling [CONNECTOR:47:eDP-1]
>[  293.397118] [drm:update_connector_routing] Updating routing for [CONNECTOR:40:DP-1]
>[  293.397122] [drm:update_connector_routing] [CONNECTOR:40:DP-1] keeps [ENCODER:39:TMDS-39], now on [CRTC:26]
>[  293.397124] [drm:drm_atomic_helper_check_modeset] [CRTC:26] needs all connectors, enable: y, active: y
>[  293.397127] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26] to ffff880270bece00
>[  293.397130] [drm:drm_atomic_helper_check_modeset] [CRTC:31] active changed
>[  293.397132] [drm:drm_atomic_helper_check_modeset] [CRTC:31] needs all connectors, enable: n, active: n
>[  293.397135] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880270bece00
>[  293.397139] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff88003553b780 state to ffff880270bece00
>[  293.397142] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26] to ffff880270bece00
>[  293.397147] [drm:connected_sink_compute_bpp] [CONNECTOR:40:DP-1] checking for sink bpp constrains
>[  293.397149] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to default limit of 24
>[  293.397154] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 148500KHz
>[  293.397159] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  293.397161] [drm:intel_dp_compute_config] DP link bw required 356400 available 432000
>[  293.397165] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 24, dithering: 0
>[  293.397169] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880272ea1800 for pipe A
>[  293.397171] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  293.397173] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  293.397176] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  293.397179] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[  293.397182] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  293.397184] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  293.397186] [drm:intel_dump_pipe_config] requested mode:
>[  293.397190] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  293.397192] [drm:intel_dump_pipe_config] adjusted mode:
>[  293.397196] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[  293.397199] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[  293.397201] [drm:intel_dump_pipe_config] port clock: 270000
>[  293.397203] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  293.397205] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  293.397208] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  293.397210] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.397212] [drm:intel_dump_pipe_config] ips: 0
>[  293.397214] [drm:intel_dump_pipe_config] double wide: 0
>[  293.397216] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0002000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  293.397218] [drm:intel_dump_pipe_config] planes on this crtc
>[  293.397221] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled
>[  293.397223] [drm:intel_dump_pipe_config] 	FB:57, fb = 2944x1080 format = 0x34325258
>[  293.397227] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1024x768 dst (0, 0) 1024x768
>[  293.397230] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  293.397233] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0
>[  293.397236] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 0.2 idx: 3 disabled, scaler_id = 0
>[  293.397242] [drm:drm_atomic_get_crtc_state] Added [CRTC:36] ffff880272ea3000 state to ffff880270bece00
>[  293.397247] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:23] with fb 57
>[  293.397249] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 1, off 1, on 1, ms 1
>[  293.397252] [drm:intel_plane_atomic_calc_changes] [CRTC:31] has [PLANE:29] with fb 57
>[  293.397255] [drm:intel_plane_atomic_calc_changes] [PLANE:29] visible 1 -> 0, off 1, on 0, ms 1
>[  293.397259] [drm:drm_atomic_commit] commiting ffff880270bece00
>[  293.397280] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.397799] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.414571] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  293.414587] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  293.414593] [drm:intel_edp_backlight_off] 
>[  293.617578] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  293.617766] [drm:edp_panel_off] Turn eDP port C panel power off
>[  293.617773] [drm:wait_panel_off] Wait for panel power off time
>[  293.617778] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  293.657988] [drm:wait_panel_status] Wait complete
>[  293.658009] [drm:intel_disable_pipe] disabling pipe A
>[  293.666291] [drm:intel_dp_link_down] 
>[  293.738481] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0x0 (PHY_CONTROL=0x0d0067fd)
>[  293.749080] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.756572] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.773403] [drm:intel_disable_pipe] disabling pipe B
>[  293.791547] [drm:intel_dp_link_down] 
>[  293.809208] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0x0 (PHY_CONTROL=0x050007fd)
>[  293.819537] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH0 lanes 0xc (PHY_CONTROL=0x0d0067fd)
>[  293.944338] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  293.944345] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  293.981751] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  293.981757] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  293.982582] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  294.021013] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  294.021018] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  294.060154] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  294.060160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
>[  294.061288] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  294.061754] [drm:intel_enable_pipe] enabling pipe A
>[  294.061776] [drm:intel_psr_enable] PSR not supported by this panel
>[  294.061795] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  294.061808] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=2 cxsr=0
>[  294.078637] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  294.078656] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=63, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1
>[  294.078664] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  294.078680] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  294.078702] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1]
>[  294.078712] [drm:intel_connector_check_state] [CONNECTOR:40:DP-1]
>[  294.078720] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[  294.078726] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  294.078733] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  294.078740] [drm:check_encoder_state] [ENCODER:52:TMDS-52]
>[  294.078745] [drm:check_encoder_state] [ENCODER:54:TMDS-54]
>[  294.078754] [drm:check_crtc_state] [CRTC:26]
>[  294.089587] [drm:check_crtc_state] [CRTC:31]
>[  294.089613] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270bece00
>[  294.089639] [drm:drm_atomic_state_free] Freeing atomic state ffff880270bece00
>[  294.089805] [drm:drm_mode_setcrtc] [CRTC:31]
>[  294.089831] [drm:drm_atomic_state_init] Allocated atomic state ffff8800756a8600
>[  294.089851] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff8802711f9800 state to ffff8800756a8600
>[  294.089870] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff880273802480 state to ffff8800756a8600
>[  294.089883] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8802711f9800
>[  294.089897] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802480 to [NOCRTC]
>[  294.089911] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880273802480
>[  294.089926] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff8800756a8600
>[  294.089942] [drm:drm_atomic_check_only] checking ffff8800756a8600
>[  294.089969] [drm:drm_atomic_commit] commiting ffff8800756a8600
>[  294.090003] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8800756a8600
>[  294.090023] [drm:drm_atomic_state_free] Freeing atomic state ffff8800756a8600
>[  294.091523] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355000
>[  294.091546] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802540 state to ffff880270355000
>[  294.091567] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272dbcc00 state to ffff880270355000
>[  294.091579] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802540 to [CRTC:26]
>[  294.091592] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802540
>[  294.091603] [drm:drm_atomic_check_only] checking ffff880270355000
>[  294.091629] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.091643] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 0 -> 1, off 0, on 1, ms 0
>[  294.091655] [drm:drm_atomic_commit] commiting ffff880270355000
>[  294.091705] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  294.091740] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=151, cursor=0, sprite0=0, sprite1=0, SR: plane=1175, cursor=0 level=2 cxsr=1
>[  294.091811] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355000
>[  294.091829] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355000
>[  294.092144] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355000
>[  294.092165] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802240 state to ffff880270355000
>[  294.092184] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272dbe800 state to ffff880270355000
>[  294.092197] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802240 to [CRTC:26]
>[  294.092209] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802240
>[  294.092220] [drm:drm_atomic_check_only] checking ffff880270355000
>[  294.092242] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.092256] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  294.092268] [drm:drm_atomic_commit] commiting ffff880270355000
>[  294.092356] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355000
>[  294.092376] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355000
>[  294.092479] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355000
>[  294.092499] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802540 state to ffff880270355000
>[  294.092515] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272dbcc00 state to ffff880270355000
>[  294.092527] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802540 to [CRTC:26]
>[  294.092539] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802540
>[  294.092550] [drm:drm_atomic_check_only] checking ffff880270355000
>[  294.092571] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.092585] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  294.092597] [drm:drm_atomic_commit] commiting ffff880270355000
>[  294.092671] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355000
>[  294.092687] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355000
>[  294.092782] [drm:drm_atomic_state_init] Allocated atomic state ffff880270355000
>[  294.092802] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802240 state to ffff880270355000
>[  294.092819] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272dbe800 state to ffff880270355000
>[  294.092831] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802240 to [CRTC:26]
>[  294.092843] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802240
>[  294.092854] [drm:drm_atomic_check_only] checking ffff880270355000
>[  294.092874] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.092888] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  294.092900] [drm:drm_atomic_commit] commiting ffff880270355000
>[  294.092974] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270355000
>[  294.092990] [drm:drm_atomic_state_free] Freeing atomic state ffff880270355000
>[  294.093805] [drm:drm_atomic_state_init] Allocated atomic state ffff880270354c00
>[  294.093816] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802540 state to ffff880270354c00
>[  294.093825] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272dbcc00 state to ffff880270354c00
>[  294.093831] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802540 to [CRTC:26]
>[  294.093837] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802540
>[  294.093843] [drm:drm_atomic_check_only] checking ffff880270354c00
>[  294.093854] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.093862] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  294.093868] [drm:drm_atomic_commit] commiting ffff880270354c00
>[  294.093914] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270354c00
>[  294.093922] [drm:drm_atomic_state_free] Freeing atomic state ffff880270354c00
>[  294.096205] [drm:drm_mode_setcrtc] [CRTC:31]
>[  294.096235] [drm:drm_mode_setcrtc] [CONNECTOR:47:eDP-1]
>[  294.096247] [drm:drm_atomic_state_init] Allocated atomic state ffff880273ff9000
>[  294.096259] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff8802702f2400 state to ffff880273ff9000
>[  294.096269] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff880273802b40 state to ffff880273ff9000
>[  294.096281] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:] for CRTC state ffff8802702f2400
>[  294.096288] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802b40 to [CRTC:31]
>[  294.096295] [drm:drm_atomic_set_fb_for_plane] Set [FB:57] for plane state ffff880273802b40
>[  294.096306] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:47] ffff88024c0221e0 state to ffff880273ff9000
>[  294.096318] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880273ff9000
>[  294.096327] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88024c0221e0 to [CRTC:31]
>[  294.096333] [drm:drm_atomic_check_only] checking ffff880273ff9000
>[  294.096342] [drm:drm_atomic_helper_check_modeset] [CRTC:31] mode changed
>[  294.096348] [drm:drm_atomic_helper_check_modeset] [CRTC:31] enable changed
>[  294.096355] [drm:update_connector_routing] Updating routing for [CONNECTOR:47:eDP-1]
>[  294.096365] [drm:update_connector_routing] [CONNECTOR:47:eDP-1] using [ENCODER:46:TMDS-46] on [CRTC:31]
>[  294.096371] [drm:drm_atomic_helper_check_modeset] [CRTC:31] active changed
>[  294.096377] [drm:drm_atomic_helper_check_modeset] [CRTC:31] needs all connectors, enable: y, active: y
>[  294.096385] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880273ff9000
>[  294.096400] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:31] to ffff880273ff9000
>[  294.096410] [drm:connected_sink_compute_bpp] [CONNECTOR:47:eDP-1] checking for sink bpp constrains
>[  294.096416] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 18
>[  294.096430] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 56000KHz
>[  294.096439] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[  294.096445] [drm:intel_dp_compute_config] DP link bw required 100800 available 432000
>[  294.096454] [drm:intel_modeset_pipe_config] hw max bpp: 30, pipe bpp: 18, dithering: 1
>[  294.096463] [drm:intel_dump_pipe_config] [CRTC:31][modeset] config ffff8802702f2400 for pipe B
>[  294.096475] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  294.096481] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  294.096488] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  294.096496] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 1957341, gmch_n: 8388608, link_m: 108741, link_n: 524288, tu: 64
>[  294.096503] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  294.096509] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  294.096513] [drm:intel_dump_pipe_config] requested mode:
>[  294.096524] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 56000 1024 1072 1104 1184 768 771 775 790 0x0 0x9
>[  294.096528] [drm:intel_dump_pipe_config] adjusted mode:
>[  294.096538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 56000 1024 1072 1104 1184 768 771 775 790 0x48 0x9
>[  294.096546] [drm:intel_dump_crtc_timings] crtc timings: 56000 1024 1072 1104 1184 768 771 775 790, type: 0x48 flags: 0x9
>[  294.096552] [drm:intel_dump_pipe_config] port clock: 270000
>[  294.096558] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  294.096569] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  294.096576] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  294.096582] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  294.096587] [drm:intel_dump_pipe_config] ips: 0
>[  294.096592] [drm:intel_dump_pipe_config] double wide: 0
>[  294.096598] [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xb0006000, dpll_md: 0x0, fp0: 0x0, fp1: 0x0
>[  294.096603] [drm:intel_dump_pipe_config] planes on this crtc
>[  294.096611] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 1.0 idx: 4 disabled, scaler_id = 0
>[  294.096619] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 1.2 idx: 5 disabled, scaler_id = 0
>[  294.096627] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 1.1 idx: 6 disabled, scaler_id = 0
>[  294.096634] [drm:intel_dump_pipe_config] STANDARD PLANE:33 plane: 1.2 idx: 7 disabled, scaler_id = 0
>[  294.096652] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880272645800 state to ffff880273ff9000
>[  294.096662] [drm:drm_atomic_get_crtc_state] Added [CRTC:36] ffff880272647800 state to ffff880273ff9000
>[  294.096675] [drm:intel_plane_atomic_calc_changes] [CRTC:31] has [PLANE:29] with fb 57
>[  294.096682] [drm:intel_plane_atomic_calc_changes] [PLANE:29] visible 0 -> 1, off 0, on 1, ms 1
>[  294.096692] [drm:drm_atomic_commit] commiting ffff880273ff9000
>[  294.096716] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  294.096791] [drm:chv_phy_powergate_lanes] Power gating DPIO PHY0 CH1 lanes 0xc (PHY_CONTROL=0x1d0667fd)
>[  294.184552] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C
>[  294.184569] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  294.184586] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  294.184603] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  294.184613] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  294.221701] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  294.221713] [drm:wait_panel_status] Wait complete
>[  294.221726] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  294.221733] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  294.425583] [drm:edp_panel_on] Turn eDP port C panel power on
>[  294.425594] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  294.425605] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  294.425612] [drm:wait_panel_status] Wait complete
>[  294.425619] [drm:wait_panel_on] Wait for panel power on
>[  294.425626] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  294.583764] [drm:wait_panel_status] Wait complete
>[  294.583775] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  294.583786] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  294.583801] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  294.583810] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  294.623557] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  294.623576] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  294.661452] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  294.661464] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  294.662937] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  294.701356] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  294.701374] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  294.741182] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  294.741202] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
>[  294.742992] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  294.743364] [drm:intel_enable_pipe] enabling pipe B
>[  294.743410] [drm:intel_edp_backlight_on] 
>[  294.743425] [drm:intel_panel_enable_backlight] pipe B
>[  294.743442] [drm:intel_panel_actually_set_backlight] set backlight PWM = 6000
>[  294.743468] [drm:intel_psr_enable] PSR not supported by this panel
>[  294.753646] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  294.753683] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=447, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  294.760299] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  294.776983] [drm:intel_connector_check_state] [CONNECTOR:47:eDP-1]
>[  294.776998] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[  294.777007] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  294.777017] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  294.777022] [drm:check_encoder_state] [ENCODER:52:TMDS-52]
>[  294.777028] [drm:check_encoder_state] [ENCODER:54:TMDS-54]
>[  294.777034] [drm:check_crtc_state] [CRTC:31]
>[  294.786630] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880273ff9000
>[  294.786643] [drm:drm_atomic_state_free] Freeing atomic state ffff880273ff9000
>[  294.786688] [drm:drm_atomic_state_init] Allocated atomic state ffff880273ff9000
>[  294.786697] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff8802711f9800 state to ffff880273ff9000
>[  294.786701] [drm:drm_atomic_check_only] checking ffff880273ff9000
>[  294.786709] [drm:drm_atomic_commit] commiting ffff880273ff9000
>[  294.786740] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880273ff9000
>[  294.786747] [drm:drm_atomic_state_free] Freeing atomic state ffff880273ff9000
>[  294.799322] [drm:drm_atomic_state_init] Allocated atomic state ffff880273ff9000
>[  294.799330] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802480 state to ffff880273ff9000
>[  294.799335] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff88027411b000 state to ffff880273ff9000
>[  294.799338] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802480 to [CRTC:26]
>[  294.799342] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802480
>[  294.799345] [drm:drm_atomic_check_only] checking ffff880273ff9000
>[  294.799354] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.799357] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  294.799361] [drm:drm_atomic_commit] commiting ffff880273ff9000
>[  294.799399] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880273ff9000
>[  294.799404] [drm:drm_atomic_state_free] Freeing atomic state ffff880273ff9000
>[  294.799421] [drm:drm_atomic_state_init] Allocated atomic state ffff880273ff9000
>[  294.799426] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880273802a80 state to ffff880273ff9000
>[  294.799431] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff880274118c00 state to ffff880273ff9000
>[  294.799434] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802a80 to [CRTC:31]
>[  294.799437] [drm:drm_atomic_set_fb_for_plane] Set [FB:78] for plane state ffff880273802a80
>[  294.799440] [drm:drm_atomic_check_only] checking ffff880273ff9000
>[  294.799445] [drm:intel_plane_atomic_calc_changes] [CRTC:31] has [PLANE:30] with fb 78
>[  294.799449] [drm:intel_plane_atomic_calc_changes] [PLANE:30] visible 0 -> 1, off 0, on 1, ms 0
>[  294.799452] [drm:drm_atomic_commit] commiting ffff880273ff9000
>[  294.799464] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  294.799473] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=447, cursor=0, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  294.799495] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880273ff9000
>[  294.799500] [drm:drm_atomic_state_free] Freeing atomic state ffff880273ff9000
>[  294.799517] [drm:drm_atomic_state_init] Allocated atomic state ffff880273ff9000
>[  294.799522] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff880273802f00 state to ffff880273ff9000
>[  294.799526] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880274119000 state to ffff880273ff9000
>[  294.799529] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802f00 to [CRTC:26]
>[  294.799532] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff880273802f00
>[  294.799535] [drm:drm_atomic_check_only] checking ffff880273ff9000
>[  294.799540] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb 59
>[  294.799544] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 1, off 0, on 0, ms 0
>[  294.799547] [drm:drm_atomic_commit] commiting ffff880273ff9000
>[  294.799570] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880273ff9000
>[  294.799574] [drm:drm_atomic_state_free] Freeing atomic state ffff880273ff9000
>[  294.799582] [drm:drm_atomic_state_init] Allocated atomic state ffff880273ff9000
>[  294.799586] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880273802480 state to ffff880273ff9000
>[  294.799590] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff88027411b000 state to ffff880273ff9000
>[  294.799594] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880273802480 to [CRTC:31]
>[  294.799597] [drm:drm_atomic_set_fb_for_plane] Set [FB:78] for plane state ffff880273802480
>[  294.799599] [drm:drm_atomic_check_only] checking ffff880273ff9000
>[  294.799604] [drm:intel_plane_atomic_calc_changes] [CRTC:31] has [PLANE:30] with fb 78
>[  294.799608] [drm:intel_plane_atomic_calc_changes] [PLANE:30] visible 1 -> 1, off 0, on 0, ms 0
>[  294.799611] [drm:drm_atomic_commit] commiting ffff880273ff9000
>[  294.799633] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880273ff9000
>[  294.799637] [drm:drm_atomic_state_free] Freeing atomic state ffff880273ff9000
>[  294.805713] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.807353] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.807561] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.807739] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.807845] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.808021] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.864602] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.864843] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.865696] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.865893] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.866285] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.867216] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.918419] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.918700] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.918968] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.919140] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.919542] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.919726] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.943114] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.943418] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.943624] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.943853] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.943962] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.944134] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.957250] [drm:drm_atomic_state_init] Allocated atomic state ffff880270bbd600
>[  294.957266] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff88027094f0c0 state to ffff880270bbd600
>[  294.957273] [drm:drm_atomic_get_crtc_state] Added [CRTC:26] ffff880274118800 state to ffff880270bbd600
>[  294.957276] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88027094f0c0 to [NOCRTC]
>[  294.957279] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88027094f0c0
>[  294.957282] [drm:drm_atomic_check_only] checking ffff880270bbd600
>[  294.957296] [drm:intel_plane_atomic_calc_changes] [CRTC:26] has [PLANE:25] with fb -1
>[  294.957299] [drm:intel_plane_atomic_calc_changes] [PLANE:25] visible 1 -> 0, off 1, on 0, ms 0
>[  294.957303] [drm:drm_atomic_commit] commiting ffff880270bbd600
>[  294.957364] [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
>[  294.957373] [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  294.957382] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270bbd600
>[  294.957386] [drm:drm_atomic_state_free] Freeing atomic state ffff880270bbd600
>[  294.957397] [drm:drm_atomic_state_init] Allocated atomic state ffff880270bbd600
>[  294.957401] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff88027094f480 state to ffff880270bbd600
>[  294.957406] [drm:drm_atomic_get_crtc_state] Added [CRTC:31] ffff880274119000 state to ffff880270bbd600
>[  294.957409] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88027094f480 to [NOCRTC]
>[  294.957411] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88027094f480
>[  294.957413] [drm:drm_atomic_check_only] checking ffff880270bbd600
>[  294.957417] [drm:intel_plane_atomic_calc_changes] [CRTC:31] has [PLANE:30] with fb -1
>[  294.957420] [drm:intel_plane_atomic_calc_changes] [PLANE:30] visible 1 -> 0, off 1, on 0, ms 0
>[  294.957422] [drm:drm_atomic_commit] commiting ffff880270bbd600
>[  294.957444] [drm:vlv_pipe_set_fifo_size] Pipe B FIFO split 511 / 511 / 511
>[  294.957452] [drm:vlv_update_wm] Setting FIFO watermarks - B: plane=447, cursor=63, sprite0=0, sprite1=0, SR: plane=0, cursor=0 level=0 cxsr=0
>[  294.957456] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880270bbd600
>[  294.957459] [drm:drm_atomic_state_free] Freeing atomic state ffff880270bbd600
>[  294.981061] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.981307] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.981751] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.981942] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  294.982073] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  294.982243] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[  297.745715] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  297.745748] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>

Actions: View

Attachments on bug 103472: 135084 | 135086

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.